A gate scanning circuit and method
By setting a normally open transistor and a ‘double-delete structure’ in the scanning circuit of the display panel, the problem of failure of transistors under high-level stress is solved, and the reliability and stability of the scanning circuit are improved.
Patent Information
- Application Number
- CN202211205072.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-28
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2042-09-28
AI Technical Summary
During the scanning process, the input high level of the transistor's gate driver circuit causes the transistor's gate to bear high level stress for a long time, especially in the high and low temperature reliability test, resulting in transistor failure.
By setting a normally open transistor in the scanning circuit and adopting a ‘double-delete structure’ at the input, the gate of the transistor only bears a high level of one row, reducing and sharing stress, thereby improving the reliability and stability of the scanning circuit.
It effectively reduces the stress of the transistor, avoids damage to the transistor by high potential, and improves the reliability and stability of the gate scanning circuit.
Smart Images
Figure CN115394232B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of display panels, and in particular to a gate scanning circuit and method. Background Art
[0002] The display panel usually operates in forward scanning or reverse scanning. However, when operating in one of the working states and then switching to another scanning working state, individual transistor stress abnormalities often occur, which can cause the gate circuit to be unable to pass on, resulting in display abnormalities.
[0003] For example, during the positive scan process, the high level of the input causes the gate of the transistor at the input end to be subjected to long-term high-level stress. Especially during high and low temperature reliability tests, this stress is aggravated, eventually leading to transistor failure.
[0004] Chinese patent CN 106452025 A discloses a technical solution for a switch having a normally-on transistor and a normally-off transistor. Therefore, it is possible to consider using a normally-on transistor to solve the problem of abnormal transistor stress. Summary of the invention
[0005] In the scanning process of the gate driving circuit of the existing display panel, the high level input will cause the high level of the input end to be subjected to high level stress for a long time, which will eventually cause the transistor to fail.
[0006] In view of the above problems, a gate scanning circuit and method are proposed. By setting a normally-on transistor in the scanning circuit, the gate of the transistor at the input end is only subjected to a high level of one row. By further adopting a "double deletion structure" at the input end, the stress of the transistor gate at the input end is further reduced and shared, thereby improving the reliability and stability of the gate scanning circuit.
[0007] In a first aspect, a gate scanning circuit is provided, which is used to form a display panel gate scanning circuit by cascading, comprising:
[0008] A first level input line, a second level input line, a third level input line, a first scan line, a second scan line, a third scan line, a fourth level input line, a fifth level input line, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and a pull-down unit;
[0009] A first level input line and a second level input line are connected to the gate of the first transistor and the gate of the second transistor respectively;
[0010] The first scan line and the third scan line are connected to the drain of the first transistor and the source of the second transistor respectively;
[0011] The source of the first transistor and the drain of the second transistor are connected together to form a first common point;
[0012] The fourth level input line and the fifth level input line are connected to the gate of the third transistor and the gate of the fourth transistor respectively;
[0013] The source of the third transistor and the drain of the fourth transistor are respectively connected to the first common point;
[0014] The drain of the third transistor and the source of the fourth transistor are connected together to form a second common point;
[0015] The gate of the fifth transistor, the first end of the first capacitor, and the first end of the pull-down unit are respectively connected to the second common point;
[0016] The source of the fifth transistor, the second end of the first capacitor, and the second end of the pull-down unit are connected together to form a third common point;
[0017] The second scanning line is connected to the third common point;
[0018] The third level input line is connected to a drain of the fifth transistor.
[0019] In combination with the gate scanning circuit of the present invention, in a first possible implementation manner, the scanning circuit further includes:
[0020] a sixth transistor;
[0021] The seventh transistor;
[0022] The first level input line is electrically connected to the gate of the first transistor and the gate of the sixth transistor respectively, and the source of the first transistor is electrically connected to the drain of the sixth transistor;
[0023] The second level input line is electrically connected to the gate of the second transistor and the gate of the seventh transistor respectively, and the drain of the second transistor is electrically connected to the source of the seventh transistor;
[0024] The source of the sixth transistor and the drain of the seventh transistor are electrically connected to the first common point respectively.
[0025] In combination with the first possible implementation manner of the present invention, in a second possible implementation manner, the fourth level input line and the fifth level input line respectively input a high level and a low level to the third transistor and the fourth transistor alternately in a frame unit.
[0026] In combination with the second possible implementation manner of the present invention, in a third possible implementation manner, the third transistor and the fourth transistor are normally-on transistors.
[0027] In a second aspect, a gate scanning method is provided, using the scanning circuit described in the first aspect, comprising:
[0028] During the forward scanning phase:
[0029] At the first moment, the first level input line is controlled to input a high level to the gate of the first transistor, so that the first transistor is turned on, and a high level and a low level are alternately input to the gate of the third transistor and the gate of the fourth transistor respectively in a frame unit through the fourth level input line and the fifth level input line, so that the gate of the third transistor and the fourth transistor are in a normally open state;
[0030] At the second moment, the third level input line is controlled to input a high level to the drain of the fifth transistor, so that the fifth transistor is turned on, and a high level and a low level are alternately input to the gate of the third transistor and the gate of the fourth transistor in frames through the fourth level input line and the fifth level input line, so that the gate of the third transistor and the fourth transistor are in a normally open state.
[0031] In conjunction with the scanning method described in the second aspect of the present invention, in a first possible implementation manner, the steps are:
[0032] Alternatingly inputting a high level and a low level to the gate of the third transistor and the gate of the fourth transistor in units of frames through the fourth level input line and the fifth level input line, so that the gate of the third transistor and the fourth transistor are in a normally open state, comprises:
[0033] In the first frame, a high level and a low level are respectively input to the gate of the third transistor and the gate of the fourth transistor through the fourth level input line and the fifth level input line, so that the gate of the third transistor and the fourth transistor are in a normally open state;
[0034] In the second frame, a low level and a high level are respectively input to the gate of the third transistor and the gate of the fourth transistor through the fourth level input line and the fifth level input line, so that the gate of the third transistor and the fourth transistor are in a normally open state.
[0035] In a third aspect, a gate scanning method is provided, using the scanning circuit described in the first aspect, comprising:
[0036] During the forward scan phase:
[0037] At the first moment, the first level input line is controlled to input a high level to the gate of the first transistor and the gate of the sixth transistor respectively, so that the first transistor and the sixth transistor are turned on, and a high level and a low level are input to the gate of the third transistor and the gate of the fourth transistor respectively in a frame unit through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally open state;
[0038] At the second moment, the third level input line is controlled to input a high level to the drain of the fifth transistor, so that the fifth transistor is turned on, and a high level and a low level are respectively input to the gate of the third transistor and the gate of the fourth transistor in units of frames through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally on state.
[0039] In conjunction with the scanning method described in the third aspect of the present invention, in a first possible implementation manner, the steps are:
[0040] Alternatingly inputting a high level and a low level to the gate of the third transistor and the gate of the fourth transistor in units of frames through the fourth level input line and the fifth level input line, so that the gate of the third transistor and the fourth transistor are in a normally open state, comprises:
[0041] In the first frame, a high level and a low level are respectively input to the gate of the third transistor and the gate of the fourth transistor through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state;
[0042] In the second frame, a low level and a high level are respectively input to the gate of the third transistor and the gate of the fourth transistor through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state.
[0043] In a fourth aspect, a gate scanning method is provided, using the scanning circuit described in the first aspect, comprising:
[0044] During the backsweep phase:
[0045] At the first moment, the second level input line is controlled to input a high level to the gate of the second transistor and the gate of the seventh transistor respectively, so that the second transistor and the seventh transistor are turned on, and a low level and a high level are input to the gate of the third transistor and the gate of the fourth transistor respectively in a frame unit through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally open state;
[0046] At the second moment, the third level input line is controlled to input a high level to the drain of the fifth transistor, so that the fifth transistor is turned on, and a low level and a high level are respectively input to the gate of the third transistor and the gate of the fourth transistor in units of frames through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally on state.
[0047] In conjunction with the scanning method described in the fourth aspect of the present invention, in a first possible implementation manner, the steps are:
[0048] Alternatingly inputting a high level and a low level to the gate of the third transistor and the gate of the fourth transistor in units of frames through the fourth level input line and the fifth level input line, so that the gate of the third transistor and the fourth transistor are in a normally open state, comprises:
[0049] In the first frame, a high level and a low level are respectively input to the gate of the third transistor and the gate of the fourth transistor through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state;
[0050] In the second frame, a low level and a high level are respectively input to the gate of the third transistor and the gate of the fourth transistor through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state.
[0051] The scanning circuit and scanning method described in the present invention are implemented by setting a normally-on transistor in the scanning circuit so that the gate of the transistor at the input end is only subjected to a high level of one row. By further adopting a "double deletion structure" at the input end, the stress of the gate of the transistor at the input end is further reduced and shared, thereby improving the reliability and stability of the gate scanning circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0053] Figure 1 It is a schematic diagram of a gate scanning circuit embodiment 1 of the present invention;
[0054] Figure 2 It is a schematic diagram of a gate scanning circuit embodiment 2 of the present invention;
[0055] Figure 3 It is a timing diagram of a gate scanning circuit in the prior art; DETAILED DESCRIPTION
[0056] The following will be combined with the accompanying drawings in the invention to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention.
[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.
[0058] In the scanning process of the gate driving circuit of the existing display panel, the high level input will cause the high level of the input end to be subjected to high level stress for a long time, which will eventually cause the transistor to fail.
[0059] In view of the above problems, a gate scanning circuit and method are proposed.
[0060] 1. Implementation Method of Gate Scan Circuit
[0061] Example 1: Adding two normally-on transistors between scan lines
[0062] A gate scanning circuit, used for forming a display panel gate scanning circuit by cascading, comprising:
[0063] A first level input line U2D, a second level input line D2U, a third level input line CK, a first scan line Gn-1, a second scan line, a third scan line, a fourth level input line VDD1, a fifth level input line VDD2, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C and a pull-down unit.
[0064] The first level input line U2D and the second level input line D2U are connected to the gate of the first transistor T1 and the gate of the second transistor T2, respectively. The first scanning line Gn-1 and the third scanning line Gn+1 are connected to the drain of the first transistor T1 and the source of the second transistor T2, respectively. The source of the first transistor T1 and the drain of the second transistor T2 are connected in common to form a first common point Q.
[0065] The fourth level input line VDD1 and the fifth level input line VDD2 are connected to the gate of the third transistor T3 and the gate of the fourth transistor T4, respectively. The source of the third transistor T3 and the drain of the fourth transistor T4 are connected to the first common point Q, respectively. The drain of the third transistor T3 and the source of the fourth transistor T4 are connected in common to form a second common point P. The gate of the fifth transistor T5, the first end of the first capacitor C, and the first end of the pull-down unit are connected in common to form a third common point H. The second scan line Gn is connected to the third common point H. The third level input line CK is connected to the drain of the fifth transistor T5.
[0066] The third transistor T3 and the fourth transistor T4 are normally-on transistors.
[0067] During the positive scan, U2D is at a high level and D2U is at a low level. During the positive scan stage, since U2D is normally at a high level, without adding normally-on transistors T3 and T4, the gate of transistor T1 is subjected to long-term high-level stress, especially during high and low temperature reliability tests. This stress is aggravated, and eventually leads to the failure of T1. The drain Q point of T1 has a high level for two lines in one frame. Figure 3 The level of the timing Qn point, Figure 3 This is a timing diagram of the prior art gate scanning circuit, please refer to Figure 1 , Figure 1 It is a schematic diagram of a gate scanning circuit embodiment 1 of the present invention; Figure 1 Normally open transistors T3 and T4 are added. Due to the high level of CK and the coupling effect of capacitor C, point P will be raised for the second time. The secondary raised voltage can usually reach (VGH-VGL) 30V or above. By setting the normally open transistors T3 and T4, the voltage at point P will not be transmitted to point Q, and the potential at point Q is close to the VGH potential. In this way, the stress on transistors T1 and T2 is greatly reduced, avoiding the high potential at point P from damaging the characteristics of T1 and T2.
[0068] Preferably, the fourth level input line VDD1 and the fifth level input line VDD2 respectively input a high level and a low level to the third transistor T3 and the fourth transistor T4 alternately in a frame unit.
[0069] In order to prevent the gates of the normally-on transistors T3 and T4 from being subjected to high-level stress for a long time, the normally-on transistors T3 and T4 are alternately driven at high and low levels, that is, the gate of the normally-on transistor T3 is at a high level and the gate of T4 is at a low level in one frame, and the gate of T3 is at a low level and the gate of T4 is at a high level in the next frame. By arranging the normally-on transistors in the scanning circuit, the gate of the transistor at the input end is subjected to only one row of high levels, thereby improving the reliability and stability of the scanning circuit.
[0070] Embodiment 2: Adding a transistor at the level input terminal
[0071] like Figure 2 , Figure 2 It is a schematic diagram of Embodiment 2 of the gate scanning circuit in the present invention; based on Embodiment 1, this embodiment adds transistors T6 and T7 at the level input end.
[0072] The scanning circuit also includes a sixth transistor T6 and a seventh transistor T7; the first level input line U2D is electrically connected to the gate of the first transistor T1 and the gate of the sixth transistor T6, respectively, and the source of the first transistor T1 is electrically connected to the drain of the sixth transistor T6; the second level input line D2U is electrically connected to the gate of the second transistor T2 and the gate of the seventh transistor T7, respectively, and the drain of the second transistor T2 is electrically connected to the source of the seventh transistor T7; the source of the sixth transistor T6 and the drain of the seventh transistor T7 are electrically connected to the first common point Q, respectively.
[0073] Preferably, the fourth level input line VDD1 and the fifth level input line VDD2 respectively input a high level and a low level to the third transistor T3 and the fourth transistor T4 alternately in a frame unit.
[0074] Preferably, the third transistor T3 , the fourth transistor T4 , the sixth transistor T6 , and the seventh transistor T7 are normally-on transistors.
[0075] During the positive scan, embodiment 1 adds normally-on transistors T3 and T4. Due to the high level of CK and the coupling effect of capacitor C, point P will be lifted for the second time. The secondary lift voltage can usually reach (VGH-VGL) 30V or above. By setting the normally-on transistors T3 and T4, the voltage at point P will not be transmitted to point Q, and the potential at point Q is close to the VGH potential, so the stress on transistors T1 and T2 is greatly reduced. In embodiment 2, transistors T6 and T7 are further added to the first level input line and the second level input line, that is, a dual-gate structure, which further reduces and shares the stress of transistors T1 and T2, and further avoids the high potential at point P from damaging the characteristics of T1 and T2, thereby further improving the reliability and stability of the gate drive circuit.
[0076] Preferably, the fourth level input line VDD1 and the fifth level input line VDD2 respectively input a high level and a low level to the third transistor T3 and the fourth transistor T4 alternately in a frame unit.
[0077] In Embodiment 2, in order to prevent the gates of the normally-on transistors T3 and T4 from being subjected to high-level stress for a long time, the normally-on transistors T3 and T4 are alternately driven at high and low levels, that is, the gate of the normally-on transistor T3 is at a high level and the gate of T4 is at a low level in one frame, and the gate of T3 is at a low level and the gate of T4 is at a high level in the next frame.
[0078] First gate scanning method implementation method
[0079] The scanning circuit in the gate scanning circuit implementation method includes the following steps:
[0080] During the forward scan phase:
[0081] At the first moment, the first level input line U2D is controlled to input a high level to the gate of the first transistor T1, so that the first transistor T1 is turned on, and high level and low level are alternately input to the gate of the third transistor T3 and the gate of the fourth transistor T4 in frames through the fourth level input line VDD1 and the fifth level input line VDD2, so that the gate of the third transistor T3 and the fourth transistor T4 are in a normally open state.
[0082] At the second moment, the third level input line CK is controlled to input a high level to the drain of the fifth transistor T5, so that the fifth transistor T5 is turned on, and a high level and a low level are alternately input to the gate of the third transistor T3 and the gate of the fourth transistor T4 in frames through the fourth level input line VDD1 and the fifth level input line VDD2, so that the gate of the third transistor T3 and the fourth transistor T4 are in a normally open state.
[0083] By making the normally-on transistors T3 and T4 in the normally-on state, the voltage at point P will not be transmitted to point Q, and the potential at point Q is close to the VGH potential. In this way, the stress on transistors T1 and T2 is greatly reduced, avoiding damage to the characteristics of T1 and T2 caused by the high potential at point P, thereby improving the stability of the scanning circuit.
[0084] Preferably, in order to prevent the gates of the normally-on transistors T3 and T4 from being subjected to high-level stress for a long time, the normally-on transistors T3 and T4 are alternately driven at high and low levels. Specifically,
[0085] In the first frame, a high level and a low level are input to the gate of the third transistor T3 and the gate of the fourth transistor T4 respectively through the fourth level input line VDD1 and the fifth level input line VDD2, so that the gate of the third transistor T3 and the fourth transistor T4 are in a normally open state;
[0086] In the second frame, a low level and a high level are input to the gate of the third transistor T3 and the gate of the fourth transistor T4 respectively through the fourth level input line VDD1 and the fifth level input line VDD2, so that the gate of the third transistor T3 and the fourth transistor T4 are in a normally open state.
[0087] That is, high level and low level are input alternately to the normally-on transistors T3 and T4 between the first frame and the second frame. The first frame may be the previous frame, and the second frame may be the next frame.
[0088] The second gate scanning method implementation method adopts a scanning circuit in a scanning circuit mode, wherein the scanning circuit includes:
[0089] During the forward scan phase:
[0090] At the first moment, the first level input line U2D is controlled to input a high level to the gate of the first transistor T1 and the gate of the sixth transistor T6, so that the first transistor T1 and the sixth transistor T6 are turned on, and the fourth level input line VDD1 and the fifth level input line VDD2 are used to input a high level and a low level to the gate of the third transistor T3 and the gate of the fourth transistor T4 in units of frames, so that the third transistor T3 and the fourth transistor T4 are in a normally open state.
[0091] At the second moment, the third level input line CK is controlled to input a high level to the drain of the fifth transistor T5, so that the fifth transistor T5 is turned on, and a high level and a low level are respectively input to the gate of the third transistor T3 and the gate of the fourth transistor T4 in frames through the fourth level input line VDD1 and the fifth level input line VDD2, so that the third transistor T3 and the fourth transistor T4 are in a normally on state.
[0092] Preferably, in order to prevent the gates of the normally-on transistors T3 and T4 from being subjected to high-level stress for a long time, the normally-on transistors T3 and T4 are alternately driven at high and low levels. Specifically,
[0093] In the first frame, a high level and a low level are input to the gate of the third transistor T3 and the gate of the fourth transistor T4 respectively through the fourth level input line VDD1 and the fifth level input line VDD2, so that the gate of the third transistor T3 and the fourth transistor T4 are in a normally open state;
[0094] In the second frame, a low level and a high level are input to the gate of the third transistor T3 and the gate of the fourth transistor T4 respectively through the fourth level input line VDD1 and the fifth level input line VDD2, so that the gate of the third transistor T3 and the fourth transistor T4 are in a normally open state.
[0095] That is, high level and low level are input alternately to the normally-on transistors T3 and T4 between the first frame and the second frame. The first frame may be the previous frame, and the second frame may be the next frame.
[0096] The third gate scanning method implementation method adopts the scanning circuit in the scanning circuit implementation method, including:
[0097] During the backsweep phase:
[0098] At the first moment, the second level input line D2U is controlled to input a high level to the gate of the second transistor T and the gate of the seventh transistor T, respectively, so that the second transistor T and the seventh transistor T are turned on, and a low level and a high level are input to the gate of the third transistor T and the gate of the fourth transistor T in units of frames through the fourth level input line VDD1 and the fifth level input line VDD2, respectively, so that the third transistor T and the fourth transistor T are in a normally open state;
[0099] At the second moment, the third level input line CK is controlled to input a high level to the drain of the fifth transistor T, so that the fifth transistor T is turned on, and a low level and a high level are respectively input to the gate of the third transistor T and the gate of the fourth transistor T in units of frames through the fourth level input line VDD1 and the fifth level input line VDD2, so that the third transistor T and the fourth transistor T are in a normally open state.
[0100] Preferably, in order to prevent the gates of the normally-on transistors T3 and T4 from being subjected to high-level stress for a long time, the normally-on transistors T3 and T4 are alternately driven at high and low levels. Specifically,
[0101] In the first frame, a high level and a low level are input to the gate of the third transistor T3 and the gate of the fourth transistor T4 respectively through the fourth level input line VDD1 and the fifth level input line VDD2, so that the gate of the third transistor T3 and the fourth transistor T4 are in a normally open state;
[0102] In the second frame, a low level and a high level are input to the gate of the third transistor T3 and the gate of the fourth transistor T4 respectively through the fourth level input line VDD1 and the fifth level input line VDD2, so that the gate of the third transistor T3 and the fourth transistor T4 are in a normally open state.
[0103] That is, high level and low level are input alternately to the normally-on transistors T3 and T4 between the first frame and the second frame. The first frame may be the previous frame, and the second frame may be the next frame.
[0104] The scanning circuit and scanning method described in the present invention are implemented by setting a normally-on transistor in the scanning circuit so that the gate of the transistor at the input end is only subjected to a high level of one row. By further adopting a "double deletion structure" at the input end, the stress of the gate of the transistor at the input end is further reduced and shared, thereby improving the reliability and stability of the gate scanning circuit.
[0105] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A gate scanning circuit, characterized in that: Used to form a display panel gate scanning circuit through cascading, including: A first level input line, a second level input line, a third level input line, a first scan line, a second scan line, a third scan line, a fourth level input line, a fifth level input line, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and a pull-down unit; A first level input line and a second level input line are connected to the gate of the first transistor and the gate of the second transistor respectively; The first scan line and the third scan line are connected to the drain of the first transistor and the source of the second transistor respectively; The source of the first transistor and the drain of the second transistor are connected together to form a first common point; The fourth level input line and the fifth level input line are connected to the gate of the third transistor and the gate of the fourth transistor respectively; The source of the third transistor and the drain of the fourth transistor are respectively connected to the first common point; The drain of the third transistor and the source of the fourth transistor are connected together to form a second common point; The gate of the fifth transistor, the first end of the first capacitor, and the first end of the pull-down unit are respectively connected to the second common point; The source of the fifth transistor, the second end of the first capacitor, and the second end of the pull-down unit are connected together to form a third common point; The second scanning line is connected to the third common point; The third level input line is connected to the drain of the fifth transistor; The third transistor and the fourth transistor are alternately driven at high and low levels, so that the second common contact voltage will not be transmitted to the first common contact, and the potential of the first common contact is close to the VGH potential, thereby reducing the stress on the first transistor and the second transistor, and preventing the high potential of the second common contact from causing characteristic damage to the first transistor and the second transistor.
2. The gate scanning circuit according to claim 1, characterized in that: The scanning circuit also includes: a sixth transistor; The seventh transistor; The first level input line is electrically connected to the gate of the first transistor and the gate of the sixth transistor respectively, and the source of the first transistor is electrically connected to the drain of the sixth transistor; The second level input line is electrically connected to the gate of the second transistor and the gate of the seventh transistor respectively, and the drain of the second transistor is electrically connected to the source of the seventh transistor; The source of the sixth transistor and the drain of the seventh transistor are electrically connected to the first common point respectively.
3. The gate scanning circuit according to claim 2, characterized in that: The fourth level input line and the fifth level input line respectively input a high level and a low level to the third transistor and the fourth transistor alternately in a frame unit.
4. The gate scanning circuit according to claim 3, characterized in that: The third transistor and the fourth transistor are normally-on transistors.
5. A gate scanning method, using the scanning circuit of any one of claims 1 to 4, characterized in that: include: During the forward scan phase: At the first moment, the first level input line is controlled to input a high level to the gate of the first transistor, so that the first transistor is turned on, and a high level and a low level are alternately input to the gate of the third transistor and the gate of the fourth transistor respectively in a frame unit through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally open state; At the second moment, the third level input line is controlled to input a high level to the drain of the fifth transistor, so that the fifth transistor is turned on, and a high level and a low level are alternately input to the gate of the third transistor and the gate of the fourth transistor in units of frames through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally on state.
6. The gate scanning method according to claim 5, characterized in that: The steps are: Alternatingly inputting a high level and a low level to the gate of the third transistor and the gate of the fourth transistor in units of frames through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state, comprises: In the first frame, a high level and a low level are respectively input to the gate of the third transistor and the gate of the fourth transistor through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state; In the second frame, a low level and a high level are respectively input to the gate of the third transistor and the gate of the fourth transistor through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state.
7. A gate scanning method, using the scanning circuit of any one of claims 1 to 4, characterized in that: include: During the forward scan phase: At the first moment, the first level input line is controlled to input a high level to the gate of the first transistor and the gate of the sixth transistor respectively, so that the first transistor and the sixth transistor are turned on, and a high level and a low level are input to the gate of the third transistor and the gate of the fourth transistor respectively in a frame unit through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally open state; At the second moment, the third level input line is controlled to input a high level to the drain of the fifth transistor, so that the fifth transistor is turned on, and a high level and a low level are respectively input to the gate of the third transistor and the gate of the fourth transistor in units of frames through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally on state.
8. The gate scanning method according to claim 7, characterized in that: The steps are: Alternatingly inputting a high level and a low level to the gate of the third transistor and the gate of the fourth transistor in units of frames through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state, comprises: In the first frame, a high level and a low level are respectively input to the gate of the third transistor and the gate of the fourth transistor through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state; In the second frame, a low level and a high level are respectively input to the gate of the third transistor and the gate of the fourth transistor through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state.
9. A gate scanning method, using the scanning circuit of any one of claims 1 to 4, characterized in that: include: During the backsweep phase: At the first moment, the second level input line is controlled to input a high level to the gate of the second transistor and the gate of the seventh transistor respectively, so that the second transistor and the seventh transistor are turned on, and a low level and a high level are input to the gate of the third transistor and the gate of the fourth transistor respectively in a frame unit through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally open state; At the second moment, the third level input line is controlled to input a high level to the drain of the fifth transistor to turn on the fifth transistor, and a low level and a high level are respectively input to the gate of the third transistor and the gate of the fourth transistor in units of frames through the fourth level input line and the fifth level input line to make the third transistor and the fourth transistor in a normally on state.
10. The gate scanning method according to claim 9, characterized in that: The steps are: Alternatingly inputting a high level and a low level to the gate of the third transistor and the gate of the fourth transistor in units of frames through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state, comprises: In the first frame, a high level and a low level are respectively input to the gate of the third transistor and the gate of the fourth transistor through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state; In the second frame, a low level and a high level are respectively input to the gate of the third transistor and the gate of the fourth transistor through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state.