Germanium-silicon heterojunction transistors and methods of making the same

Abstract

The application provides a germanium-silicon heterojunction transistor and a preparation method thereof. The preparation method comprises the following steps: providing a substrate, forming a first dielectric layer, a dummy gate and a second dielectric layer on the substrate; forming a third dielectric layer; forming a first germanium-silicon layer, a second polysilicon layer and a fourth dielectric layer; removing the second dielectric layer and the third dielectric layer; forming a fifth dielectric layer; removing the fifth dielectric layer on the upper surface of the dummy gate, the dummy gate and the first dielectric layer at the bottom of the dummy gate; forming a second germanium-silicon layer on the bottom wall of the convex groove; and forming a third polysilicon layer. The first germanium-silicon layer is first formed on the substrate at the side of the dummy gate, and then the second germanium-silicon layer is formed on the surface of the substrate after the dummy gate is removed. The germanium-silicon epitaxial layer is formed on the surface of the substrate in a segmented manner, the number of times that the germanium-silicon epitaxial layer undergoes a heat process for preparing other film layers is greatly reduced, diffusion of doped ions in the germanium-silicon epitaxial layer is avoided, and the electrical performance of the germanium-silicon heterojunction transistor is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a germanium-silicon heterojunction transistor and a preparation method thereof. BACKGROUND

[0002] After decades of development, the germanium-silicon heterojunction transistor (SiGe HBT) technology has been widely used in cellular phones, personal communication systems, wireless telephones, global positioning system receivers, wireless local area networks and industrial and medical fields. Therefore, the SiGe HBT technology has always been valued by researchers. Although the device performance of the SiGe HBT is excellent, the process is complex and the production cost is high, which has always restricted the development of such products. Therefore, the optimization of the device structure and the simplification of the process steps are the main research directions of the researchers.

[0003] The selective epitaxy technology of the SiGe layer is difficult and seriously restricts the development of the SiGe HBT. At present, in the process of preparing the HBT device, the SiGe epitaxial layer located on the surface of the substrate is greatly affected by the temperature factor, and the growth process of some film layers on the SiGe epitaxial layer mostly needs to be prepared / deposited in a high-temperature environment greater than 400°C, which is easy to cause the outward diffusion of the doping ions (such as boron ions) in the SiGe epitaxial layer, thereby affecting the performance of the HBT device, and even causing the failure of the HBT device. SUMMARY

[0004] The present application provides a germanium-silicon heterojunction transistor and a preparation method thereof, which can solve the problem that the SiGe epitaxial layer is affected by the process steps (thermal process) of other film layers of the device prepared by multiple high-temperature processes in the current preparation process of the SiGe HBT, thereby causing poor device performance.

[0005] In one aspect, the present application provides a preparation method of a germanium-silicon heterojunction transistor, comprising:

[0006] providing a substrate, a first dielectric layer, a first polysilicon layer and a second dielectric layer are formed on the substrate;

[0007] etching the second dielectric layer and the first polysilicon layer to form a pseudo gate, wherein the upper surface of the pseudo gate remains the second dielectric layer;

[0008] forming a third dielectric layer, the third dielectric layer covers the side surface of the pseudo gate;

[0009] removing the first dielectric layer on the substrate surface at the side of the pseudo gate;

[0010] forming a first germanium-silicon layer on the substrate surface at the side of the pseudo gate by a selective epitaxial growth process;

[0011] forming a second polysilicon layer, the second polysilicon layer covering the first germanium-silicon layer;

[0012] forming a fourth dielectric layer, the fourth dielectric layer covering the second polysilicon layer;

[0013] removing the second dielectric layer on the surface of the dummy gate and the third dielectric layer on the surface of the dummy gate, wherein the dummy gate and the second polysilicon layer, the fourth dielectric layer form an opening;

[0014] forming a fifth dielectric layer, the fifth dielectric layer filling the opening and covering the dummy gate and the fourth dielectric layer;

[0015] removing the fifth dielectric layer on the surface of the dummy gate, the dummy gate and the first dielectric layer at the bottom of the dummy gate, wherein the first germanium-silicon layer, the second polysilicon layer, the fourth dielectric layer and the fifth dielectric layer form a convex groove;

[0016] forming a second germanium-silicon layer at the bottom wall of the convex groove by a selective epitaxial growth process, the upper surface of the second germanium-silicon layer being flush with the upper surface of the first germanium-silicon layer;

[0017] forming a third polysilicon layer, the third polysilicon layer covering the fifth dielectric layer and filling the remaining space of the convex groove;

[0018] etching the third polysilicon layer, the fifth dielectric layer and the fourth dielectric layer, the second polysilicon layer and the first germanium-silicon layer on the side of the convex groove to the surface of the substrate, so that the side of the third polysilicon layer, the fifth dielectric layer and the fourth dielectric layer, the second polysilicon layer and the first germanium-silicon layer form a stepped topography.

[0019] Optionally, in the preparation method of the germanium-silicon heterojunction transistor, the first dielectric layer is a silicon oxide layer; the second dielectric layer is a silicon nitride layer; the third dielectric layer is a silicon nitride layer; the fourth dielectric layer is a silicon oxide layer; and the fifth dielectric layer is a silicon nitride layer.

[0020] Optionally, in the preparation method of the germanium-silicon heterojunction transistor, the second dielectric layer is formed by a plasma-enhanced chemical vapor deposition process; and the third dielectric layer is formed by a plasma-enhanced chemical vapor deposition process.

[0021] Optionally, in the preparation method of the germanium-silicon heterojunction transistor, the fifth dielectric layer is formed by a high-temperature furnace tube low-pressure chemical vapor deposition process, and the process temperature for forming the fifth dielectric layer is greater than 600°C.

[0022] Optionally, in the method for manufacturing the germanium-silicon heterojunction transistor, the step of removing the second dielectric layer on the upper surface of the dummy gate and the third dielectric layer on the side surface of the dummy gate comprises:

[0023] The second dielectric layer on the upper surface of the dummy gate is removed by using a dry etching process.

[0024] The third dielectric layer on the side surface of the dummy gate is removed by using a wet etching process.

[0025] Optionally, in the method for manufacturing the germanium-silicon heterojunction transistor, the step of removing the fifth dielectric layer on the upper surface of the dummy gate, the first dielectric layer on the bottom of the dummy gate and the dummy gate comprises:

[0026] The fifth dielectric layer on the upper surface of the dummy gate is removed by using a dry etching process.

[0027] The dummy gate is removed by using a dry etching process.

[0028] The first dielectric layer on the bottom of the dummy gate is removed by using a wet etching process.

[0029] Optionally, in the method for manufacturing the germanium-silicon heterojunction transistor, the step of etching the third polysilicon layer, the fifth dielectric layer and the fourth dielectric layer on the side of the convex groove, the second polysilicon layer, the first germanium-silicon layer to the surface of the substrate so that the side surfaces of the third polysilicon layer, the fifth dielectric layer and the fourth dielectric layer, the second polysilicon layer and the first germanium-silicon layer form a stepped topography comprises:

[0030] The third polysilicon layer, the fifth dielectric layer and the fourth dielectric layer on the side of the convex groove are etched to the surface of the second polysilicon layer.

[0031] The second polysilicon layer and the first germanium-silicon layer are etched to the surface of the substrate, wherein part of the surface of the second polysilicon layer on the side of the convex groove is not covered by the fourth dielectric layer.

[0032] Optionally, in the method for manufacturing the germanium-silicon heterojunction transistor, the thickness of the first germanium-silicon layer is The thickness of the second germanium-silicon layer is

[0033] Optionally, in the method for manufacturing the germanium-silicon heterojunction transistor, the first dielectric layer on the surface of the substrate on the side of the dummy gate is removed by using a wet etching process.

[0034] In another aspect, the embodiments of the present application also provide a germanium-silicon heterojunction transistor, comprising:

[0035] A substrate;

[0036] a first germanium silicon layer on the substrate surface;

[0037] a second polysilicon layer covering the first germanium silicon layer;

[0038] a fourth dielectric layer covering part of the surface of the second polysilicon layer;

[0039] a fifth dielectric layer covering the fourth dielectric layer and the inner surface of the fourth dielectric layer and the inner surface of the second polysilicon layer, wherein a convex groove is formed in the fifth dielectric layer, the fourth dielectric layer, the second polysilicon layer and the first germanium silicon layer;

[0040] a second germanium silicon layer covering the bottom wall of the convex groove, and the upper surface of the second germanium silicon layer is flush with the upper surface of the first germanium silicon layer;

[0041] a third polysilicon layer filling the remaining space of the convex groove and covering the upper surface of the fifth dielectric layer.

[0042] The technical scheme of the present application has at least the following advantages:

[0043] The present application first forms a first germanium silicon layer on the substrate on the side of the dummy gate, and then forms a second germanium silicon layer on the bottom wall of the convex groove after removing the dummy gate. The present application forms a germanium silicon epitaxial layer on the substrate surface in a segmented manner, greatly reduces the number of times the second germanium silicon layer at the bottom of the third polysilicon layer undergoes the heat process of preparing other film layers, thereby avoiding the diffusion of doped ions in the germanium silicon epitaxial layer, and improving the electrical performance and device reliability of the germanium silicon heterojunction transistor.

[0044] Further, the present application first forms a protective side wall on the side of the dummy gate using a third dielectric layer, then removes the third dielectric layer, and then re-forms a fifth dielectric layer on the side of the dummy gate, which ensures that the second germanium silicon layer is completely grown on the substrate surface during the process of forming the second germanium silicon layer by selective epitaxial growth process, avoids the case that the second germanium silicon layer is grown on the surface of the third dielectric layer, improves the crystal quality of the germanium silicon epitaxial layer, and further improves the electrical performance and device reliability of the germanium silicon heterojunction transistor. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the specific embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings without creative labor on the basis of these drawings.

[0046] Figure 1 is a flow chart of a preparation method of a germanium-silicon heterojunction transistor of an embodiment of the present application;

[0047] Figures 2-15 is a schematic diagram of a semiconductor structure in each process step of preparing a germanium-silicon heterojunction transistor of an embodiment of the present application;

[0048] In the drawings, the following reference signs are used:

[0049] 1-substrate, 101-shallow trench isolation structure, 2-first dielectric layer, 3-first polysilicon layer, 301-pseudo gate, 4-second dielectric layer, 5-third dielectric layer, 6-first germanium-silicon layer, 7-second polysilicon layer, 8-fourth dielectric layer, 9-fifth dielectric layer, 10-second germanium-silicon layer, 11-third polysilicon layer. DETAILED DESCRIPTION

[0050] The technical solutions in the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort belong to the scope of the present application.

[0051] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0052] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements, or it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0053] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0054] This application provides a method for fabricating a germanium-silicon heterojunction transistor. Please refer to [link / reference]. Figure 1 , Figure 1 This is a flowchart of a method for fabricating a germanium-silicon heterojunction transistor according to an embodiment of the present invention.

[0055] For details, please refer to Figures 2-15 , Figures 2-15 This is a schematic diagram of the semiconductor structure in each process step of the fabrication of a germanium-silicon heterojunction transistor according to an embodiment of the present invention.

[0056] The method for fabricating the germanium-silicon heterojunction transistor includes:

[0057] Step S1: As Figure 2 As shown, a substrate 1 is provided, on which a first dielectric layer 2, a first polycrystalline silicon layer 3, and a second dielectric layer 4 are formed. Specifically, the substrate 1 can be one of monocrystalline silicon, polycrystalline silicon, and amorphous silicon, and can also be gallium arsenide, gallium silicon compound, etc., which are not listed in this embodiment. In this embodiment, the first dielectric layer 2 can be a silicon oxide layer; the second dielectric layer 4 can be a silicon nitride layer. Further, in this embodiment, the second dielectric layer 4 can be formed using a plasma-enhanced chemical vapor deposition process. The substrate 1 can also have multiple shallow trench isolation structures 101 formed thereon.

[0058] Step S2: As Figure 3 As shown, the second dielectric layer 4 and the first polysilicon layer 3 are etched to form a dummy gate 301, wherein the upper surface of the dummy gate 301 retains the remaining second dielectric layer 4.

[0059] Step S3: As Figure 4 As shown, a third dielectric layer 5 is formed, which covers the side surface of the pseudogate 301. Specifically, the third dielectric layer 5 can be a silicon nitride layer. Furthermore, the third dielectric layer 5 can be formed using plasma-enhanced chemical vapor deposition (PECVD).

[0060] In this embodiment, the step of forming the third dielectric layer 5 may include: (1) firstly depositing an entire layer of the third dielectric layer 5, the third dielectric layer 5 covering the upper surface of the second dielectric layer 4, the side surface of the pseudogate 301 and the surface of the first dielectric layer 2; (2) then removing the third dielectric layer 5 on the upper surface of the second dielectric layer 4 and the upper surface of the first dielectric layer 2 using photolithography and etching processes, leaving only the third dielectric layer 5 on the side surface of the pseudogate 301 to form a protective sidewall.

[0061] Step S4: As Figure 5As shown, the first dielectric layer 2 on the surface of the substrate 1 on the pseudogate 301 side is removed. Specifically, in this embodiment, a wet etching process can be used to remove the first dielectric layer 2 on the surface of the substrate 1 on the pseudogate 301 side.

[0062] Step S5: As Figure 6 As shown, a first germanium-silicon layer 6 is formed on the surface of the substrate 1 on the pseudogate 301 side using a selective epitaxial growth process. Specifically, the thickness of the first germanium-silicon layer 6 is...

[0063] Step S6: As Figure 7 As shown, a second polysilicon layer 7 is formed, which covers the first germanium-silicon layer 6. Specifically, in this embodiment, a second polysilicon layer 7 covering the second dielectric layer 4, the third dielectric layer 5 (protective sidewall), and the first germanium-silicon layer 6 can be deposited first. Then, the second polysilicon layer 7 covering the surface of the second dielectric layer 4 and part of the surface of the third dielectric layer 5 (protective sidewall) is removed by photolithography and etching processes, leaving the second polysilicon layer 7 covering the first germanium-silicon layer 6.

[0064] Step S7: As Figure 7 As shown, a fourth dielectric layer 8 is formed, which covers the second polysilicon layer 7. Specifically, the fourth dielectric layer 8 can be a silicon oxide layer. In this embodiment, a fourth dielectric layer 8 covering the second dielectric layer 4, the third dielectric layer 5 (protective sidewall), and the second polysilicon layer 7 can be deposited first. Then, the fourth dielectric layer 8 on the surface of the second dielectric layer 4 and part of the surface of the third dielectric layer 5 (protective sidewall) is removed by photolithography and etching processes, leaving the fourth dielectric layer 8 covering the second polysilicon layer 7.

[0065] Step S8: As Figure 8 As shown, the second dielectric layer 4 on the upper surface of the pseudogate 301 and the third dielectric layer 5 on the side surface of the pseudogate 301 are removed, wherein an opening is formed between the pseudogate 301 and the second polysilicon layer 7 and the fourth dielectric layer 8. Specifically, the step of removing the second dielectric layer 4 on the upper surface of the pseudogate 301 and the third dielectric layer 5 on the side surface of the pseudogate 301 may include:

[0066] The second dielectric layer 4 on the upper surface of the pseudogate 301 is removed using a dry etching process;

[0067] The third dielectric layer 5 on the side surface of the pseudogate 301 is removed by a wet etching process.

[0068] Step S9: As Figure 9As shown, a fifth dielectric layer 9 is formed, which fills the opening and covers the dummy gate 301 and the fourth dielectric layer 8. Specifically, the fifth dielectric layer 9 can be a silicon nitride layer.

[0069] Preferably, the fifth dielectric layer 9 is formed by using a high-temperature furnace tube and a chemical vapor deposition process. In the process of forming the fifth dielectric layer 9 by using a high-temperature furnace tube and a low-pressure chemical vapor deposition process, the process temperature is greater than 600°C, for example, 650°C, 700°C, 750°C, etc.

[0070] In this application, the third dielectric layer 5 is first used to form a protective side wall on the side of the dummy gate 301, and then the third dielectric layer 5 is removed, and then the fifth dielectric layer 9 is formed on the side of the dummy gate 301 by using a high-temperature furnace tube and a low-pressure chemical vapor deposition process. This improves the crystal quality of the fifth dielectric layer 9 and ensures that the second germanium-silicon layer 10 is completely grown on the surface of the substrate 1 during the subsequent formation of the second germanium-silicon layer 10 by a selective epitaxial growth process. This avoids the growth of the second germanium-silicon layer 10 on the surface of the third dielectric layer 5, improves the overall crystal quality of the germanium-silicon epitaxial layer, and thus improves the electrical performance and device reliability of the germanium-silicon heterojunction transistor.

[0071] Step S10: removing the fifth dielectric layer 9 on the upper surface of the dummy gate 301, the dummy gate 301, and the first dielectric layer 2 at the bottom of the dummy gate 301. Specifically, the step of removing the fifth dielectric layer on the upper surface of the dummy gate, the dummy gate, and the first dielectric layer at the bottom of the dummy gate can specifically include:

[0072] As shown in Figure 10 , the fifth dielectric layer 9 on the upper surface of the dummy gate 301 is removed by a dry etching process;

[0073] As shown in Figure 11 , the dummy gate 301 is removed by a dry etching process;

[0074] As shown in Figure 12 , the first dielectric layer 2 at the bottom of the dummy gate 301 is removed by a wet etching process.

[0075] Among the first germanium-silicon layer 6, the second polysilicon layer 7, the fourth dielectric layer 8, and the fifth dielectric layer 9, a convex groove is formed.

[0076] Step S11: as shown in Figure 13 , a second germanium-silicon layer 10 is formed on the bottom wall of the convex groove by a selective epitaxial growth process, and the upper surface of the second germanium-silicon layer 10 is flush with the upper surface of the first germanium-silicon layer 6. Specifically, the thickness of the second germanium-silicon layer 10 can be

[0077] Step S12: as shown in the figure, a third polysilicon layer 11 is formed, which covers the fifth dielectric layer 9 and fills the remaining space of the convex-shaped trench. Figure 14

[0078] Step S13: as shown in the figure, the third polysilicon layer 11, the fifth dielectric layer 9 and the fourth dielectric layer 8, the second polysilicon layer 7, the first germanium-silicon layer 6 on the side of the convex-shaped trench are etched to the surface of the substrate 1, so that the side surfaces of the third polysilicon layer 11, the fifth dielectric layer 9 and the fourth dielectric layer 8, the second polysilicon layer 7, the first germanium-silicon layer 6 form a stepped topography. Figure 15

[0079] Specifically, the step of etching the third polysilicon layer 11, the fifth dielectric layer 9 and the fourth dielectric layer 8, the second polysilicon layer 7, the first germanium-silicon layer 6 on the side of the convex-shaped trench to the surface of the substrate 1, so that the side surfaces of the third polysilicon layer 11, the fifth dielectric layer 9 and the fourth dielectric layer 8, the second polysilicon layer 7, the first germanium-silicon layer 6 form a stepped topography comprises:

[0080] etching the third polysilicon layer 11, the fifth dielectric layer 9 and the fourth dielectric layer 8 on the side of the convex-shaped trench to the surface of the second polysilicon layer 7 by a photolithography process and an etching process;

[0081] etching the second polysilicon layer 7, the first germanium-silicon layer 6 to the surface of the substrate 1 by a photolithography process and an etching process, wherein part of the surface of the second polysilicon layer 7 on the side of the convex-shaped trench is not covered by the fourth dielectric layer 8. The part of the surface of the second polysilicon layer 7 exposed is used for subsequent electrode lead-out.

[0082] In the germanium-silicon heterojunction transistor prepared by the embodiment, the substrate 1 constitutes the collector of the device; the combination of the first germanium-silicon layer 6 and the second germanium-silicon layer 10 constitutes the base SiGe layer, and the second polysilicon layer 7 constitutes the emitter of the device.

[0083] ​​In the present application, the first germanium-silicon layer 6 mainly functions as a conductive layer of the outer base region, and the second germanium-silicon layer 10 is an important region of the base germanium-silicon epitaxial layer, which plays an important role in the normal operation of the device. The present application first forms the first germanium-silicon layer 6 on the substrate 1 on the side of the dummy gate 301, and then forms the second germanium-silicon layer 10 on the bottom wall of the convex-shaped trench after removing the dummy gate 301. The present application forms a combined germanium-silicon epitaxial layer on the surface of the substrate 1 in a segmented manner, greatly reduces the number of times that the second germanium-silicon layer 10 at the bottom of the third polysilicon layer 11 undergoes a thermal process for preparing other film layers (all film layers in the process steps after forming the first germanium-silicon layer 6 and in the process steps before forming the second germanium-silicon layer 10), and especially avoids the thermal process for preparing the fifth dielectric layer 9 at high temperature, thereby avoiding the diffusion of doped ions in the germanium-silicon epitaxial layer, and improving the electrical performance and device reliability of the germanium-silicon heterojunction transistor.

[0084] Based on the same inventive concept, the present application also provides a germanium-silicon heterojunction transistor, as shown in the accompanying drawings, which comprises: Figure 15

[0085] a substrate 1;

[0086] a first germanium-silicon layer 6 formed on the surface of the substrate 1;

[0087] a second polysilicon layer 7 covering part of the surface of the first germanium-silicon layer 6;

[0088] a fourth dielectric layer 8 covering part of the surface of the second polysilicon layer 7;

[0089] a fifth dielectric layer 9 covering the fourth dielectric layer 8, the inner side surface of the fourth dielectric layer 8, and the inner side surface of the second polysilicon layer 7, wherein the fifth dielectric layer 9, the fourth dielectric layer 8, the second polysilicon layer 7, and the first germanium-silicon layer 6 are formed with a convex-shaped trench; that is, the fifth dielectric layer 9 covers the fourth dielectric layer 8 and the side wall of the convex-shaped trench;

[0090] a second germanium-silicon layer 10 covering the bottom wall of the convex-shaped trench, and the upper surface of the second germanium-silicon layer 10 being flush with the upper surface of the first germanium-silicon layer 6;

[0091] a third polysilicon layer 11 filling the remaining space of the convex-shaped trench and covering the upper surface of the fifth dielectric layer 9.

[0092] ​Obviously, the above embodiments are merely example for clearly illustrating but not limitation to the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments are not required to be enumerated and it is impossible to enumerate all the embodiments. The changes or variations derived from the above are still within the protection scope of the present application.

Claims

1. A method of fabricating a germanium-silicon heterojunction transistor, comprising: The method comprises the following steps: providing a substrate, a first dielectric layer, a first polysilicon layer and a second dielectric layer are formed on the substrate; etching the second dielectric layer and the first polysilicon layer to form a dummy gate, wherein the upper surface of the dummy gate remains the second dielectric layer; forming a third dielectric layer covering the side surface of the dummy gate; removing the first dielectric layer on the substrate surface at the side of the dummy gate; forming a first germanium-silicon layer on the substrate surface at the side of the dummy gate by selective epitaxial growth process; forming a second polysilicon layer covering the first germanium-silicon layer; forming a fourth dielectric layer covering the second polysilicon layer; removing the second dielectric layer on the upper surface of the dummy gate and the third dielectric layer on the side surface of the dummy gate, wherein an opening is formed between the dummy gate and the second polysilicon layer and the fourth dielectric layer; forming a fifth dielectric layer filling the opening and covering the dummy gate and the fourth dielectric layer; removing the fifth dielectric layer on the upper surface of the dummy gate, the dummy gate and the first dielectric layer at the bottom of the dummy gate, wherein a convex groove is formed in the first germanium-silicon layer, the second polysilicon layer, the fourth dielectric layer and the fifth dielectric layer; forming a second germanium-silicon layer on the bottom wall of the convex groove by selective epitaxial growth process, the upper surface of the second germanium-silicon layer is flush with the upper surface of the first germanium-silicon layer; forming a third polysilicon layer covering the fifth dielectric layer and filling the remaining space of the convex groove; etching the third polysilicon layer, the fifth dielectric layer and the fourth dielectric layer, the second polysilicon layer and the first germanium-silicon layer on the side of the convex groove to the substrate surface, so that the side of the third polysilicon layer, the fifth dielectric layer and the fourth dielectric layer, the second polysilicon layer and the first germanium-silicon layer forms a stepped topography.

2. The method of fabricating a germanium-silicon heterojunction transistor of claim 1, wherein, The first dielectric layer is a silicon oxide layer; the second dielectric layer is a silicon nitride layer; the third dielectric layer is a silicon nitride layer; the fourth dielectric layer is a silicon oxide layer; and the fifth dielectric layer is a silicon nitride layer.

3. The method of fabricating a germanium-silicon heterojunction transistor according to claim 1 or 2, wherein The second dielectric layer is formed by plasma enhanced chemical vapor deposition process; and the third dielectric layer is formed by plasma enhanced chemical vapor deposition process.

4. The method of fabricating a germanium-silicon heterojunction transistor according to claim 1 or 2, wherein The fifth dielectric layer is formed by high-temperature furnace tube low-pressure chemical vapor deposition process, and the process temperature for forming the fifth dielectric layer is greater than 600 ℃.

5. The method of fabricating a germanium-silicon heterojunction transistor of claim 1, wherein, The step of removing the second dielectric layer on the upper surface of the dummy gate and the third dielectric layer on the side surface of the dummy gate comprises: the second dielectric layer on the upper surface of the dummy gate is removed by dry etching process; the third dielectric layer on the side surface of the dummy gate is removed by wet etching process.

6. The method of fabricating a germanium-silicon heterojunction transistor of claim 1, wherein, The step of removing the fifth dielectric layer on the upper surface of the dummy gate, the dummy gate and the first dielectric layer at the bottom of the dummy gate comprises: the fifth dielectric layer on the upper surface of the dummy gate is removed by dry etching process; the dummy gate is removed by dry etching process; the first dielectric layer at the bottom of the dummy gate is removed by wet etching process.

7. The method of fabricating a germanium-silicon heterojunction transistor of claim 1, wherein, The step of etching the third polysilicon layer, the fifth dielectric layer and the fourth dielectric layer, the second polysilicon layer, the first germanium-silicon layer to the surface of the substrate on the side of the convex-shaped trench, so that the side surfaces of the third polysilicon layer, the fifth dielectric layer and the fourth dielectric layer, the second polysilicon layer, the first germanium-silicon layer form a stepped topography, comprises: etching the third polysilicon layer, the fifth dielectric layer and the fourth dielectric layer on the side of the convex-shaped trench to the surface of the second polysilicon layer; etching the second polysilicon layer, the first germanium-silicon layer to the surface of the substrate, wherein part of the surface of the second polysilicon layer on the side of the convex-shaped trench is not covered by the fourth dielectric layer.

8. The method of fabricating a germanium-silicon heterojunction transistor of claim 1, wherein, a thickness of the first germanium silicon layer is a thickness of the second germanium silicon layer is 9. The method of fabricating a germanium-silicon heterojunction transistor of claim 1, wherein, The first dielectric layer on the surface of the substrate on the side of the pseudo-gate is removed by a wet etching process.

10. The germanium-silicon heterojunction transistor produced according to the method of any one of claims 1 to 9, characterized in that Comprise: a substrate; a first germanium-silicon layer on the surface of the substrate; a second polysilicon layer covering the first germanium-silicon layer; a fourth dielectric layer covering part of the surface of the second polysilicon layer; a fifth dielectric layer covering the fourth dielectric layer, the inner side surface of the fourth dielectric layer and the inner side surface of the second polysilicon layer, wherein the fifth dielectric layer, the fourth dielectric layer, the second polysilicon layer and the first germanium-silicon layer form a convex-shaped trench therein; a second germanium-silicon layer covering the bottom wall of the convex-shaped trench, and the upper surface of the second germanium-silicon layer is flush with the upper surface of the first germanium-silicon layer; a third polysilicon layer filling the remaining space of the convex-shaped trench and covering the upper surface of the fifth dielectric layer.

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