Undervoltage lockout circuit and method under high voltage

Abstract

The present invention relates to an undervoltage lockout circuit and method under high voltage. The circuit of the present invention comprises a PNP transistor QP1, a PNP transistor QP2, a PMOS transistor MP1, a PMOS transistor MP2, a PMOS transistor MP3, a PMOS transistor MP4, a PMOS transistor MP5, an NMOS transistor MN1, an NMOS transistor MN2, an NMOS transistor MN3, a power supply VCC, a diode D1, an NPN transistor QN1, an NPN transistor QN2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a resistor R6. The present invention can generate a reference voltage and a bias current by itself, and the hysteresis voltage has a small drift with temperature, and the chip start-up voltage is more accurate, and can be used as an independent module.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit power management, and in particular relates to an undervoltage lockout circuit and method under high voltage. Background Art

[0002] In the field of integrated circuits, the stability of power supply voltage is particularly important. In order to ensure that the chip can still work normally when the power supply voltage fluctuates, it is necessary to integrate an undervoltage lockout circuit inside the chip to monitor the power supply voltage, thereby improving the reliability and stability of the circuit. Undervoltage lockout (UVLO for short) is a low voltage shutdown, which is a protection mode when the power supply voltage is lower than the chip start-up voltage. When the power supply voltage is lower than the preset value set by the UVLO circuit, the chip is turned off to ensure that the chip is not damaged when the supply voltage is insufficient, and the purpose of the hysteresis function is to ensure that the noise jitter on the signal will not cause chip system failure. Therefore, the research on undervoltage lockout circuits, especially the application requirements of undervoltage lockout under high voltage, has become an important part of integrated circuits and various power management chips.

[0003] The reference voltage source and bias current required in the traditional undervoltage lockout circuit must be obtained from an external module. The module cannot be called separately to monitor the power supply voltage, resulting in an increase in the number of tubes, an increase in chip area, and an increase in cost. When the voltage is too low and the chip system is shut down, the external reference power supply and bias current modules may work abnormally, causing the comparator of the traditional undervoltage lockout circuit module to fail to work properly. Under the influence of transistor parasitic parameters and temperature drift, the comparator hysteresis will also drift, causing the undervoltage lockout threshold point to drift, and the UVLO outputs an error signal, thereby affecting the locking and monitoring of the power supply voltage by the entire circuit, and further affecting the reliability of the entire chip. At present, some undervoltage lockout circuits have a simple structure, but ignore the circuit power consumption, resulting in high power consumption when the system is working normally; some undervoltage lockout circuits do not require external reference and bias circuits, but do not have good temperature characteristics, which reduces power efficiency, increases the chip heat dissipation burden, and affects system stability. In addition, with the increasing demand for integrated circuit chip applications, the monitoring of system power stability under high voltage also poses new challenges. Summary of the invention

[0004] In order to solve the above problems existing in the background technology, the present invention provides an under-voltage lockout circuit and method under high voltage, which can self-generate reference voltage and bias current, and the hysteresis voltage drifts little with temperature, and the chip start-up voltage is more accurate, and can be used as an independent module.

[0005] The technical solution of the present invention is: the present invention is an undervoltage lockout circuit under high voltage, which is special in that: the circuit includes a PNP transistor QP1, a PNP transistor QP2, a PMOS transistor MP1, a PMOS transistor MP2, a PMOS transistor MP3, a PMOS transistor MP4, a PMOS transistor MP5, an NMOS transistor MN1, an NMOS transistor MN2, an NMOS transistor MN3, a power supply VCC, a diode D1, an NPN transistor QN1, an NPN transistor QN2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a resistor R6, the emitter of the PNP transistor QP2 is connected to the power supply VCC, and the PNP transistor The base and collector of QP2 are short-circuited and then connected to the base of the PNP transistor QP1, and are also connected to the source and substrate of the PMOS transistor MP2; the emitter of the PNP transistor QP1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the power supply VCC; the collector of the PNP transistor QP1 is connected to the source and substrate of the PMOS transistor MP1, the gate of the PMOS transistor MP1 is connected to the gate and drain of the PMOS transistor MP2, the gate and drain of the PMOS transistor MP2 are simultaneously connected to one end of the resistor R3, and the other end of the resistor R3 is grounded; the gate and drain of the NMOS transistor MN1 are short-circuited and connected to the drain of the PMOS transistor MP1, and are also connected to the gate of the NMOS transistor MN2, and the NMOS transistor MN1 is connected to the gate of the NMOS transistor MN2. The source and substrate of the NMOS tube MN2 are short-circuited, and the positive electrode of the diode D1 is connected at the same time. The negative electrode of the diode D1 is connected to the collector and base of the NPN transistor QN1. The emitter of the NPN transistor QN1 is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded. The substrate and source of the NMOS tube MN2 are short-circuited, and the source and substrate of the PMOS tube MP3 are connected at the same time. The gate and drain of the PMOS tube MP3 are short-circuited, and one end of the resistor R4 is connected at the same time. The other end of the resistor R4 is grounded. The gate and drain of the PMOS tube MP2 are short-circuited, and the gate of the PMOS tube MP4 is connected at the same time. The source and substrate of the PMOS tube MP4 are short-circuited to one end of the resistor R6. The other end of the resistor R6 is connected to the power supply VCC. The drain of the S transistor MP4 is connected to the source and substrate of the PMOS transistor MP5 and serves as the UVLO output port of this circuit. The gate of the PMOS transistor MP5 is connected to the source and substrate of the NMOS transistor MN2. The drain of the PMOS transistor MP5 is grounded. The UVLO output port is connected to the collector of the NPN transistor QN2 and the gate of the NMOS transistor MN3. The emitter of the NPN transistor QN2 is grounded. The base of the NPN transistor QN2 is connected to the base and collector of the NPN transistor QN1. The base of the NPN transistor QN2 is connected to one end of the resistor R5 at the same time. The other end of the resistor R5 is connected to the drain of the NMOS transistor MN3. The substrate and source of the NMOS transistor MN3 are grounded.

[0006] Furthermore, the PMOS tube MP1 , the PMOS tube MP2 , the PMOS tube MP4 , and the PMOS tube MP5 are high-voltage PMOS tubes, and the PMOS tube MP3 is a common PMOS tube.

[0007] Furthermore, the NMOS tube MN1 and the NMOS tube MN2 are high-voltage NMOS tubes, and the NMOS tube MN3 is a common NMOS tube.

[0008] A method for implementing the above-mentioned undervoltage lockout circuit under high voltage, the special feature of which is that the method comprises the following steps:

[0009] 1) The branch composed of the PNP transistor QP2, the PMOS transistor MP2 and the resistor R3 is a sampling circuit for the power supply VCC input. In this branch, the input VCC voltage signal is converted into a current signal, and then copied to the branch where the resistor R1 and the branch where the resistor R5 are located through the current mirror structure. The common source connection with source negative feedback composed of the resistor R1, the PNP transistor QP1 and the PMOS transistor MP1 will limit the speed of change of the copied current;

[0010] 2) When the power supply VCC voltage is greater than the UVLO start voltage and the input VCC starts to rise, the PNP transistor QP2, the PMOS transistor MP2, and the resistor R3 branch provide bias current for the branches on both sides. The PMOS transistor MP3 acts as a current mirror load. This branch provides a bias voltage to the PMOS transistor MP5. During normal operation, the PMOS transistor MP5 is turned off. When the current provided is large enough, the PMOS transistor MP4 is turned on first, the base voltage of the NPN transistor QN1 is greater than the turn-on voltage of the NPN transistor QN2, the NPN transistor QN2 is turned on, and the output voltage UVLO will be pulled down to 0V. At this time, the NMOS transistor MN3 is turned off, and this signal indicates that the chip power supply is established.

[0011] 3) When the power supply VCC voltage is lower than the UVLO start voltage, the PNP transistor QP2, PMOS transistor MP2, and resistor R3 branch provide a bias current reduction for the left resistor R1 branch, the base voltage of the NPN transistor QN1 is lower than the turn-on voltage of the NPN transistor QN2, the NPN transistor QN2 is turned off first, the output voltage UVLO is high, and the NMOS transistor MN3 is turned on;

[0012] 4) The circuit composed of NMOS tube MN3 and resistor R5 sets a hysteresis voltage for UVLO to prevent the input signal from jittering near the UVLO start voltage. The output voltage UVLO can only output a high level after the VCC voltage is lower than the UVLO start voltage.

[0013] The present invention provides an undervoltage lockout circuit and method under high voltage, which is based on the BCD process, has a structure with a reference voltage and bias current, does not require an additional sub-circuit, and can be called separately to monitor the power supply voltage, so that the undervoltage lockout circuit structure is simple, the number of transistors is reduced, the chip area is saved, and the cost is saved. The PNP transistor QP2 and the NPN transistor QN1 are connected as diodes, and high-order temperature compensation is performed on the reference. The NPN transistor QN1 and the NPN transistor QN2 use the same type of tube to reduce the threshold drift caused by temperature changes on the NPN transistor QN2, effectively reduce the hysteresis voltage drift, and the resistor R2 resistance can offset the temperature The influence of the change in resistor R3 is affected to a certain extent, so that the undervoltage lockout circuit opening voltage is more accurate. In addition, the present invention does not use a hysteresis comparator to generate a hysteresis signal to prevent signal jitter, and does not need to control the flipping speed and accuracy of the comparator, thereby saving chip power consumption and avoiding the drift of the hysteresis of the comparator under the influence of transistor parasitic parameters and temperature drift, causing the locking point to drift, thereby affecting the locking and monitoring of the power supply voltage by the entire circuit.

[0014] The circuit of the present invention does not require external reference voltage and bias current, and introduces high-order temperature compensation, so that the threshold voltage and hysteresis are more stable, and the reliability of the module circuit is improved. The circuit has the advantages of simple structure, small area, low power consumption, accurate threshold voltage, low temperature sensitivity, etc., and can be called as an independent module. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a circuit schematic diagram of the present invention. DETAILED DESCRIPTION

[0016] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0017] See also Figure 1The structure of the specific embodiment of the under-voltage lockout circuit under high voltage of the present invention includes a PNP transistor QP1, a PNP transistor QP2, a PMOS transistor MP1, a PMOS transistor MP2, a PMOS transistor MP3, a PMOS transistor MP4, a PMOS transistor MP5, an NMOS transistor MN1, an NMOS transistor MN2, an NMOS transistor MN3, a power supply VCC, a diode D1, an NPN transistor QN1, an NPN transistor QN2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a resistor R6, the emitter of the PNP transistor QP2 is connected to the power supply VCC, the base and the collector of the PNP transistor QP2 are short-circuited and then connected to The base of the PNP transistor QP1 is connected to the source and substrate of the PMOS transistor MP2; the emitter of the PNP transistor QP1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the power supply VCC; the collector of the PNP transistor QP1 is connected to the source and substrate of the PMOS transistor MP1, the gate of the PMOS transistor MP1 is connected to the gate and drain of the PMOS transistor MP2, the gate and drain of the PMOS transistor MP2 are connected to one end of the resistor R3, and the other end of the resistor R3 is grounded; the gate and drain of the NMOS transistor MN1 are short-circuited to the drain of the PMOS transistor MP1, and are connected to the gate of the NMOS transistor MN2, and the source and substrate of the NMOS transistor MN1 are short-circuited. At the same time, the anode of diode D1 is connected, the cathode of diode D1 is connected to the collector and base of NPN transistor QN1, the emitter of NPN transistor QN1 is connected to one end of resistor R2, the other end of resistor R2 is grounded, the substrate and source of NMOS tube MN2 are short-circuited, and the source and substrate of PMOS tube MP3 are connected at the same time, the gate and drain of PMOS tube MP3 are short-circuited, and one end of resistor R4 is connected at the same time, the other end of resistor R4 is grounded, the gate and drain of PMOS tube MP2 are short-circuited, and the gate of PMOS tube MP4 is connected at the same time, the source and substrate of PMOS tube MP4 are short-circuited to one end of resistor R6, the other end of resistor R6 is connected to power supply VCC, PMOS tube MP The drain of 4 is connected to the source and substrate of the PMOS tube MP5 and serves as the UVLO output port of this circuit. The gate of the PMOS tube MP5 is connected to the source and substrate of the NMOS tube MN2. The drain of the PMOS tube MP5 is grounded. The UVLO output port is connected to the collector of the NPN transistor QN2 and the gate of the NMOS tube MN3. The emitter of the NPN transistor QN2 is grounded. The base of the NPN transistor QN2 is connected to the base and collector of the NPN transistor QN1. The base of the NPN transistor QN2 is connected to one end of the resistor R5 at the same time. The other end of the resistor R5 is connected to the drain of the NMOS tube MN3. The substrate and source of the NMOS tube MN3 are grounded. Among them,

[0018] The PMOS tube MP1 , the PMOS tube MP2 , the PMOS tube MP4 , and the PMOS tube MP5 are high-voltage PMOS tubes, and the PMOS tube MP3 is a common PMOS tube.

[0019] The NMOS tube MN1 and the NMOS tube MN2 are high-voltage NMOS tubes, and the NMOS tube MN3 is a common NMOS tube.

[0020] The voltage of the power supply VCC can reach 80V. In the high-voltage circuit, all MOS tubes are high-voltage tubes. In this circuit, the branch composed of PNP transistor QP2, PMOS tube MP2 and resistor R3 is the sampling circuit of the power supply VCC input. In this branch, the voltage signal of the input power supply VCC will be converted into a current signal, and then copied to the branch where resistor R1 and resistor R5 are located through the current mirror structure. PNP transistor QP2 and NPN transistor QN1 are connected as diodes to perform high-order temperature compensation on the reference. The common source connection method with source negative feedback formed by resistor R1, PNP transistor QP1 and PMOS tube MP1 will limit the speed of the copied current change to a certain extent. The same applies to resistor R6 and PMOS tube MP4. Using the same type of tube for NPN transistor QN1 and NPN transistor QN2 can reduce the threshold drift effect caused by temperature change on NPN transistor QN2. The resistance of resistor R2 can offset the influence of temperature resistance on R3 to a certain extent, making the resistance more accurate.

[0021] When the UVLO circuit is enabled, the PMOS tube MP5 is in the off state. When the power supply VCC voltage is greater than the UVLO start voltage and the input power supply VCC begins to rise, the branch formed by the PNP transistor QP2, the PMOS tube MP2 and the resistor R3 provides bias current for the branches on both sides. The PMOS tube MP3 acts as a current mirror load. This branch provides bias voltage to the PMOS tube MP5. During normal operation, the PMOS tube MP5 is turned off. When the current provided is large enough, the PMOS tube MP4 is turned on first, the base voltage of the NPN transistor QN1 is greater than the turn-on voltage of the NPN transistor QN2, the NPN transistor QN2 is turned on, and the output voltage UVLO will be pulled down to 0V. At this time, the NMOS tube MN3 is turned off, and this signal indicates that the chip power supply has been established. When the power supply VCC voltage is lower than the UVLO start voltage, the branch formed by the PNP transistor QP2, the PMOS transistor MP2 and the resistor R3 provides a bias current reduction for the left resistor R1 branch, the base voltage of the NPN transistor QN1 is lower than the turn-on voltage of the NPN transistor QN2, the NPN transistor QN2 is turned off first, the output voltage UVLO is high, the NMOS transistor MN3 is turned on, and the circuit formed by the NMOS transistor MN3 and the resistor R5 sets a hysteresis voltage for UVLO to prevent the input signal from jittering near the UVLO start voltage. The output voltage UVLO can only output a high level when the power supply VCC voltage is lower than the UVLO start voltage.

[0022] The present invention also provides a method for under-voltage lockout under high voltage, and a preferred implementation method thereof is implemented by the following steps:

[0023] 1) The branch composed of the PNP transistor QP2, the PMOS transistor MP2 and the resistor R3 is a sampling circuit for the power supply VCC input. In this branch, the input VCC voltage signal is converted into a current signal, and then copied to the branch where the resistor R1 and the branch where the resistor R5 are located through the current mirror structure. The resistor R1, the PNP transistor QP1 and the PMOS transistor MP1 are similar to the common source connection with source negative feedback, which will limit the speed of the copied current change to a certain extent;

[0024] 2) When the power supply VCC voltage is greater than the UVLO start voltage and the input VCC starts to rise, the PNP transistor QP2, the PMOS transistor MP2, and the resistor R3 branch provide bias current for the branches on both sides. The PMOS transistor MP3 acts as a current mirror load. This branch provides a bias voltage to the PMOS transistor MP5. During normal operation, the PMOS transistor MP5 is turned off. When the current provided is large enough, the PMOS transistor MP4 is turned on first, the base voltage of the NPN transistor QN1 is greater than the turn-on voltage of the NPN transistor QN2, the NPN transistor QN2 is turned on, and the output voltage UVLO will be pulled down to 0V. At this time, the NMOS transistor MN3 is turned off, and this signal indicates that the chip power supply is established.

[0025] 3) When the power supply VCC voltage is lower than the UVLO start voltage, the PNP transistor QP2, PMOS transistor MP2, and resistor R3 branch provide a bias current reduction for the left resistor R1 branch, the base voltage of the NPN transistor QN1 is lower than the turn-on voltage of the NPN transistor QN2, the NPN transistor QN2 is turned off first, the output voltage UVLO is high, and the NMOS transistor MN3 is turned on;

[0026] 4) The circuit composed of NMOS tube MN3 and resistor R5 sets a hysteresis voltage for UVLO to prevent the input signal from jittering near the UVLO start voltage. The output voltage UVLO can only output a high level after the VCC voltage is lower than the UVLO start voltage.

[0027] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An undervoltage lockout circuit under high voltage, characterized in that: The circuit comprises a PNP transistor QP1, a PNP transistor QP2, a PMOS transistor MP1, a PMOS transistor MP2, a PMOS transistor MP3, a PMOS transistor MP4, a PMOS transistor MP5, an NMOS transistor MN1, an NMOS transistor MN2, an NMOS transistor MN3, a power source VCC, a diode D1, an NPN transistor QN1, an NPN transistor QN2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a resistor R6. The emitter of the PNP transistor QP2 is connected to the power source VCC, the base and the collector of the PNP transistor QP2 are short-circuited and then connected to the base of the PNP transistor QP1, and at the same time connected to the PMOS transistor MP2. The source and substrate of the PNP transistor QP1; the emitter of the PNP transistor QP1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the power supply VCC; the collector of the PNP transistor QP1 is connected to the source and substrate of the PMOS tube MP1, the gate of the PMOS tube MP1 is connected to the gate and drain of the PMOS tube MP2, the gate and drain of the PMOS tube MP2 are simultaneously connected to one end of the resistor R3, and the other end of the resistor R3 is grounded; the gate and drain of the NMOS tube MN1 are short-circuited to the drain of the PMOS tube MP1, and are simultaneously connected to the gate of the NMOS tube MN2, the source and substrate of the NMOS tube MN1 are short-circuited, and are simultaneously connected to the anode of the diode D1, and the The negative electrode is connected to the collector and base of the NPN transistor QN1, the emitter of the NPN transistor QN1 is connected to one end of the resistor R2, the other end of the resistor R2 is grounded, the substrate and source of the NMOS tube MN2 are short-circuited, and the source and substrate of the PMOS tube MP3 are connected at the same time, the gate and drain of the PMOS tube MP3 are short-circuited, and one end of the resistor R4 is connected at the same time, the other end of the resistor R4 is grounded, the gate and drain of the PMOS tube MP2 are short-circuited, and the gate of the PMOS tube MP4 is connected at the same time, the source and substrate of the PMOS tube MP4 are short-circuited to one end of the resistor R6, the other end of the resistor R6 is connected to the power supply VCC, and the drain of the PMOS tube MP4 is connected to the PMOS The source and substrate of the PMOS transistor MP5 are used as the UVLO output port of this circuit. The gate of the PMOS transistor MP5 is connected to the source and substrate of the NMOS transistor MN2. The drain of the PMOS transistor MP5 is grounded. The UVLO output port is connected to the collector of the NPN transistor QN2 and the gate of the NMOS transistor MN3. The emitter of the NPN transistor QN2 is grounded. The base of the NPN transistor QN2 is connected to the base and collector of the NPN transistor QN1. The base of the NPN transistor QN2 is connected to one end of the resistor R5 at the same time. The other end of the resistor R5 is connected to the drain of the NMOS transistor MN3. The substrate and source of the NMOS transistor MN3 are grounded.

2. The undervoltage lockout circuit under high voltage according to claim 1, characterized in that: The PMOS tube MP1, the PMOS tube MP2, the PMOS tube MP4 and the PMOS tube MP5 are high-voltage PMOS tubes, and the PMOS tube MP3 is a common PMOS tube.

3. The under-voltage lockout circuit under high voltage according to claim 1, characterized in that: The NMOS tube MN1 and the NMOS tube MN2 are high-voltage NMOS tubes, and the NMOS tube MN3 is a common NMOS tube.

4. A method for implementing the undervoltage lockout circuit under high voltage as claimed in claim 1, characterized in that: The method comprises the following steps: 1) The branch composed of the PNP transistor QP2, the PMOS transistor MP2 and the resistor R3 is a sampling circuit for the power supply VCC input. In this branch, the input VCC voltage signal is converted into a current signal, and then copied to the branch where the resistor R1 and the branch where the resistor R5 are located through the current mirror structure. The common source connection with source negative feedback composed of the resistor R1, the PNP transistor QP1 and the PMOS transistor MP1 will limit the speed of change of the copied current; 2) When the power supply VCC voltage is greater than the UVLO start voltage and the input VCC starts to rise, the PNP transistor QP2, the PMOS transistor MP2, and the resistor R3 branch provide bias current for the branches on both sides. The PMOS transistor MP3 acts as a current mirror load. This branch provides a bias voltage to the PMOS transistor MP5. During normal operation, the PMOS transistor MP5 is turned off. When the current provided is large enough, the PMOS transistor MP4 is turned on first, the base voltage of the NPN transistor QN1 is greater than the turn-on voltage of the NPN transistor QN2, the NPN transistor QN2 is turned on, and the output voltage UVLO will be pulled down to 0V. At this time, the NMOS transistor MN3 is turned off, and this signal indicates that the chip power supply is established. 3) When the power supply VCC voltage is lower than the UVLO start voltage, the PNP transistor QP2, PMOS transistor MP2, and resistor R3 branch provide a bias current reduction for the left resistor R1 branch, the base voltage of the NPN transistor QN1 is lower than the turn-on voltage of the NPN transistor QN2, the NPN transistor QN2 is turned off first, the output voltage UVLO is high, and the NMOS transistor MN3 is turned on; 4) The circuit composed of NMOS tube MN3 and resistor R5 sets a hysteresis voltage for UVLO to prevent the input signal from jittering near the UVLO start voltage. The output voltage UVLO can only output a high level after the VCC voltage is lower than the UVLO start voltage.

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