Method of manufacturing a semiconductor device
By forming a shielding layer to block the second type of region during the semiconductor device fabrication process, the problem of over-etching of the sidewalls of adjacent type regions is solved, thereby improving the performance and yield of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2021-05-28
- Publication Date
- 2026-06-23
AI Technical Summary
During the fabrication of semiconductor devices, over-etching can occur on the sidewalls of adjacent regions, affecting the yield of the semiconductor.
By forming a mask layer on the surface of the first type region and a shielding layer on its sidewall to shield part of the surface of the second type region, the second type region is etched using the mask layer and the shielding layer as a mask. The width of the shielding layer is greater than the maximum lateral erosion width of the second type region. Subsequently, the shielding layer is removed to expose the shielded part of the second type region, ensuring that the sidewalls of the first type region are vertical and flush.
It effectively avoids lateral etching of the sidewalls of the first type region, improves the performance and yield of semiconductor devices, and enhances the bonding between the mask layer and the stacked layer through the anti-reflective layer, preventing etching gas corrosion and protecting the first type region.
Smart Images
Figure CN115410907B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for fabricating a semiconductor device. Background Technology
[0002] Existing semiconductor device fabrication processes, such as high-k metal gate (HKMG) technology, are important technologies in the semiconductor field. In the HKMG fabrication process, different types of regions are formed on the substrate and the stacked structure on it, such as for fabricating PMOS and NMOS. However, when different types of regions are etched, the sidewalls of adjacent types of regions are over-etched, which affects the yield of the semiconductor. Summary of the Invention
[0003] The purpose of this invention is to provide a method for fabricating semiconductor devices that can reduce the over-etching effect on adjacent sidewalls during the etching process, thereby improving product performance and yield.
[0004] A method for fabricating a semiconductor device according to an embodiment of the present invention includes: providing a substrate; forming a stacked layer on the surface of the substrate, the stacked layer including a first type region and a second type region, the first type region and the second type region being disposed adjacent to each other; forming a mask layer on the surface of the first type region; forming a shielding layer on the sidewall of the mask layer, the shielding layer shielding a portion of the surface of the second type region; etching the second type region using the mask layer and the shielding layer as masks, the second type region shielded by the shielding layer being laterally etched, the width of the shielding layer being greater than the maximum width of the lateral etch of the second type region; removing the shielding layer to expose the portion of the second type region it shields; removing the exposed portion of the second type region so that the sidewall of the first type region is vertically flush.
[0005] According to some embodiments of the present invention, the width of the shielding layer is 0.1 nm-20 nm.
[0006] According to some embodiments of the present invention, in the step of forming a mask layer on the surface of the first type region, the mask layer includes a photoresist layer.
[0007] According to some embodiments of the present invention, the mask layer includes a photoresist layer and an anti-reflection layer, and the step of forming the mask layer on the surface of the first type region includes: forming an anti-reflection layer on the surface of the first type region; forming a photoresist layer on the surface of the anti-reflection layer, and the shielding layer is formed on the sidewalls of the anti-reflection layer and the photoresist layer.
[0008] According to some embodiments of the present invention, the step of forming a shielding layer on the sidewall of the mask layer includes: forming an initial shielding layer on the surface and sidewall of the mask layer and the surface of the second type region; removing a portion of the initial shielding layer located on the surface of the mask layer and the surface of the second type region, and retaining the initial shielding layer located on the sidewall of the mask layer to form the shielding layer.
[0009] Optionally, in the step of forming an initial shielding layer on the surface and sidewalls of the mask layer and on the surface of the second type region, the initial shielding layer is formed by atomic layer deposition.
[0010] According to some embodiments of the present invention, the shielding layer comprises a silicon dioxide layer.
[0011] According to some embodiments of the present invention, dry etching is used to remove the exposed portion of the second type region in the step of removing the exposed portion of the second type region so that the sidewalls of the first type region are vertically flush.
[0012] Optionally, in the dry etching process, a combination gas formed by one or more gases such as hydrogen fluoride, nitrogen, chlorine, and argon is used to etch the exposed portion of the second type region, and the etching time is 10s-60s.
[0013] According to some embodiments of the present invention, the stacked layer includes an insulating layer and a gate layer stacked thereon; the step of forming the stacked layer includes: forming the insulating layer on the surface of the substrate; and forming the gate layer on the surface of the insulating layer.
[0014] Optionally, the insulating layer includes a first insulating layer and a second insulating layer stacked together, the first insulating layer being formed on the surface of the substrate, the second insulating layer being formed on the surface of the first insulating layer, the first insulating layer being a silicon-containing oxide nitride layer or oxide layer, and the second insulating layer being a high-k material layer.
[0015] Optionally, the first insulating layer is a silicon oxide layer, and the second insulating layer is a hafnium silicate layer.
[0016] According to some embodiments of the present invention, the gate layer includes a plurality of stacked metal sub-gate layers and a dielectric layer disposed between the plurality of metal sub-gate layers.
[0017] According to some embodiments of the present invention, the gate layer includes a first metal sub-gate layer, a second metal sub-gate layer and an intermediate dielectric layer stacked together, wherein the first metal sub-gate layer and the second metal sub-gate layer are titanium nitride layers and the intermediate dielectric layer is an aluminum oxide layer.
[0018] According to some embodiments of the present invention, in the step of etching the second type region using the mask layer and the shielding layer as a mask, one or more of the following gases, such as boron trichloride, chlorine, and argon, are used to etch the second type region, and the etching time is 2s to 120s.
[0019] Therefore, in the semiconductor device fabrication method according to embodiments of the present invention, a shielding layer is formed to shield a portion of the second type region located on the sidewall of the first type region. Thus, during etching of the second type region, lateral etching is performed on the shielded second type region, rather than on the sidewall of the first type region. Subsequent removal of the shielding layer and the second type region below it ensures that the sidewall of the first type region is relatively vertical and flush, thereby avoiding interference with subsequent processes in the first type region and guaranteeing the performance and yield of the final semiconductor device. Simultaneously, the present invention employs an anti-reflective layer formed between the photoresist layer and the stacked layers. This anti-reflective layer enhances the bonding with the stacked layers, resulting in a tighter bond between the mask layer and the stacked layers. This prevents etching gases from causing additional corrosion to the film layer through gaps in the bonding surface, further protecting the first type region. Attached Figure Description
[0020] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;
[0021] Figures 2-10 A cross-sectional view of a semiconductor device in each step of a method for fabricating a semiconductor device according to an embodiment of the present invention;
[0022] Figures 11-13 This is a schematic diagram of the structure of a semiconductor device, showing some steps of the fabrication method of the semiconductor device in the related technology.
[0023] Figure label:
[0024] 1: Substrate;
[0025] 2: Stacked layer, 21: Insulating layer, 22: First insulating layer, 23: Second insulating layer, 24: Metal gate layer, 25: First metal sub-gate layer, 26: Intermediate dielectric layer, 27: Second metal sub-gate layer, 28: First type region, 29: Second type region;
[0026] 3: Mask layer; 31: Photoresist layer; 32: Anti-reflection layer;
[0027] 4: Occlusion layer, 41: Initial occlusion layer. Detailed Implementation
[0028] The following describes in further detail a method for fabricating a semiconductor device according to the present invention, with reference to the accompanying drawings and specific embodiments.
[0029] As described in the background art, when etching different types of regions, over-etching occurs on the sidewalls of adjacent regions, affecting the semiconductor yield. The inventors discovered that, specifically... Figures 11-13 As shown, in the process of processing semiconductor devices, such as Figure 11 As shown, photoresist is typically applied directly to the surface of semiconductor devices. However, this method, relying solely on the photoresist layer (32'), can easily lead to over-etching during the etching process. Figure 12 As shown, when etching the topmost material layer 27' of the semiconductor device, an uneven structure is formed on the sidewalls of the topmost material layer 27'. When other stacked material layers, such as the intermediate material layer 26' and the lower material layer 25', are gradually etched, obvious unevenness is formed on the sidewalls of the stacked structure, such as... Figure 13 As shown, a noticeable uneven lateral erosion phenomenon will form on the sidewalls of the uppermost material layer 27' and the middle material layer 26'.
[0030] The following describes a method for fabricating a semiconductor device according to an embodiment of the present invention with reference to the accompanying drawings. This method can be used to fabricate a high-k metal gate (HKMG).
[0031] like Figure 1 As shown, a method for fabricating a semiconductor device according to an embodiment of the present invention may include providing a substrate 1; forming a stacked layer 2 on the surface of the substrate 1, the stacked layer 2 including a first type region 28 and a second type region 29, the first type region 28 and the second type region 29 being disposed adjacent to each other; forming a mask layer 3 on the surface of the first type region 28; forming a shielding layer 4 on the sidewall of the mask layer 3, the shielding layer 4 shielding a portion of the surface of the second type region 29; etching the second type region 29 using the mask layer 3 and the shielding layer 4 as masks, the second type region 29 shielded by the shielding layer 4 having lateral etch, the width of the shielding layer 4 being greater than the maximum width of the lateral etch of the second type region 29; removing the shielding layer 4 to expose the portion of the second type region 29 it shields; removing the exposed portion of the second type region 29 so that the sidewall of the first type region 28 is vertically flush.
[0032] Figures 2-10 The following is a schematic cross-sectional view of the pattern formed by each step of the method for fabricating a semiconductor device according to an embodiment of the present invention, with reference to the accompanying drawings. Figures 2-10 The method for fabricating the semiconductor device according to embodiments of the present invention will be described in detail.
[0033] like Figure 2As shown, a substrate 1 is provided, and the material of the substrate 1 can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other group III-V compounds.
[0034] like Figure 2 As shown, a stacked layer 2 is formed on the surface of substrate 1. The stacked layer 2 includes a first type region 28 and a second type region 29, which are arranged adjacent to each other. The stacked layer 2 may include multiple material layers for forming devices, such as insulating layers, gate layers, and dielectric layers. Functional devices are formed by etching the stacked layer 2. In the stacking direction perpendicular to the stacking direction, the stacked layer 2 may also include the first type region 28 and the second type region 29, which are arranged adjacent to each other and can be used to form devices of the same or different types. For example, the semiconductor device fabrication method can be used in the HKMG process, where the stacked layer 2 is used to form PMOS transistors and NMOS transistors. Specifically, the first type region 28 can be used to form PMOS transistors, and the second type region 29 can be used to form NMOS transistors.
[0035] In some embodiments of the present invention, combined with Figures 2-4 As shown, the stacked layer 2 includes an insulating layer 21 and a gate layer 24 stacked together. The gate layer 24 is formed above the insulating layer 21, wherein the gate layer 24 and the insulating layer 21 can together form the metal gate of a semiconductor device. The steps of forming the stacked layer 2 include: forming the insulating layer 21 on the surface of the substrate 1; forming the gate layer 24 on the surface of the insulating layer 21, wherein the insulating layer 21 may include multiple layers of insulating material, and the gate layer 24 may include multiple layers of gate material and an intermediate dielectric layer 26 formed between the multiple layers of gate material, wherein the intermediate dielectric layer 26 is used to adjust the Vt voltage of the metal gate.
[0036] Optionally, such as Figures 2-4 As shown, the insulating layer 21 may include a first insulating layer 22 and a second insulating layer 23 stacked together. The first insulating layer 22 is formed on the surface of the substrate 1, and the second insulating layer 23 is formed on the surface of the first insulating layer 22. The first insulating layer 22 may be a silicon-containing oxide nitride layer or oxide layer, for example, the first insulating layer 22 may be a silicon oxide layer. The second insulating layer 23 may be a high-k material layer, for example, the second insulating layer 23 may be a hafnium silicate layer.
[0037] The gate layer 24 may include multiple stacked metal sub-gate layers and a dielectric layer disposed between the multiple metal sub-gate layers 24. For example, the gate layer 24 may include a first metal sub-gate layer 25, a second metal sub-gate layer 27, and an intermediate dielectric layer 26 stacked together. The first metal sub-gate layer 25 is formed on the surface of the insulating layer 21, and the intermediate dielectric layer 26 is formed between the first metal sub-gate layer 25 and the second metal sub-gate layer 27. The first metal sub-gate layer 25 and the second metal sub-gate layer 27 can both be titanium nitride layers, and the intermediate dielectric layer 26 can be an aluminum oxide layer. Figures 2-4 In the example shown, the step of forming the stacked layer 2 may specifically include: forming a first insulating layer 22, a second insulating layer 23, a first metal sub-gate layer 25, an intermediate dielectric layer 26, and a second metal sub-gate layer 27 sequentially on the surface of the substrate 1.
[0038] like Figure 3 As shown, a mask layer 3 is formed on the surface of the first type region 28, that is, the mask layer 3 covers the stacked layer 2 formed on the surface of the first type region 28 and exposes the surface of the second type region 29. In this way, the second type region 29 can be etched with the mask layer 3 as a mask, while the first type region 28 is preserved.
[0039] In some examples of the present invention, the mask layer 3 may include a photoresist layer 31, wherein photoresist is coated on the surface of the first type region 28 to form the photoresist layer 31, and then photolithography of the second type region 29 is achieved through exposure, development and other steps.
[0040] In other examples of the invention, such as Figure 3 As shown, the mask layer 3 may further include a photoresist layer 31 and an anti-reflection layer 32. Specifically, an anti-reflection layer 32 is formed on the surface of the first type region 28, and a photoresist layer 31 is formed on the surface of the anti-reflection layer 32. The anti-reflection layer 32 enhances the bonding with the stacked layer 2, making the mask layer 3 and the stacked layer 2 tightly bonded. This prevents etching gas from causing additional corrosion to the film layer through the gaps at the bonding surface, thereby protecting the first type region 28 and reducing lateral etching when etching the second type region 29. Figure 3 In the example shown, the step of forming mask layer 3 may include: forming an anti-reflection layer 32 on the surface of the second metal sub-gate layer 27 located in the first type region 28, and coating the surface of the anti-reflection layer 32 with photoresist to form a photoresist layer 31.
[0041] like Figures 4-5As shown, a shielding layer 4 is formed on the sidewall of the mask layer 3, which shields part of the surface of the second type region 29. The second type region 29 is etched using the mask layer 3 and the shielding layer 4 as masks. In this way, during the etching process, the second type region 29 not covered by the shielding layer 4 can be etched, while the part of the second type region 29 located below the shielding layer 4 is retained. Specifically, during the etching process of the second type region 29, if only the mask layer 3 is used as a mask for etching, the sidewall of the mask layer 3 corresponds to the adjacent positions of the first type region 28 and the second type region 29. Due to the etching characteristics, lateral etching will inevitably occur on the sidewall of the first type region 28, causing the first type region 29 to be partially etched. The sidewalls of the first type region 28 have an uneven structure, which affects the subsequent processing and product performance of the first type region 28. In this invention, by forming a shielding layer 4 and using the shielding layer 4 and the masking layer 3 as a mask for etching, when etching the second type region 29, the lateral etching formed during the etching process will be formed on the sidewalls of the second type region 29 located below the shielding layer 4, thereby avoiding lateral etching of the sidewalls of the first type region 28. Then, by removing the remaining second type region 29 shielded by the shielding layer 4, the sidewalls of the first type region 28 can be kept vertical, flat and intact, thereby avoiding any impact on the first type region 28 and improving the product yield and performance.
[0042] The thickness of the shielding layer 4 is greater than the maximum width of the lateral erosion of the second type region 29. That is, the shielding layer 4 can completely block the lateral erosion of the second type region 29, so that the lateral erosion is only formed in the second type region 29 located below the shielding layer 4 during etching. This avoids the lateral erosion from extending to the first type region 28 and causing over-etching of the sidewalls of the first type region 28 during the etching process. For example, the thickness of the shielding layer 4 can be greater than or equal to the width of the lateral erosion of the second metal sub-gate layer 27. Since the second metal sub-gate layer 27 needs to be etched from both sides, its lateral erosion width is larger. Therefore, the thickness of the shielding layer 4 can block the largest part of the lateral erosion of the second metal sub-gate layer 27 in the second type region 29 during the etching process, thus avoiding lateral erosion of the sidewalls of the first type region 28.
[0043] Optionally, the width of the shielding layer 4 is 0.1nm-20nm. For example, the thickness of the shielding layer 4 can be 1nm, 5nm or 10nm, etc., which can be set according to actual needs. For example, it can be set according to the etching parameters and the width of the lateral erosion caused by the etching thickness of the second type region 29. In this way, the width of the second type region 29 covered by the shielding layer 4 is 0.1nm-20nm. This can prevent the sidewall of the first type region 28 from being over-etched due to the thinness of the shielding layer 4 being too small, and can also prevent the shielding layer 4 from being too thick and affecting the subsequent etching.
[0044] In such Figure 4 In the example shown, the step of forming the shielding layer 4 on the sidewall of the mask layer 3 may include: forming an initial shielding layer 41 on the surface and sidewall of the mask layer 3 and on the surface of the second type region 29. Optionally, in this step, the initial shielding layer 41 may be deposited using an atomic layer deposition process. Then, a portion of the initial shielding layer 41 located on the surface of the mask layer 3 and the surface of the second type region 29 is removed, leaving the initial shielding layer 41 on the sidewall of the mask layer 3 to form the shielding layer 4. Thus, the shielding layer 4 is formed above the portion of the second type region 29 adjacent to the first type region 28 to shield the portion of the second type region 29 adjacent to the first type region 28 and protect the sidewalls adjacent to the first type region 28 and the second type region 29.
[0045] Optionally, the material of the shielding layer 4 can be a silicon dioxide layer. Of course, it is understood that the shielding layer 4 can also be other materials, such as a silicon oxynitride layer.
[0046] like Figure 6 and Figure 7 As shown, the second type region 29 is etched using mask layer 3 and masking layer 4 as masks to remove the exposed portion of the second type region 29. Specifically, when using mask layer 3 and masking layer 4 as masks to etch the second type region 29, the second type region 29 can be etched layer by layer, such as... Figure 6 As shown, the second metal sub-gate layer 27 is etched using the mask layer 3 and the shielding layer 4 as masks, retaining the portion of the second metal sub-gate layer 27 covered by the mask layer 3 and the shielding layer 4, and the sidewalls of the portion of the second metal sub-gate layer 27 are flush.
[0047] like Figure 7 As shown, the intermediate dielectric layer 26 and the first metal sub-gate layer 25 are etched sequentially using the mask layer 3 and the shielding layer 4 as a mask pair, retaining the portion of the first metal sub-gate layer 25 and the portion of the intermediate dielectric layer 26 covered by the mask layer 3 and the shielding layer 4. The sidewalls of the portion of the first metal sub-gate layer 25 and the portion of the intermediate dielectric layer 26 are both vertically flush, thereby ensuring that the sidewalls of the retained first metal sub-gate layer 25, intermediate dielectric layer 26, and second metal sub-gate layer 27 are all flush with the sidewalls of the shielding layer 4, and no uneven structure is formed.
[0048] Optionally, in this step, one or more of the following gases, such as boron trichloride, chlorine, and argon, can be used to etch the second type region 29. The etching time is 2s to 120s. Specifically, the gate layer 24 can be a titanium nitride layer. For example, the first metal sub-gate layer 25 and the second metal sub-gate layer 27 can both be titanium nitride layers. Taking chlorine as an example, when etching the gate layer 24, the etching time can be 2s to 120s, and the flow rate of the etching gas can be 50 to 100 torr.
[0049] like Figure 8 and Figure 9 As shown, the shielding layer 4 is removed to expose the portion of the second type region 29 that it shields, thereby removing the exposed portion of the second type region 29 and making the sidewalls of the remaining first type region 28 vertically flush.
[0050] Specifically, such as Figure 8 As shown, the shielding layer 4 is removed to expose the portion of the second type region 29 that it shields. Due to etching characteristics, after the shielding layer 4 is removed by etching, an uneven structure is formed on the sidewalls of the remaining second type region 29, especially on the sidewalls of the second metal sub-gate layer 27. That is, lateral erosion occurs on the sidewalls of the second type region 29. The reason for the formation of lateral erosion is that during the etching process of the second type region 29, a small lateral erosion occurs on the sidewalls of the shielded portion of the second type region 29. As the second type region 29 is etched layer by layer and the shielding layer 4 is etched, the lateral erosion of the second type region 29 gradually increases, forming a significant uneven structure. Moreover, since the material of the shielding layer 4 is different from that of the gate layer 24, the etching parameters such as the etching gas are different, which also increases the degree of lateral erosion of the second type region 29. The second metal sub-gate layer 27 is located on the upper layer, and after multiple etchings, the lateral erosion of its sidewalls is more obvious.
[0051] like Figure 9 As shown, the second type region 29 with laterally eroded sidewalls is removed using the anti-reflective layer 32 as a mask, while the first type region 28 is retained. Thus, by removing the second type region 29 with its uneven structure, the sidewalls of the first type region 28 are flush with the sidewalls of the mask layer 3 without forming an uneven structure. Figure 9 In the example shown, the sidewall of the first type region 28 is flush with the sidewall of the anti-reflective layer 32.
[0052] Optionally, in this step, a dry etching process can be used to etch the exposed portion of the second-type region 29 after removing the shielding layer 4. Specifically, in the dry etching process, a combination gas formed by one or more gases such as hydrogen fluoride, nitrogen, chlorine, and argon can be used to etch the exposed portion of the second-type region 29 for 10-60 seconds. Further, chlorine can be used to etch the exposed portion of the second-type region 29 so that the sidewalls of the first-type region 28 are vertically flush, and the flow rate of the chlorine can be 10-100 torr.
[0053] like Figure 10 As shown, remove mask layer 3, and then... Figure 10 In the example shown, the anti-reflective layer 32 is removed to expose the first type region 28, thereby facilitating subsequent processing of the first type region 28.
[0054] Therefore, in the semiconductor device fabrication method according to embodiments of the present invention, when the second type region 29 is directly etched using only the mask layer 3 as a mask, the sidewall of the mask layer 3 adjacent to the second type region 29 is flush with the sidewall of the first type region 28 adjacent to the second type region 29. This makes it easy for over-etching to occur on the sidewall of the first type region 28 during etching of the second type region 29, resulting in unevenness on the sidewall of the first type region 28 and affecting subsequent etching processes such as etching of the first type region 28. However, in the present invention, a shielding layer 4 is formed to shield a portion of the second type region 29 located on the sidewall of the first type region 28. Thus, during etching of the second type region 29, lateral etching is formed in the shielded second type region 29. Instead of the sidewalls of the first type region 28, the subsequent removal of the shielding layer 4 and the second type region 29 located below the shielding layer 4 allows the sidewalls of the first type region 28 to be relatively vertical and flush, thereby avoiding affecting the subsequent process of the first type region 28 and ensuring the performance and yield of the final semiconductor device. At the same time, in this invention, an anti-reflection layer 32 is formed between the photoresist layer 31 and the stacked layer 2. The anti-reflection layer 32 can be formed as a barrier layer. The anti-reflection layer 32 can enhance the bonding with the stacked layer 2, making the mask layer 3 and the stacked layer 2 tightly bonded. This can prevent etching gas from causing additional corrosion to the film layer through the gaps in the bonding surface, further protecting the first type region 28 and improving the lateral erosion phenomenon of the first type region 28.
[0055] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A stacked layer is formed on the surface of the substrate, the stacked layer including a first type region and a second type region, the first type region and the second type region being disposed adjacent to each other; A mask layer is formed on the surface of the first type of region; A shielding layer is formed on the sidewall of the mask layer, and the shielding layer shields a portion of the surface of the second type region; The second type region is etched using the mask layer and the shielding layer as masks. Lateral erosion is formed in the second type region shielded by the shielding layer. The width of the shielding layer is greater than the maximum width of the lateral erosion of the second type region. Remove the masking layer to expose the portion of the second type of region that it was covering; Remove the exposed portion of the second type region to make the sidewalls of the first type region vertically flush; The mask layer includes a photoresist layer and an anti-reflection layer, and the step of forming the mask layer on the surface of the first type region includes: An anti-reflective layer is formed on the surface of the first type of region; A photoresist layer is formed on the surface of the anti-reflective layer, and a shielding layer is formed on the sidewalls of the anti-reflective layer and the photoresist layer; The anti-reflective layer is formed between the photoresist layer and the stacked layer. The anti-reflective layer enhances the bonding with the stacked layer, making the mask layer and the stacked layer tightly bonded, and preventing etching gas from causing additional corrosion to the film layer through the gaps in the bonding surface.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The width of the shielding layer is 0.1nm-20nm.
3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming a shielding layer on the sidewall of the mask layer includes: An initial shielding layer is formed on the surface and sidewalls of the mask layer and on the surface of the second type region; Remove a portion of the initial masking layer located on the surface of the mask layer and the surface of the second type region, and retain the initial masking layer located on the sidewall of the mask layer to form the masking layer.
4. The method for fabricating a semiconductor device according to claim 3, characterized in that, In the step of forming an initial shielding layer on the surface and sidewalls of the mask layer and on the surface of the second type region, the initial shielding layer is formed by atomic layer deposition.
5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The shielding layer includes a silicon dioxide layer.
6. The method for fabricating a semiconductor device according to claim 1, characterized in that, In the step of removing the exposed portion of the second type region to make the sidewalls of the first type region vertically flush, the exposed portion of the second type region is removed by dry etching.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, In the dry etching process, a combination gas formed by one or more of hydrogen fluoride, nitrogen, chlorine, and argon is used to etch the exposed portion of the second type region for a time of 10s-60s.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The stacked layer includes an insulating layer and a gate layer stacked together; the step of forming the stacked layer includes: The insulating layer is formed on the surface of the substrate; The gate layer is formed on the surface of the insulating layer.
9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The insulating layer includes a first insulating layer and a second insulating layer stacked together. The first insulating layer is formed on the surface of the substrate, and the second insulating layer is formed on the surface of the first insulating layer. The first insulating layer is a silicon-containing oxide nitride layer or oxide layer, and the second insulating layer is a high-k material layer.
10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The first insulating layer is a silicon oxide layer, and the second insulating layer is a hafnium silicate layer.
11. The method for fabricating a semiconductor device according to claim 8, characterized in that, The gate layer includes a plurality of stacked metal sub-gate layers and a dielectric layer disposed between the plurality of metal sub-gate layers.
12. The method for fabricating a semiconductor device according to claim 11, characterized in that, The gate layer includes a first metal sub-gate layer, a second metal sub-gate layer and an intermediate dielectric layer stacked together, wherein the first metal sub-gate layer and the second metal sub-gate layer are titanium nitride layers and the intermediate dielectric layer is an aluminum oxide layer.
13. The method for fabricating a semiconductor device according to claim 12, characterized in that, In the step of etching the second type of region using the mask layer and the shielding layer as a mask, one or more of boron trichloride, chlorine, and argon are used to etch the second type of region for a time of 2s to 120s.