Electronic device and method of operating the same

Abstract

The present invention relates to an electronic device comprising: a plurality of analog-to-digital converters each configured to receive an analog input signal and output a digital output signal corresponding to the analog input signal; an analog input signal generator configured to generate the analog input signal provided to each of the analog-to-digital converters based on an input voltage and weight data; an input signal distribution information generator configured to generate input signal distribution information for each of the analog-to-digital converters, the input signal distribution information being indicative of a distribution of the analog input signal; an analog-to-digital converter group classifier configured to classify the analog-to-digital converters into a plurality of first analog-to-digital converter groups based on the input signal distribution information; and an analog-to-digital converter input range optimizer configured to determine an input range for each of the first analog-to-digital converter groups based on the input signal distribution information, and each of the analog-to-digital converters is configured to operate in accordance with the input range of the respective first analog-to-digital converter group.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority and benefit to Korean Patent Application No. 10-2021-0067928, filed on May 26, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] The technology disclosed in this patent application relates to an electronic device and its operating method. Background Technology

[0004] A neural network is a computational architecture obtained by modeling the biological brain. With the recent development of neural network technology, research is actively underway on extracting useful information from input data using one or more neural network models in various types of electronic systems. Convolution operations account for a large portion of the computation required by neural network models. Summary of the Invention

[0005] The disclosed embodiments provide an electronic device and a method of operating the same, which can improve the accuracy of a neural network model including an analog-to-digital converter while reducing the area and power consumption of the analog-to-digital converter.

[0006] According to an embodiment of the disclosed technology, an electronic device includes: a plurality of analog-to-digital converters (ADCs), each ADC configured to receive an analog input signal and output a digital output signal corresponding to the analog input signal; an analog input signal generator configured to generate an analog input signal provided to each of the plurality of ADCs based on calculations performed on a plurality of input voltages and a plurality of weighted data; an input signal distribution information generator configured to generate input signal distribution information for each of the plurality of ADCs, the input signal distribution information indicating the distribution of the analog input signal; an ADC group classifier configured to classify the plurality of ADCs into a plurality of first ADC groups based on the input signal distribution information of the plurality of ADCs; and an ADC input range optimizer configured to determine the input range of each of the plurality of first ADC groups based on the input signal distribution information of the plurality of ADCs, and each of the plurality of ADCs is configured to operate according to the input range of the corresponding first ADC group among the plurality of first ADC groups.

[0007] According to an embodiment of the disclosed technology, a method of operating an electronic device includes classifying a plurality of analog-to-digital converters into a plurality of default analog-to-digital converter groups, generating analog input signals for the plurality of analog-to-digital converters using operations based on a plurality of input voltages and a plurality of weight data, generating input signal distribution information of the plurality of default analog-to-digital converter groups based on the analog input signals, classifying the plurality of default analog-to-digital converter groups into a plurality of first analog-to-digital converter groups based on the input signal distribution information of the plurality of default analog-to-digital converter groups, determining an input range of each of the plurality of first analog-to-digital converter groups based on the input signal distribution information of the plurality of default analog-to-digital converter groups, and controlling the plurality of analog-to-digital converters to operate according to the input range of a corresponding first analog-to-digital converter group among the plurality of first analog-to-digital converter groups.

[0008] According to the present technology, there is provided an electronic device and an operating method thereof, which can reduce the area and power consumption of an analog-to-digital converter while improving the accuracy of a neural network model including the analog-to-digital converter. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 FIG. 1 is a diagram illustrating an example of a computing system according to an embodiment of the disclosed technology.

[0010] Figure 2A FIG. 2 is a diagram illustrating a configuration of a neural network according to an embodiment of the disclosed technology. Figure 2B

[0011] Figure 3 FIG. 3 is a diagram illustrating an electronic device for optimizing an input range of an analog-to-digital converter according to an embodiment of the disclosed technology.

[0012] Figure 4 FIG. 4 is a diagram illustrating a computing circuit according to an embodiment of the disclosed technology.

[0013] Figure 5A FIG. 5 is a diagram illustrating an example of a sub-array according to an embodiment of the disclosed technology.

[0014] Figure 5B FIG. 6 is a diagram illustrating another example of a sub-array according to an embodiment of the disclosed technology.

[0015] Figure 6 FIG. 7 is a diagram illustrating input signal distribution information according to an embodiment of the disclosed technology.

[0016] Figure 7A FIG. 8 is a diagram illustrating an operation of classifying a plurality of analog-to-digital converters into a plurality of first analog-to-digital converter groups according to an embodiment of the disclosed technology.

[0017] Figure 7B ​is a diagram illustrating an operation of classifying a plurality of default analog-to-digital converter groups into a plurality of first analog-to-digital converter groups according to an embodiment of the disclosed technology.

[0018] Figure 8A is a diagram illustrating an example of an operation of determining an input range of each of a plurality of first analog-to-digital converter groups according to an embodiment of the disclosed technology.

[0019] Figure 8B is a diagram illustrating another example of an operation of determining an input range of each of a plurality of first analog-to-digital converter groups according to an embodiment of the disclosed technology.

[0020] Figure 9 is a diagram illustrating an operation of optimizing an input range of an analog-to-digital converter according to an embodiment of the disclosed technology.

[0021] Figure 10 is a flowchart illustrating a method of operating an electronic device for optimizing an input range of an analog-to-digital converter according to an embodiment of the disclosed technology.

[0022] Figure 11 is a flowchart illustrating a method of operating an electronic device for optimizing an input range of an analog-to-digital converter according to an additional embodiment of the disclosed technology. DETAILED DESCRIPTION

[0023] Figure 1 is a diagram illustrating an example of a computing system according to an embodiment of the disclosed technology.

[0024] REFERENCE Figure 1 The computing system 10 can extract effective information by analyzing input data in real time based on a neural network, and determine a situation based on the extracted information or a control configuration of an electronic device in which the computing system 10 is installed. For example, the computing system 10 can be applied to a drone, an advanced driver assistance system (ADAS), a smart television, a smart phone, a medical device, a mobile device, an image display device, a measuring device, an Internet of Things (IoT) device, etc., and can be installed on one of various types of electronic devices.

[0025] The computing system 10 can include a central processing unit (CPU) 110, a random access memory (RAM) 120, a neural network processor 130, an input / output device 140, and a memory 150. In addition, the computing system 10 can further include other general-purpose components such as a multi-format codec (MFC), a video module (e.g., a camera interface, a joint photographic experts group (JPEG) processor, a video processor, a mixer, etc.), a 3D graphics kernel, an audio system, a display driver, a graphics processing unit (GPU), and a digital signal processor (DSP). The CPU 110, the RAM 120, the neural network processor 130, the input / output device 140, and the memory 150 can transmit / receive data through a communication bus 160.

[0026] In an embodiment, the components of the computing system 10 (e.g., the CPU 110, the RAM 120, the neural network processor 130, the input / output device 140, and the memory 150) can be implemented as one semiconductor chip, and for example, the computing system 10 can be implemented as a system on chip (SoC). However, the disclosed technology is not limited thereto, and the computing system 10 can be implemented as a plurality of semiconductor chips. In an embodiment, the computing system 10 can be an application processor mounted on a mobile device.

[0027] The CPU 110 can control overall operations of the computing system 10. The CPU 110 can include one core (single core) or a plurality of cores (multi-core). The CPU 110 can process or execute programs and / or data stored in the RAM 120 and the memory 150. For example, the CPU 110 can control functions of the computing system 10 by executing programs stored in the memory 150.

[0028] The RAM 120 can temporarily store programs, data, or instructions. For example, programs and / or data stored in the memory 150 can be temporarily loaded into the RAM 120 according to control or booting codes of the CPU 110. The RAM 120 can be implemented using a memory such as dynamic RAM (DRAM) or static RAM (SRAM).

[0029] The input / output device 140 can receive a user input or input data from the outside, and can output a data processing result of the computing system 10. The input / output device 140 can be implemented as a touch screen panel, a keyboard, various types of sensors, etc. In an embodiment, the input / output device 140 can collect information around the computing system 10. For example, the input / output device 140 can include at least one of various types of sensing devices such as an imaging device, an image sensor, a light detection and ranging (LIDAR) sensor, an ultrasonic sensor, or an infrared sensor, or can receive a sensing signal from a device.

[0030] The memory 150 can be a storage place for storing data, and can store, for example, an operating system (OS), various programs, and various data. The memory 150 can be a DRAM, but is not limited thereto. The memory 150 can include at least one of a volatile memory and a non-volatile memory. The non-volatile memory can include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. The volatile memory can include a dynamic RAM (DRAM), a static RAM (SRAM), a synchronous DRAM (SDRAM), etc. In addition, in an embodiment, the memory 150 can be implemented as a storage device such as a hard disk drive (HDD), a solid state drive (SSD), a compact flash (CF), a secure digital (SD), a micro-SD, a mini-SD, an extreme digital (xD), or a memory stick.

[0031] The neural network processor 130 can generate a neural network, train (or learn) the neural network, or perform an operation based on received input data, and can generate an information signal based on an operation result or retrain the neural network. The neural network can include various types of neural network models such as a convolutional neural network (CNN), a region convolutional neural network (R-CNN), a region proposal network (RPN), a recurrent neural network (RNN), a deep neural network (DNN), a stacked-based deep neural network (S-DNN), a state-space dynamic neural network (S-SDNN), a de-convolutional network, a deep belief network (DBN), a restricted Boltzmann machine (RBM), a fully convolutional network, a long short-term memory (LSTM) network, or a classification network. The above-described neural network is merely an example, and is not limited thereto. Referring to Figure 2A and Figure 2B A configuration of a neural network is exemplarily described.

[0032] Figure 2A and Figure 2B is a diagram illustrating a configuration of a neural network according to an embodiment of the disclosed technology.

[0033] Referring to Figure 2A , the neural network can include an input layer IL, a plurality of hidden layers HL1 and HL2, and an output layer OL. In Figure 2A , the number of hidden layers is two, and the number of hidden layers can be different according to an embodiment.

[0034] The input layer IL can include input nodes x1 and x2, and input data IDAT can be input to each input node. On the other hand, the number of input nodes included in the input layer can vary according to embodiments.

[0035] The plurality of hidden layers HL1 and HL2 can include hidden nodes h11, h12, h13, h21, h22, and h23. For example, the hidden layer HL1 can include a plurality of hidden nodes h11, h12, and h13, and the hidden layer HL2 can include a plurality of hidden nodes h21, h22, and h23. On the other hand, the number of hidden nodes included in each hidden layer is not limited to three, and can vary according to embodiments.

[0036] The output layer OL can include output nodes y1 and y2, and can output a result of the input data IDAT as output data ODAT. On the other hand, the number of output nodes included in the output layer can vary according to embodiments.

[0037] Figure 2A The illustrated network structure can include branches between nodes, shown as straight lines between two nodes, and weights used in each connection, although not shown. At this time, nodes in one layer can not be connected, and nodes included in different layers can be connected completely or partially.

[0038] Figure 2A Each node (e.g., h11) of the neural network can receive an output of a previous node (e.g., x1) and perform an operation, and can output an operation result to a subsequent node (e.g., h21). At this time, each node can operate a value to be output by applying an input value to a specific function, for example, a nonlinear function.

[0039] In general, the structure of a neural network can be determined in advance, and an appropriate value can be calculated using data with known correct answers according to the weights of connections between nodes. As described above, data with known correct answers is referred to as "learning data", and the process of determining weights is referred to as "learning". In addition, assuming that a set of structures and weights that can be learned independently is a "model", the process in which a model in which weights are determined predicts to which class input data belongs and outputs a predicted value can be referred to as a "test process".

[0040] Referring to Figure 2B , an example of an operation performed in one node ND among the nodes shown in Figure 2A is specifically illustrated. It is assumed that n inputs a1, a2,..., and an are provided in one node ND.

[0041] In an embodiment, the node ND can multiply the n inputs a1, a2, a3,..., and an by the respective n weights w1, w2, w3,..., and wn, add the values obtained by the multiplication, add a bias (b) to the added input values, and apply the input values reflecting the bias to a specific function (σ) to generate one output value. At this time, the specific function (σ) can be an activation function.

[0042] When Figure 2A A layer included in the neural network illustrated in FIG. 1 can include M nodes ND, and the M nodes ND can be configured as illustrated in FIG. 2. Figure 2B When the M nodes ND illustrated in FIG. 2 are included in a layer, an output value of the layer can be obtained as in the following [Equation 1].

[0043] [Equation 1]

[0044] WA = Z

[0045] In [Equation 1], W denotes all the weights of the connections included in a layer, and can be implemented in the form of an M x N matrix. A denotes the n inputs a1, a2, a3,..., and an received in a layer, and can be implemented in the form of an n x 1 matrix. Z denotes the m outputs z1, z2, z3,..., and zm output from a layer, and can be implemented in the form of an m x 1 matrix.

[0046] Figure 3 is a diagram illustrating an electronic device for optimizing an input range of an analog-to-digital converter according to an embodiment of the disclosed technology. In the disclosed technology, a neural network model is implemented using an analog-to-digital converter (ADC). A conventional ADC occupies a large area and has a large power consumption, and some embodiments of the disclosed technology provide an electronic device capable of reducing the area and power consumption of the ADC while improving the accuracy of the neural network model.

[0047] In an embodiment, the electronic device 300 can be implemented as a neural network processor 130 including a plurality of analog-to-digital converters (ADCs) as illustrated in FIG. 3. Figure 3 The electronic device 300 illustrated in FIG. 3 can be implemented as one configuration of the neural network processor 130. For example, the electronic device 300 can optimize the input ranges of the plurality of analog-to-digital converters included in the computing circuit 330. At this time, the input range can denote a maximum dynamic range that prevents the analog-to-digital converters from being overloaded. The "input range" can also be referred to as a "quantization range." Figure 1 Referring to FIG. 3,

[0048] , the electronic device 300 can include a controller 310, a global buffer 320, and a computing circuit 330. In an embodiment, the controller 310, the global buffer 320, and the computing circuit 330 can communicate through a communication bus. Figure 3

[0049] ​In an embodiment, the electronic device 300 can be implemented as a single semiconductor chip. For example, the electronic device 300 can be implemented as a system on chip (SoC). However, the disclosed technology is not limited thereto, and the electronic device 300 can be implemented with a plurality of semiconductor chips.

[0050] The controller 310 can control overall operations of the electronic device 300. The controller 310 can control operations of the global buffer 320 and the computing circuit 330. For example, the controller 310 can set and manage parameters related to neural network operations, such as convolution operations, so that the computing circuit 330 can normally operate layers of a neural network.

[0051] The controller 310 can be implemented as hardware, software (or firmware), or a combination of hardware and software. In an embodiment, the controller 310 can be implemented with hardware logic designed to perform the above-described functions. In an embodiment, the controller 310 can be implemented with at least one processor, such as a CPU, a microprocessor, or the like, and can execute a program including instructions configuring the above-described functions.

[0052] In an embodiment, the controller 310 can include an input signal distribution information generator 311, an analog-to-digital converter group classifier 312, an analog-to-digital converter input range optimizer 313, a neural network model controller 314, and a neural network model accuracy measurer 315.

[0053] The input signal distribution information generator 311 can generate input signal distribution information for each of the plurality of analog-to-digital converters. At this time, the input signal distribution information can indicate a distribution of an analog input signal.

[0054] In an embodiment, the input signal distribution information generator 311 can generate input signal distribution information of the plurality of analog-to-digital converters based on an analog input signal input to each of the plurality of analog-to-digital converters. For example, the input signal distribution information generator 311 can receive an analog input signal input to each of the plurality of analog-to-digital converters from the computing circuit 330. The input signal distribution information generator 311 can calculate a mean value and a standard deviation of the analog input signal. In addition, the input signal distribution information generator 311 can generate input signal distribution information of the plurality of analog-to-digital converters using the mean value and the standard deviation.

[0055] In an embodiment, the input signal distribution information generator 311 can generate input signal distribution information of the plurality of analog-to-digital converters using a 3-sigma technique. Referring to FIG. 4, the input signal distribution information generator 311 can generate input signal distribution information of the plurality of analog-to-digital converters using the 3-sigma technique. Figure 6 The 3-sigma technique is described in detail.

[0056] The analog-to-digital converter group classifier 312 can classify the plurality of analog-to-digital converters into a plurality of first analog-to-digital converter groups based on the input signal distribution information of the plurality of analog-to-digital converters.

[0057] In an embodiment, the analog-to-digital converter group classifier 312 can determine an analog-to-digital converter having a similar size value corresponding to the input signal distribution information as any one of the plurality of first analog-to-digital converter groups. In an embodiment, the size value corresponding to the input signal distribution information can represent an addition of a mean value of the analog input signal and a multiple of a standard deviation.

[0058] For example, the analog-to-digital converter group classifier 312 can classify the plurality of analog-to-digital converters into the plurality of first analog-to-digital converter groups using a clustering technique. The analog-to-digital converter group classifier 312 can determine a size value corresponding to the input signal distribution information as a point of an analog-to-digital converter having the corresponding input signal distribution information. The analog-to-digital converter group classifier 312 can configure the plurality of first analog-to-digital converter groups by determining analog-to-digital converters having a close distance between points as one first analog-to-digital converter group. Accordingly, the analog-to-digital converter group classifier 312 can use the size value corresponding to the input signal distribution information as a variable and determine analog-to-digital converters having similar variables as a first analog-to-digital converter group.

[0059] In an embodiment, the clustering technique can be used to classify data into a plurality of groups based on similarity or other concepts. At this time, clustering can be referred to as grouping, and one group can be referred to as a cluster. The clustering technique can allow a group to be defined based on a certain feature or other features of data and classify data having similar features into the same group. Accordingly, data having similar features can belong to the same group, and data having different features can belong to different clusters.

[0060] For example, the analog-to-digital converter group classifier 312 can classify the plurality of analog-to-digital converters into the plurality of first analog-to-digital converter groups using a k-means clustering technique. The k-means clustering technique can be an algorithm for classifying classification objects into k clusters. Accordingly, the analog-to-digital converter group classifier 312 can classify the plurality of analog-to-digital converters into k first analog-to-digital converter groups using the k-means clustering technique. At this time, k can be set in various ways and can be increased by an operation of increasing the number of groups to be configured with the plurality of analog-to-digital converters, which will be described later. In the above example, the plurality of analog-to-digital converters are classified into the plurality of first analog-to-digital converter groups using the k-means clustering technique, but other embodiments can also exist. Accordingly, other clustering techniques other than the k-means clustering technique can be applied to classify the plurality of analog-to-digital converters into the plurality of first analog-to-digital converter groups.

[0061] The analog-to-digital converter input range optimizer 313 can optimize the input range of the plurality of analog-to-digital converters.

[0062] In an embodiment, the analog-to-digital converter input range optimizer 313 can determine an input range of each of the plurality of first analog-to-digital converter groups based on the input signal distribution information of the plurality of analog-to-digital converter groups. In this case, each of the plurality of analog-to-digital converters can operate according to the input range of the corresponding first analog-to-digital converter group among the plurality of first analog-to-digital converter groups. For example, the analog-to-digital converter input range optimizer 313 can determine any one of the analog-to-digital converters included in each of the plurality of first analog-to-digital converter groups as a reference analog-to-digital converter in each of the plurality of first analog-to-digital converter groups. At this time, the reference analog-to-digital converter can be an analog-to-digital converter among the analog-to-digital converters included in each of the plurality of first analog-to-digital converter groups, which has a maximum size value corresponding to the input signal distribution information. In addition, the analog-to-digital converter input range optimizer 313 can determine a distribution range corresponding to the input signal distribution information of the reference analog-to-digital converter determined in each of the plurality of first analog-to-digital converter groups as the input range of each of the plurality of first analog-to-digital converter groups. In an embodiment, the distribution range corresponding to the input signal distribution information can represent a range formed by the mean value of the analog input signal and the multiple of the standard deviation.

[0063] The neural network model controller 314 can control a result of the neural network model outputting input data. For example, the neural network model controller 314 can obtain an output value of the input data by using a neural network model including the plurality of analog-to-digital converters operating according to the input range optimized by the analog-to-digital converter input range optimizer 313. The output value can represent a result of the neural network model for the input data, and a form of the output value can differ according to a type of the neural network model.

[0064] In an embodiment, the neural network model can be implemented using the electronic device 300. For example, the plurality of layers included in the neural network model can be implemented using the plurality of processing elements PE or the plurality of sub-arrays included in the computing circuit 330. Accordingly, the operation of the neural network model can be performed by the computing circuit 330. In this case, the computing circuit 330 can include the plurality of analog-to-digital converters operating according to the optimized input range. Accordingly, the neural network model is applied to optimize the input range of each of the plurality of analog-to-digital converters. In some embodiments, the input range of each of the plurality of analog-to-digital converters can be optimized according to the input range of the corresponding first analog-to-digital converter group. The electronic device 300 implements the neural network model by including the plurality of analog-to-digital converters operating according to the optimized input range.

[0065] In an embodiment, the neural network model controller 314 can output a result of the input data using a neural network model including a plurality of analog-to-digital converters operating according to an optimized input range. For example, the neural network model controller 314 can provide the input data and the weight data to the global buffer 320 and the computing circuit 330, and control the global buffer 320 and the computing circuit 330 to output an output value of the input data. Thereafter, the neural network model controller 314 can obtain the output value from the global buffer 320 and the computing circuit 330.

[0066] The neural network model accuracy measurer 315 can measure the accuracy of the neural network model based on the output value of the neural network model. For example, the neural network model accuracy measurer 315 can measure the accuracy of the neural network model based on a result of comparing the output value with target data corresponding to the input data. At this time, the target data can be data indicating a correct answer to the input data. In some embodiments, the neural network model controller 314 can obtain a plurality of output values for a plurality of input data. The neural network model accuracy measurer 315 can compare a plurality of target data corresponding to the plurality of input data with the plurality of output values, and can determine whether each of the plurality of output values is a correct answer. The neural network model accuracy measurer 315 can determine a ratio of the number of output values determined to be a correct answer to the number of output values that are not a correct answer as the accuracy of the neural network model. The above-described method of measuring the accuracy of the neural network model is merely an example, and other implementations can exist. Accordingly, the method of measuring the accuracy of the neural network model can be implemented in various ways.

[0067] In an embodiment, when the accuracy of the neural network model is less than a preset threshold, the electronic device 300 can perform the operation of classifying the plurality of analog-to-digital converters and the operation of determining the input range again.

[0068] For example, when the accuracy of the neural network model is less than a preset threshold, the ADC group classifier 312 can increase the number of groups configured by the plurality of analog-to-digital converters or the number of output bits of the plurality of analog-to-digital converters. At this time, the number of output bits can indicate the number of bits representing the analog input signal. In an embodiment, the "number of output bits" can be referred to as "number of quantization bits". Thereafter, the ADC group classifier 312 can reclassify the plurality of analog-to-digital converters into a plurality of second analog-to-digital converter groups according to the increased number of groups or the increased number of output bits. The first analog-to-digital converter groups can be groups before reclassification, and the second analog-to-digital converter groups can be groups after reclassification. In an embodiment, the ADC group classifier 312 can reclassify the plurality of analog-to-digital converters into a plurality of second analog-to-digital converter groups while increasing the number of groups. When the number of groups is no longer increased, the ADC group classifier 312 can reclassify the plurality of analog-to-digital converters into a plurality of second analog-to-digital converter groups while increasing the number of output bits. In addition, the ADC input range optimizer 313 can determine an input range of each of the plurality of second analog-to-digital converter groups based on the input signal distribution information of the plurality of analog-to-digital converters. In this case, each of the plurality of analog-to-digital converters can operate according to the input range of the corresponding second analog-to-digital converter group among the plurality of second analog-to-digital converter groups. Accordingly, the electronic device 300 can repeat the operation of classifying the analog-to-digital converters and the operation of determining the input range until the accuracy of the neural network model is equal to or greater than the preset threshold.

[0069] In an embodiment, the electronic device 300 can classify the plurality of analog-to-digital converters into a plurality of default analog-to-digital converter groups, and then classify the plurality of default analog-to-digital converter groups into a plurality of first analog-to-digital converter groups.

[0070] For example, the ADC group classifier 312 can classify the plurality of analog-to-digital converters into a plurality of default analog-to-digital converter groups according to a preset unit. At this time, each of the plurality of default analog-to-digital converter groups can correspond to a layer unit or a hardware unit. For example, the ADC group classifier 312 can determine the analog-to-digital converters included in one layer as a default analog-to-digital converter group. As another example, the ADC group classifier 312 can determine the analog-to-digital converters included in one processing element (PE) as a default analog-to-digital converter group. As another example, the ADC group classifier 312 can determine the analog-to-digital converters included in one sub-array as a default analog-to-digital converter group. However, this is merely an example, and the unit to which the plurality of default analog-to-digital converter groups corresponds can be different.

[0071] Thereafter, the input signal distribution information generator 311 can generate input signal distribution information of the plurality of default ADC groups based on the analog input signals input to the ADCs included in each of the plurality of default ADC groups. For example, the input signal distribution information of each of the default ADC groups can indicate a distribution of the analog input signals input to the ADCs included in each of the default ADC groups. The ADC group classifier 312 can classify the plurality of default ADC groups into a plurality of first ADC groups based on the input signal distribution information of the plurality of default ADC groups. In addition, the ADC input range optimizer 313 can determine an input range of each of the plurality of first ADC groups based on the input signal distribution information of the plurality of default ADC groups.

[0072] Accordingly, the electronic device 300 can also apply the operations of classifying the plurality of ADCs and determining the input range to the plurality of default ADC groups, which have been described with respect to the plurality of ADCs.

[0073] The global buffer 320 can store weight data. The stored weight data can be provided to the computing circuit 330. In addition, when the weight data is updated, the global buffer 320 can store the updated weight data and provide the updated weight data to the computing circuit 330.

[0074] The global buffer 320 can be implemented with a random access memory (RAM), for example, a dynamic RAM (DRAM), an SRAM, or the like.

[0075] The computing circuit 330 can include a plurality of processing elements (PEs). The computing circuit 330 can perform a convolution operation, for example, an element-wise multiply-accumulate (MAC) operation. The plurality of processing elements (PEs), for example, the analog input signal generator, can perform the MAC operation on the input data and the weight data. The computing circuit 330 can provide a result of the MAC operation to the global buffer 320 or the controller 310.

[0076] In an embodiment, the computing circuit 330 can generate an analog input signal input to each of the plurality of ADCs. For example, the computing circuit 330 can perform the MAC operation on a plurality of input voltages corresponding to the input data and a plurality of weight data. The computing circuit 330 can output a plurality of output currents as a result of the MAC operation and convert the plurality of output currents into the analog input signal. Thereafter, the computing circuit 330 can provide the analog input signal to the global buffer 320 or the controller 310. In addition, the computing circuit 330 can output a digital output signal corresponding to the analog input signal using the plurality of ADCs. At this time, the plurality of ADCs can operate according to the optimized input range.

[0077] In an embodiment, the computing circuit 330 can perform the operation of the neural network model through the MAC operation on the input data and the weight data described above, the conversion from the output current to the analog input signal, and the conversion from the analog input signal to the digital output signal. Accordingly, the result of the neural network model for the input data can be represented as a value finally output through the MAC operation on the input data and the weight data described above, the conversion from the output current to the analog input signal, and the conversion from the analog input signal to the digital output signal.

[0078] Accordingly, according to an embodiment of the disclosed technology, it is possible to reduce the area occupied by the analog-digital converter and the power consumption by using a low-resolution analog-digital converter. In addition, according to an embodiment of the disclosed technology, it is possible to improve the accuracy of the neural network model while using a low-resolution analog-digital converter.

[0079] Figure 4 FIG. 1 is a diagram illustrating a computing circuit according to an embodiment of the disclosed technology.

[0080] Referring to Figure 4 The computing circuit 330 can include a plurality of processing elements PE. The plurality of processing elements PE can perform the MAC operation on the input data and the weight data. For example, the plurality of processing elements PE can independently operate and simultaneously perform the MAC operation. Accordingly, the MAC operation on a plurality of input data can be performed in parallel. In an embodiment, one layer included in the neural network can be implemented by one processing element PE.

[0081] In an embodiment, each of the plurality of processing devices PE can include a plurality of sub-arrays SA. The plurality of sub-arrays SA can perform the MAC operation on the input data and the weight data. For example, the plurality of sub-arrays SA can independently operate and simultaneously perform the MAC operation. Accordingly, the MAC operation on a plurality of input data can be performed in parallel. In an embodiment, one layer included in the neural network can be implemented by one processing element PE or one sub-array SA.

[0082] Figure 5A FIG. 5 is a diagram illustrating an example of a sub-array according to an embodiment of the disclosed technology.

[0083] Referring to Figure 5A The sub-array SA can include a crossbar array 510, a plurality of current-voltage converters (IVC), and a plurality of analog-digital converters (ADC).

[0084] The cross-point array 510 includes a plurality of resistive memory cells CELL each including a resistive element and arranged in a matrix form. In an embodiment, the resistive element can be implemented as a memristor. A resistance value of the resistive element can change according to an applied voltage, and the plurality of resistive memory cells CELL can store data using the resistance change.

[0085] In an embodiment, each resistive memory cell CELL can be implemented by including a random resistive memory cell such as a phase-change random access memory (PRAM) cell, a resistive random access memory (RRAM) cell, a magnetic random access memory (MRAM) cell, or a ferroelectric random access memory (FRAM) cell. Each of the plurality of resistive memory cells CELL can be connected to one of a plurality of rows and one of a plurality of columns.

[0086] The cross-point array 510 stores a plurality of weight data. At this time, the plurality of weight data can correspond to conductances G11, G12, G13, G21, G22, G23, G31, G32, and G33 of the plurality of resistive memory cells CELL. For example, the plurality of weight data can be stored in the plurality of resistive memory cells CELL by using a resistance change of the resistive element included in each of the plurality of resistive memory cells CELL. In addition, the cross-point array 510 can be configured to perform a multiply and accumulate (MAC) operation on a plurality of input voltages V1, V2, and V3 and the plurality of weight data. The cross-point array 510 can include a structure that performs the MAC operation. The cross-point array 510 can output a plurality of output currents I1, I2, and I3 according to a result of the MAC operation. For example, the plurality of input voltages V1, V2, and V3 can be input to the cross-point array 510 through a plurality of rows.

[0087] In Figure 5A , the sub-array SA includes 3x3 resistive memory cells CELL, but the number of resistive memory cells CELL is not limited to 3, and other numbers of resistive memory cells CELL can be included in the sub-array SA.

[0088] Each resistive memory cell CELL can correspond to one synapse or connection of a neural network, and can store one weight data. Accordingly, the mxn data stored in the cross-point array 510 can correspond to a weight matrix implemented in an mxn matrix form included in one layer described above with reference to Figure 2A and Figure 2B [Equation 1], for example, W.

[0089] The input voltages applied through the plurality of rows can correspond to the plurality of input voltages V1, V2, and V3 described above with reference to Figure 2A and Figure 2BThe n inputs a1, a2, …, and an received in one layer shown can correspond to an input matrix implemented in the form of an n x 1 matrix, that is, A of Equation 1 above.

[0090] The output currents output through the plurality of columns correspond to the results of performing MAC operations on the input data by the plurality of weights stored in the plurality of resistive memory cells. Figure 2A and Figure 2B The m outputs z1, z2, …, and zm output in one layer shown can correspond to an output matrix implemented in the form of an m x 1 matrix, that is, Z of [Equation 1] above.

[0091] As described above, the crossbar array 510 is implemented by storing a plurality of weight data having a matrix form in a plurality of resistive memory cells CELL. When input voltages V1, V2, and V3 corresponding to input data are input through a plurality of rows, output currents I1, I2, and I3 output through a plurality of columns can be the results of performing MAC operations by a neural network. When all the plurality of layers of the neural network are implemented in this method, an electronic device 300 that performs data storage and operations at once can be implemented.

[0092] A plurality of current-voltage converters IVC can be connected between the crossbar array 510 and a plurality of analog-to-digital converters ADC. The plurality of current-voltage converters IVC can convert the plurality of output currents I1, I2, and I3 into a plurality of analog input signals I_SIG1, I_SIG2, and I_SIG3. In other words, the computing circuit 330 can perform operations on the plurality of input voltages V1, V2, and V3 and the plurality of weight data using the crossbar array 510 and the plurality of current-voltage converters IVC, and can generate the analog input signals I_SIG1, I_SIG2, and I_SIG3 input to each of the plurality of analog-to-digital converters ADC based on the operation results. In Figure 5A In the sub-array SA, the plurality of current-voltage converters IVC includes three current-voltage converters IVC, but the number of current-voltage converters IVC is not limited to three and can include any other number of current-voltage converters IVC.

[0093] The plurality of analog-to-digital converters ADC can respectively receive the analog input signals I_SIG1, I_SIG2, and I_SIG3 and output digital output signals O_SIG1, O_SIG2, O_SIG3 corresponding to the analog input signals I_SIG1, I_SIG2, and I_SIG3. In Figure 5A In the sub-array SA, the plurality of analog-to-digital converters ADC includes three analog-to-digital converters ADC, but the number of analog-to-digital converters ADC is not limited to three and other numbers of analog-to-digital converters ADC can be included in the sub-array SA.

[0094] Figure 5B is a diagram illustrating another example of a sub-array according to an embodiment of the disclosed technology.

[0095] Referring to Figure 5B , the sub-array SA can include one analog-to-digital converter ADC. That is, according to an embodiment, the sub-array SA can share one analog-to-digital converter ADC. In this case, the number of analog-to-digital converters ADC is reduced compared to the embodiment shown in FIG. 1. Figure 5A Thus, the area of the analog-to-digital converter ADC can be reduced.

[0096] Figure 6 is a graph illustrating input signal distribution information according to an embodiment of the disclosed technology.

[0097] Figure 6 The input signal distribution information shown in FIG. 3 can indicate input signal distribution information of any one or more of the plurality of analog-to-digital converters or any one of the plurality of first analog-to-digital converter groups.

[0098] In Figure 6 , the vertical axis can represent the size of the analog input signal, and the horizontal axis can represent the number of analog input signals.

[0099] Referring to Figure 6 , the input signal distribution information generator 311 can generate input signal distribution information of the plurality of analog-to-digital converters by using a 3-sigma technique. For example, the input signal distribution information can be generated based on the mean μ and the standard deviation σ of the plurality of analog input signals. In an embodiment, the 3-sigma technique can be a rule of forming a normal distribution using values falling within a range of the mean μ to 3 standard deviations 3σ on both sides. The distribution range corresponding to the input signal distribution information can be determined as a range from μ-3σ to μ+3σ.

[0100] In an embodiment, the size value corresponding to the input signal distribution information can be represented as μ+3σ. However, according to an embodiment, the size value corresponding to the input signal distribution information can be set to a value other than μ+3σ.

[0101] Figure 7A is a graph illustrating an operation of classifying the plurality of analog-to-digital converters into a plurality of first analog-to-digital converter groups according to an embodiment of the disclosed technology.

[0102] In Figure 7A , for convenience of description, it is assumed that the number of analog-to-digital converters is 8, and the analog-to-digital converters are classified into two first analog-to-digital converter groups. However, according to an embodiment, the number of analog-to-digital converters and the number of first analog-to-digital converter groups can be different.

[0103] Referring to Figure 7AThe analog-to-digital converter group classifier 312 can classify the plurality of analog-to-digital converters ADC1 to ADC8 into a plurality of first analog-to-digital converter groups ADC_GROUP a and ADC_GROUP b based on the input signal distribution information of the analog-to-digital converters ADC1 to ADC8.

[0104] For example, the first analog-to-digital converter ADC1, the fourth analog-to-digital converter ADC4, the fifth analog-to-digital converter ADC5, the sixth analog-to-digital converter ADC6, the seventh analog-to-digital converter ADC7, and the eighth analog-to-digital converter ADC8 can have similar size values corresponding to the input signal distribution information. In this case, the analog-to-digital converter group classifier 312 can classify the first analog-to-digital converter ADC1, the fourth analog-to-digital converter ADC4, the fifth analog-to-digital converter ADC5, the sixth analog-to-digital converter ADC6, the seventh analog-to-digital converter ADC7, and the eighth analog-to-digital converter ADC8 into the a-th analog-to-digital converter group ADC_GROUP a.

[0105] In addition, the second analog-to-digital converter ADC2 and the third analog-to-digital converter ADC3 can have similar size values corresponding to the input signal distribution information. In this case, the analog-to-digital converter group classifier 312 can classify the second analog-to-digital converter ADC2 and the third analog-to-digital converter ADC3 into the b-th analog-to-digital converter group ADC_GROUP b.

[0106] On the other hand, when the plurality of analog-to-digital converters are reclassified into a plurality of second analog-to-digital converter groups, the operations illustrated in Figure 7A may be applied similarly. For example, when reclassifying after increasing the number of groups, the analog-to-digital converter group classifier 312 can reclassify the plurality of analog-to-digital converters ADC1 to ADC8 into three or more second analog-to-digital converter groups. As another example, when reclassifying after increasing the output bit number of the analog-to-digital converters, the analog-to-digital converter group classifier 312 can reclassify the plurality of analog-to-digital converters ADC1 to ADC8 into three or more second analog-to-digital converter groups according to the increased output bit number.

[0107] Figure 7B is a diagram illustrating an operation of classifying a plurality of default analog-to-digital converter groups into a plurality of first analog-to-digital converter groups according to an embodiment of the disclosed technology.

[0108] Unlike the diagram illustrated in Figure 7A , the analog-to-digital converter group classifier 312 can classify the plurality of analog-to-digital converters ADC1 to ADC8 into a plurality of first analog-to-digital converter groups ADC_GROUP a and ADC_GROUP b based on the input signal distribution information of the analog-to-digital converters ADC1 to ADC8. Figure 7BThe diagram shown illustrates the following operation: classifying multiple analog-to-digital converters (ADCs) into multiple default ADC groups DEFAULT GROUP1 through DEFAULT GROUP8, and then classifying the multiple default ADC groups DEFAULT GROUP1 through DEFAULT GROUP8 into multiple first ADC groups ADC_GROUP c and ADC_GROUP d. Each of the default ADC groups DEFAULT GROUP1 through DEFAULT GROUP8 can include multiple ADCs. For example, each of the multiple default ADC groups DEFAULT GROUP1 through DEFAULT GROUP8 can correspond to a layer unit or a hardware unit.

[0109] exist Figure 7B For ease of description, it is assumed that the default number of analog-to-digital converter (ADC) groups is 8, and these default ADC groups are classified into two first ADC groups. However, according to embodiments, the number of default ADC groups and the number of first ADC groups can be different.

[0110] Reference Figure 7B The analog-to-digital converter group classifier 312 can classify multiple default analog-to-digital converter groups DEFAULT GROUP1 to DEFAULT GROUP8 into multiple first analog-to-digital converter groups ADC_GROUP c and ADC_GROUP d based on the input signal distribution information of the default analog-to-digital converter groups DEFAULT GROUP1 to DEFAULT GROUP8.

[0111] For example, the first default ADC group DEFAULT GROUP1, the fourth default ADC group DEFAULT GROUP4, the fifth default ADC group DEFAULT GROUP5, the sixth default ADC group DEFAULT GROUP6, the seventh default ADC group DEFAULT GROUP7, and the eighth default ADC group DEFAULT GROUP8 can have similar magnitude values ​​corresponding to the input signal distribution information. In this case, the ADC group classifier 312 can classify the first default ADC group DEFAULT GROUP1, the fourth default ADC group DEFAULT GROUP4, the fifth default ADC group DEFAULT GROUP5, the sixth default ADC group DEFAULT GROUP6, the seventh default ADC group DEFAULT GROUP7, and the eighth default ADC group DEFAULT GROUP8 into the c-th ADC group ADC_GROUP c.

[0112] In addition, the second default ADC group DEFAULT GROUP 2 and the third default ADC group DEFAULT GROUP 3 can have similar size values corresponding to the input signal distribution information. In this case, the ADC group classifier 312 can classify the second default ADC group DEFAULT GROUP 2 and the third default ADC group DEFAULT GROUP 3 as the d-th ADC group ADC_GROUP d.

[0113] On the other hand, when the plurality of default ADC groups are reclassified as a plurality of second ADC groups, the operations illustrated in Figure 7B may be equally applied. For example, when reclassifying after increasing the number of groups, the ADC group classifier 312 can reclassify the plurality of default ADC groups DEFAULT GROUP 1 to DEFAULT GROUP 8 as three or more second ADC groups. As another example, when reclassifying after increasing the output bit number of the ADC, the ADC group classifier 312 can reclassify the plurality of default ADC groups DEFAULT GROUP 1 to DEFAULT GROUP 8 as three or more second ADC groups according to the increased output bit number.

[0114] In an embodiment, the operations illustrated in Figure 7A and Figure 7B may be performed using a clustering technique.

[0115] Figure 8A is a diagram illustrating an example of operations of determining an input range of each of a plurality of first ADC groups according to an embodiment of the disclosed technology.

[0116] Figure 8A The plurality of first ADC groups ADC_GROUP a and ADC_GROUP b of Figure 7A may represent the plurality of first ADC groups ADC_GROUP a and ADC_GROUP b of

[0117] In Figure 8A , it is assumed that a size value corresponding to input signal distribution information of a fifth ADC ADC5 among the ADCs ADC1, ADC4, ADC5, ADC6, ADC7, and ADC8 included in the a-th ADC group ADC_GROUP a is the largest. In an embodiment, the size value corresponding to the input signal distribution information can represent a sum of an average value of an analog input signal and 3 x standard deviation.

[0118] The fifth analog-digital converter ADC 5 can be determined as a reference analog-digital converter REF_ADC1 of the a-th analog-digital converter group ADC_GROUP a. In this case, the analog-digital converter input range optimizer 313 can determine a distribution range corresponding to the input signal distribution information of the fifth analog-digital converter ADC 5 as an input range of the a-th analog-digital converter group ADC_GROUP a. In an embodiment, the distribution range corresponding to the input signal distribution information can represent a range from -3 x standard deviation to +3 x standard deviation from an average value of the analog input signal. Accordingly, the input ranges of the analog-digital converters ADC1, ADC4, ADC6, ADC7, and ADC8 included in the a-th analog-digital converter group ADC_GROUP a can be optimized to the distribution range corresponding to the input signal distribution information of the fifth analog-digital converter ADC 5. The analog-digital converters ADC1, ADC4, ADC5, ADC6, ADC7, and ADC8 can operate according to the optimized input ranges.

[0119] It is assumed that a size value corresponding to the input signal distribution information of the second analog-digital converter ADC2 among the analog-digital converters ADC2 and ADC3 included in the b-th analog-digital converter group ADC_GROUP b is the largest.

[0120] The second analog-digital converter ADC2 can be determined as a reference analog-digital converter REF_ADC2 of the b-th analog-digital converter group ADC_GROUP b. In this case, the analog-digital converter input range optimizer 313 can determine a distribution range corresponding to the input signal distribution information of the second analog-digital converter ADC2 as an input range of the b-th analog-digital converter group ADC_GROUP b. Accordingly, the input range of the analog-digital converter ADC3 included in the b-th analog-digital converter group ADC_GROUP b can be optimized to the distribution range corresponding to the input signal distribution information of the second analog-digital converter ADC2. The analog-digital converters ADC2 and ADC3 can operate according to the optimized input ranges.

[0121] On the other hand, when determining the input range of each of the plurality of second analog-digital converter groups, the operations illustrated in FIGS. 10A and 10B can be equally applied. Figure 8A The operations illustrated in FIGS. 10A and 10B can be equally applied.

[0122] Figure 8B FIG. 11 is a diagram illustrating another example of operations of determining an input range of each of a plurality of first analog-digital converter groups according to an embodiment of the disclosed technology.

[0123] Figure 8B The plurality of first analog-digital converter groups ADC_GROUP c and ADC_GROUP d of FIG. 11 can represent Figure 7Ba plurality of first analog-digital converter groups ADC_GROUP c and ADC_GROUP d.

[0124] In Figure 8B In this case, it is assumed that a size value corresponding to input signal distribution information of a fifth default analog-digital converter group DEFAULT GROUP5 among the default analog-digital converter groups DEFAULT GROUP1, DEFAULT GROUP4, DEFAULT GROUP5, DEFAULT GROUP6, DEFAULT GROUP7, and DEFAULT GROUP8 included in the c-th analog-digital converter group ADC_GROUP c is the largest.

[0125] The fifth default analog-digital converter group DEFAULT GROUP5 can be determined as a reference default analog-digital converter group REF_GROUP 1 of the c-th analog-digital converter group ADC_GROUP c. In this case, the analog-digital converter input range optimizer 313 can determine a distribution range corresponding to the input signal distribution information of the fifth default analog-digital converter group DEFAULT GROUP5 as an input range of the c-th analog-digital converter group ADC_GROUP c. Accordingly, input ranges of the analog-digital converters included in the default analog-digital converter groups DEFAULT GROUP1, DEFAULT GROUP4, DEFAULT GROUP6, DEFAULT GROUP7, and DEFAULT GROUP8 can be optimized to the distribution range corresponding to the signal distribution information of the fifth default analog-digital converter group DEFAULT GROUP5. The analog-digital converters included in the default analog-digital converter groups DEFAULT GROUP1, DEFAULT GROUP4, DEFAULT GROUP5, DEFAULT GROUP6, DEFAULT GROUP7, and DEFAULT GROUP8 can operate according to the optimized input ranges.

[0126] It is assumed that a size value corresponding to input signal distribution information of a second default analog-digital converter group DEFAULT GROUP2 among the default analog-digital converter groups DEFAULT GROUP2 and DEFAULT GROUP3 included in the d-th analog-digital converter group ADC_GROUP d is the largest.

[0127] The second default analog-to-digital converter (ADC) group DEFAULT GROUP2 can be determined as the reference default ADC group REF_GROUP2 for the d-th ADC group ADC_GROUP d. In this case, the ADC input range optimizer 313 can determine the distribution range corresponding to the input signal distribution information of the second default ADC group DEFAULT GROUP2 as the input range of the d-th ADC group ADC_GROUP d. Therefore, the input range of the ADCs included in the default ADC group DEFAULT GROUP3 can be optimized to the distribution range corresponding to the input signal distribution information of the second default ADC group DEFAULT GROUP2. The ADCs included in the default ADC groups DEFAULT GROUP2 and DEFAULT GROUP3 can operate according to the optimized input range.

[0128] On the other hand, the same principle can be applied when determining the input range of each of the multiple second analog-to-digital converter groups. Figure 8B The operation shown.

[0129] Figure 9 This is a diagram illustrating the operation of an optimized analog-to-digital converter input range according to an embodiment of the disclosed technology.

[0130] exist Figure 9 In this context, we assume that the output bit width of the analog-to-digital converter is 2 bits.

[0131] Figure 9 The diagram shown indicates the input signal distribution information of the reference analog-to-digital converter. On the other hand, although for ease of description of the reference... Figure 9 The input signal distribution of the analog-to-digital converter is described, but the input signal distribution of the default analog-to-digital converter group can be applied in the same way.

[0132] Reference Figure 9The distribution range corresponding to the input signal distribution information of the reference analog-to-digital converter can be defined as μ-3σ to μ+3σ. In this case, the analog-to-digital converter input range optimizer 313 can optimize the input range of the analog-to-digital converter by linearly dividing the distribution range corresponding to the input signal distribution information. For example, the analog-to-digital converter whose input range is optimized can output a digital output signal (e.g., 00) corresponding to 0 for an analog input signal in the distribution range from μ-3σ to μ-(3 / 2)σ. As another example, the analog-to-digital converter whose input range is optimized can output a digital output signal (e.g., 01) corresponding to 1 for an analog input signal in the distribution range from μ-(3 / 2)σ to μ. As still another example, the analog-to-digital converter whose input range is optimized can output a digital output signal (e.g., 10) corresponding to 2 for an analog input signal in the distribution range from μ to μ+(3 / 2)σ. As still another example, the analog-to-digital converter whose input range is optimized can output a digital output signal (e.g., 11) corresponding to 3 for an analog input signal in the distribution range from μ+(3 / 2)σ to μ+3σ.

[0133] Figure 10 FIG. 1 is a flowchart illustrating a method of operating an electronic device for optimizing an input range of an analog-to-digital converter according to an embodiment of the disclosed technology.

[0134] Figure 10 The illustrated method, for example, can be performed by Figure 3 the electronic device 300 illustrated.

[0135] In step S1001, the electronic device 300 can generate an analog input signal input to each of the plurality of analog-to-digital converters based on an operation on the plurality of input voltages and the plurality of weight data.

[0136] In some embodiments, the electronic device 300 can perform a MAC operation on the plurality of input voltages and the plurality of weight data. In addition, the electronic device 300 can output a plurality of output currents according to a result of the operation. In addition, the electronic device 300 can convert the plurality of output currents into the analog input signal.

[0137] In step S1003, the electronic device 300 can generate input signal distribution information of the plurality of analog-to-digital converters.

[0138] In some embodiments, the electronic device 300 can calculate a mean value and a standard deviation of the analog input signal. In addition, the electronic device 300 can generate the input signal distribution information of the plurality of analog-to-digital converters using the mean value and the standard deviation.

[0139] In step S1005, the electronic device 300 can classify the plurality of analog-to-digital converters into a plurality of analog-to-digital converter groups based on the input signal distribution information of the plurality of analog-to-digital converters.

[0140] In some embodiments, the electronic device 300 can determine an analog-to-digital converter having a similar size value corresponding to the input signal distribution information among the plurality of analog-to-digital converters as any one of the plurality of first analog-to-digital converter groups. For example, the electronic device 300 can classify the analog-to-digital converters into the plurality of first analog-to-digital converter groups using a clustering technique.

[0141] In step S1007, the electronic device 300 can determine an input range of each of the plurality of first analog-to-digital converter groups based on the input signal distribution information of the plurality of analog-to-digital converters.

[0142] In some embodiments, in each of the plurality of first analog-to-digital converter groups, the electronic device 300 can determine an analog-to-digital converter having a maximum value corresponding to the input signal distribution information among the analog-to-digital converters included in each of the plurality of first analog-to-digital converter groups as a reference analog-to-digital converter.

[0143] In addition, the electronic device 300 can determine a distribution range corresponding to the input signal distribution information of the reference analog-to-digital converter determined in each of the plurality of first analog-to-digital converter groups as the input range of each of the plurality of first analog-to-digital converter groups.

[0144] In step S1009, the electronic device 300 can control the plurality of analog-to-digital converters to operate according to the input range of the corresponding analog-to-digital converter group among the plurality of analog-to-digital converter groups.

[0145] Figure 11 FIG. 11 is a flowchart illustrating a method of operating an electronic device for optimizing an input range of an analog-to-digital converter according to an additional embodiment of the disclosed technology.

[0146] Figure 11 The illustrated method, for example, can be performed by the electronic device 300 illustrated in FIG. 1. Figure 3 The electronic device 300 illustrated in FIG. 1 can perform.

[0147] In step S1101, the electronic device 300 can classify the plurality of analog-to-digital converters into a plurality of default analog-to-digital converter groups.

[0148] In step S1103, the electronic device 300 can generate an analog input signal input to each of the plurality of analog-to-digital converters based on an operation on the plurality of input voltages and the plurality of weight data.

[0149] In some embodiments, the electronic device 300 can perform a MAC operation on the plurality of input voltages and the plurality of weight data. In addition, the electronic device 300 can output a plurality of output currents according to a result of the operation. In addition, the electronic device 300 can convert the plurality of output currents into the analog input signal.

[0150] In step S1105, the electronic device 300 can generate input signal distribution information of the plurality of default ADC groups using an analog input signal input to an ADC included in each of the plurality of default ADC groups.

[0151] In some embodiments, the electronic device 300 can calculate a mean value and a standard deviation of the analog input signal. In addition, the electronic device 300 can generate the input signal distribution information of the default ADC group using the mean value and the standard deviation.

[0152] In step S1107, the electronic device 300 can classify the plurality of default ADC groups into a plurality of ADC groups based on the input signal distribution information of the plurality of default ADC groups.

[0153] In some embodiments, the electronic device 300 can determine a default ADC group having a similar size value corresponding to each of the input signal distribution information among the plurality of default ADC groups as an arbitrary one of the plurality of ADC groups. For example, the electronic device 300 can classify the plurality of default ADC groups into the plurality of ADC groups using a clustering technique.

[0154] In step S1109, the electronic device 300 can determine an input range of each of the plurality of ADC groups based on the input signal distribution information of the plurality of default ADC groups.

[0155] In some embodiments, in each of the plurality of ADC groups, the electronic device 300 can determine a default ADC group having a maximum value corresponding to the input signal distribution information among the default ADC groups included in each of the plurality of ADC groups as a reference default ADC group.

[0156] In addition, the electronic device 300 can determine a distribution range corresponding to the input signal distribution information of the reference default ADC group determined in each of the plurality of ADC groups as an input range of each of the plurality of ADC groups.

[0157] In step S1111, the electronic device 300 can obtain an output value of input data using a neural network model including a plurality of ADCs controlled to operate according to the determined input range.

[0158] In step S1113, the electronic device 300 can measure accuracy of the neural network model based on the output value.

[0159] In step S1115, the electronic device 300 can determine whether the accuracy is equal to or greater than a preset threshold.

[0160] When the accuracy is less than the preset threshold according to the determination result in step S1115, step S1117 can be performed. In step S1117, the electronic device 300 can increase the number of groups configured by the plurality of analog-to-digital converters or the output bit number of the plurality of analog-to-digital converters. Thereafter, the electronic device 300 can perform step S1107 again according to the increased number of groups or the increased output bit number. Accordingly, the electronic device 300 can perform steps S1107, S1109, and S1111 again while increasing the number of groups or the output bit number until the accuracy becomes equal to or greater than the preset threshold. On the other hand, the analog-to-digital converter group before the reclassification can be referred to as a first analog-to-digital converter group, and the analog-to-digital converter group after the reclassification can be referred to as a second analog-to-digital converter group.

[0161] On the other hand, when the accuracy is equal to or greater than the preset threshold according to the determination result in step S1115, step S1119 can be performed. In step S1119, the electronic device 300 can control the plurality of analog-to-digital converters to operate according to the input range of the corresponding analog-to-digital converter group among the plurality of analog-to-digital converter groups.

[0162] Only examples of the disclosed embodiments have been described. Various modifications and improvements can be made to the disclosed embodiments and other embodiments based on what is described or illustrated in this patent application document.

Claims

1. An electronic device comprising: Multiple analog-to-digital converters, each receiving an analog input signal and outputting a digital output signal corresponding to the analog input signal; An analog input signal generator generates an analog input signal for each of the plurality of analog-to-digital converters based on calculations on multiple input voltages and multiple weighted data. An input signal distribution information generator generates input signal distribution information for each of the plurality of analog-to-digital converters, the input signal distribution information indicating the distribution of the analog input signal; An analog-to-digital converter (ADC) group classifier classifies the multiple ADCs into multiple first ADC groups based on the input signal distribution information of the multiple ADCs; as well as An analog-to-digital converter (ADC) input range optimizer determines the input range of each group in the plurality of first ADC groups based on the input signal distribution information of the plurality of ADCs. Each of the plurality of analog-to-digital converters operates according to the input range of a corresponding first analog-to-digital converter group among the plurality of first analog-to-digital converter groups. The input signal distribution information generator calculates the average value and standard deviation of the analog input signal, and uses the average value and standard deviation to generate the input signal distribution information of the plurality of analog-to-digital converters.

2. The electronic device of claim 1, wherein the analog input signal generator comprises: An array includes multiple resistive memory cells for storing the multiple weight data, and the array receives the multiple input voltages and the multiple weight data, performs multiplication and accumulation operations using the multiple input voltages and the multiple weight data, and outputs multiple output currents based on the results of the operations; as well as A current-to-voltage converter is disposed between the array and the plurality of analog-to-digital converters, and converts the plurality of output currents into the analog input signals.

3. The electronic device of claim 1, wherein the input signal distribution information generator uses 3-sigma technology to generate the input signal distribution information of the plurality of analog-to-digital converters.

4. The electronic device of claim 1, wherein the analog-to-digital converter group classifier classifies analog-to-digital converters having similar magnitude values ​​corresponding to the input signal distribution information into one group of the plurality of first analog-to-digital converter groups.

5. The electronic device of claim 4, wherein the analog-to-digital converter group classifier uses clustering techniques to classify the plurality of analog-to-digital converters into the plurality of first analog-to-digital converter groups.

6. The electronic device of claim 1, wherein the analog-to-digital converter input range optimizer determines any one of the analog-to-digital converters included in each of the plurality of first analog-to-digital converter groups as a reference analog-to-digital converter, and determines the distribution range corresponding to the input signal distribution information of the reference analog-to-digital converter as the input range of each of the plurality of first analog-to-digital converter groups.

7. The electronic device of claim 6, wherein the reference analog-to-digital converter is an analog-to-digital converter having a maximum value corresponding to the input signal distribution information among the analog-to-digital converters included in each of the plurality of first analog-to-digital converter groups.

8. The electronic device of claim 1, wherein the analog-to-digital converter group classifier classifies the plurality of analog-to-digital converters into a plurality of default analog-to-digital converter groups.

9. The electronic device of claim 8, wherein each of the plurality of default analog-to-digital converter groups corresponds to a layer unit or a hardware unit.

10. The electronic device of claim 8, wherein the input signal distribution information generator generates input signal distribution information for the plurality of default analog-to-digital converter groups based on analog input signals input to the analog-to-digital converters included in each of the plurality of default analog-to-digital converter groups. The analog-to-digital converter (ADC) group classifier classifies the multiple default ADC groups into multiple first ADC groups based on the input signal distribution information of the multiple default ADC groups, and The analog-to-digital converter input range optimizer determines the input range of each of the plurality of first analog-to-digital converter groups based on the input signal distribution information of the plurality of default analog-to-digital converter groups.

11. The electronic device according to claim 1, further comprising: A neural network model controller uses a neural network model to obtain output values ​​for input data, the neural network model being applied to the plurality of analog-to-digital converters, each analog-to-digital converter operating according to the input range of a corresponding first analog-to-digital converter group; and A neural network model accuracy measurer measures the accuracy of the neural network model based on the output value.

12. The electronic device of claim 11, wherein the analog-to-digital converter group classifier increases the number of groups to be classified by the plurality of analog-to-digital converters or the number of output bits of the plurality of analog-to-digital converters in response to the accuracy being less than a preset threshold.

13. A method of operating an electronic device, the method comprising: Multiple analog-to-digital converters are categorized into multiple default analog-to-digital converter groups; The analog input signals are generated for the multiple analog-to-digital converters using computation based on multiple input voltages and multiple weight data. Based on the analog input signal, the input signal distribution information of the multiple default analog-to-digital converter groups is generated; Based on the input signal distribution information of the multiple default analog-to-digital converter groups, the multiple default analog-to-digital converter groups are classified into multiple first analog-to-digital converter groups; Based on the input signal distribution information of the plurality of default analog-to-digital converter groups, the input range of each of the plurality of first analog-to-digital converter groups is determined; and The plurality of analog-to-digital converters are controlled to operate according to the input range of the corresponding first analog-to-digital converter group among the plurality of first analog-to-digital converter groups. The generation of the input signal distribution information includes: Calculate the average value and standard deviation of the analog input signal; and The input signal distribution information of the plurality of default analog-to-digital converter groups is generated using the average value and the standard deviation.

14. The method of claim 13, wherein generating the analog input signal comprises: Perform multiplication and accumulation operations on the multiple input voltages and the multiple weighted data; Multiple output currents are output based on the results of the multiplication and accumulation operations; and The plurality of output currents are converted into the analog input signal.

15. The method of claim 13, wherein classifying into the plurality of first analog-to-digital converter groups comprises classifying default analog-to-digital converters having similar magnitude values ​​corresponding to the input signal distribution information into one group of the plurality of first analog-to-digital converter groups.

16. The method of claim 15, wherein classifying the plurality of first analog-to-digital converter groups comprises classifying the plurality of default analog-to-digital converter groups into the plurality of first analog-to-digital converter groups using a clustering technique.

17. The method of claim 13, wherein determining the input range comprises: The default analog-to-digital converter (ADC) group with the maximum value corresponding to the input signal distribution information among the default ADC groups included in each of the plurality of first ADC groups is determined as the reference default ADC group in each of the plurality of first ADC groups; and The distribution range corresponding to the input signal distribution information of the reference default analog-to-digital converter group determined in each of the plurality of first analog-to-digital converter groups is determined as the input range of each of the plurality of first analog-to-digital converter groups.

18. The method of claim 13, further comprising: A neural network model is used to obtain output values ​​for input data, the neural network model being applied to the plurality of analog-to-digital converters, the plurality of analog-to-digital converters being controlled to operate according to a determined input range; The accuracy of the neural network model is measured based on the output value; as well as In response to the accuracy being less than a preset threshold, the number of groups to be classified by the plurality of analog-to-digital converters or the number of bits output by the plurality of analog-to-digital converters is increased.

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