An adaptive comparator delay loop SAR ADC
By adaptively adjusting the comparator loop delay module, the problem of wasted comparator loop delay time in traditional SARADCs is solved, and efficient operation of high-speed SARADCs is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2022-08-24
- Publication Date
- 2026-05-29
AI Technical Summary
In traditional SARADCs, the comparator loop delay time is wasted, making it difficult to achieve high-speed operation.
An adaptive comparator delay loop is adopted. By adaptively adjusting the comparator loop delay module, the comparator loop delay is adjusted according to the inconsistency of the MSB to LSB establishment time in the DAC capacitor array, so as to match the comparator reset time and DAC voltage establishment time.
While ensuring accurate DAC voltage establishment, the comparator loop delay time is minimized to improve ADC speed, and the time utilization rate can reach 100%.
Smart Images
Figure CN115412099B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of analog integrated circuit design, specifically to a SARADC with an adaptive comparator delay loop, which can be applied to ultra-high-speed SARADCs. Background Technology
[0002] Traditional SAR ADCs struggle to achieve high speeds, but asynchronous logic timing makes high-speed SAR ADCs possible. The asynchronous timing logic of SAR divides the ADC operation into three parts: DAC voltage setup, comparator voltage comparison, and SAR logic switching. These three parts continuously cycle through each other.
[0003] Using a non-binary capacitor array can increase the DAC voltage setup error and reduce the DAC voltage setup time, while asynchronous sequential logic can significantly reduce the SAR logic switching time. During ADC quantization, the comparator constantly switches between compare and reset states. Typically, the comparator operates very quickly, entering the reset state after one comparison and then entering the next comparison state after the reset. It is highly possible that the comparator starts working before the DAC voltage setup is complete. To ensure that each comparator start-up comparison occurs after the DAC voltage setup is complete, a delay module is added to the comparator's internal loop. In a typical comparator loop delay module, the delay is the same for each operation. However, because the DAC capacitor value decreases sequentially from MSB (most significant bit) to LSB (least significant bit), the required DAC voltage setup time for each bit is different. The comparator loop delay must be the MSB setup time; otherwise, the final quantization result will be incorrect. This results in wasted comparator loop delay time, which is detrimental to the implementation of high-speed SAR ADCs.
[0004] To address this issue, existing technologies can reduce some wasted time by setting control bits to uniformly adjust the comparator's loop delay. However, since the settling times of each DAC voltage are different, it is not possible to achieve a high degree or even a perfect match between the comparator delay time and the DAC voltage settling time, thus limiting the effectiveness. Summary of the Invention
[0005] To address the aforementioned problems and shortcomings, and to resolve the issue of wasted time due to comparator loop delay in existing SARADCs, which hinders the implementation of high-speed SARADCs, this invention proposes an adaptive comparator loop delay SARADC. The basic idea of this invention is to adaptively adjust the comparator loop delay based on the inconsistency in the MSB-LSB establishment time within the DAC capacitor array. This minimizes the comparator loop delay time while ensuring accurate DAC voltage establishment, and can be applied to ultra-high-speed SARADCs.
[0006] An adaptive comparator delay loop SAR ADC includes a DAC capacitor array, comparator enable logic, a loop delay module, and SAR logic circuitry.
[0007] The DAC capacitor array consists of cascaded sampling capacitors and switches to sample the input signal.
[0008] The comparator enable logic consists of a sampling clock and an adjustable delay unit.
[0009] After the sampling clock (CLKT) is sampled by the DAC capacitor array, it is delayed by the adjustable delay unit to generate the comparator enable signal, triggering the comparator's first comparison.
[0010] The adjustable delay unit consists of an inverter and a transmission gate, controlling the start time of the comparator's first comparison to ensure the DAC voltage of the first capacitor is fully established. The size of the capacitor represents the degree of delay; the larger the capacitance, the greater the delay.
[0011] The loop delay module consists of an adjustable delay stage and a fixed delay stage. The fixed delay stage provides the comparator reset time required for the least significant bit DAC voltage setup time. Then, the adjustable delay stage adaptively controls the reset time T of the comparator for the (i+1)th comparison as the DAC voltage setup time required for the (i+1)th comparison changes. CMP_RST Matching the settling time of the DAC voltage, 1≤i≤M-1, where M is the number of capacitors in the DAC capacitor array.
[0012] The fixed delay stage is composed of cascaded inverters to provide a fixed delay.
[0013] The adjustable delay stage consists of an inverter and a transmission gate. The delay is changed by the high or low level digital signal dc[N:0] from the external SPI module and the delay control signal df[N:0] generated by the internally designed adaptive adjustment module. N is the number of the adjustable delay stage. The digital signal from the external SPI module ensures that the remaining time is allocated as much as possible to the establishment of the DAC voltage while ensuring that the ADC quantization is completed.
[0014] The adaptive adjustment module adjusts the delay by generating a control signal from the flag signal after each quantization using internal logic. Specifically:
[0015] The comparator reset time T of the (i+1)th comparison cycle CMP_RSTControlled by dc[N:0] and df[N:0], both are active high. dc[N:0] is provided by an external SPI module. By adjusting dc[N:0], as much remaining time as possible is allocated to the establishment of each DAC voltage, thus ensuring the accuracy of the ADC.
[0016] df[N:0] is generated by the adaptive adjustment module. For N-level delay control, there is one normally open stage, and the remaining N-1 stages are controlled by control bits to make the comparator's reset time perfectly match the DAC voltage establishment time.
[0017] The logic of the adaptive adjustment module: Qi is the flag indicating the completion of the i-th quantization of the SAR ADC. During ADC sampling, all Qi signals are reset to low level. After the i-th bit is quantized, Qi becomes high level until the next ADC sampling cycle. Therefore, when the Qi signal transitions from low to high level is determined by when the comparator completes quantization. The Qi signal indicating the completion of each quantization bit is connected by an XOR gate and an AND gate to generate a delay control signal df[N:0]. Therefore, when the i-th bit is quantized, Qi becomes high level, and the generated delay control signal df[N:0] adaptively controls the reset time of the (i+1)-th comparator to match the establishment time of the DAC voltage.
[0018] Timing of the adaptive adjustment module: The change of df[N:0] as Qi changes from low to high. The time corresponding to the column containing Qi is the reset delay time of the (i+1)th comparator in the design, which corresponds one-to-one with the setup time of the DAC voltage after the MSB (i.e., the (i+1)th) iteration. df[N:0] has N control words, which means there are N adjustable delay levels. Adding one fixed delay level, there are a total of N+1 levels of adjustment. Increasing the number of delay levels can improve the accuracy of each delay level and more precisely adjust the comparator's reset time T. CMP_RST The matching degree with the DAC voltage settling time is adjusted until a perfect match is achieved, resulting in 100% time utilization.
[0019] The SAR logic circuit consists of a latch circuit and a logic circuit that controls the switching of the DAC capacitor array. The result of the comparator comparison is latched by the latch circuit. After latching, the logic circuit generates a control signal to control the switching of the DAC capacitor array, performing successive approximation quantization on the sampled input signal.
[0020] In the adaptive comparator delay loop SAR ADC of the present invention, after the input signal is sampled by the DAC capacitor array during the sampling phase, the comparator enable logic enables the first comparison; the output signal after the first comparison is received by the SAR logic circuit, which controls the switching of the DAC capacitor array to establish the DAC voltage for the (i+1)th time. After the DAC voltage is established, the comparator performs the (i+1)th comparison again, and this process is repeated until the least significant bit quantization is completed. The entire ADC completes one sampling and quantization of the input signal.
[0021] Furthermore, for different DAC setup times, the precision of each adjustment can be increased by increasing the number of adjustable delay stages N. However, simply increasing precision would result in an excessively high number of adjustable delay stages, leading to significant waste of area and power consumption. Further adjustments can be made to the capacitor values of the adjustable delay stages to specifically set the delay value of each stage, ensuring that the reset time T of the (i+1)th comparator is optimal. CMP_RST The settling time of the DAC voltage is matched until 100% time utilization is achieved, reducing the number of adjustable delay stages and optimizing area and power consumption.
[0022] In summary, this invention, by setting the number N of the adjustable delay stages of the loop delay module, enables the comparator to reset the time T for each subsequent comparison after the first comparison. CMP_RST By matching the DAC voltage establishment time, the comparator loop delay is adaptively adjusted to reduce the comparator loop delay time. Depending on the different designs of the delay stages N in the adaptive adjustment module, the time utilization rate can reach 100%. This invention minimizes the comparator loop delay time to the greatest extent while ensuring accurate DAC voltage establishment; in the embodiment, the ADC time utilization rate can reach 98.54%, significantly improving the ADC speed. Attached Figure Description
[0023] Figure 1 This is a logic block diagram of a single SAR unit with a comparator.
[0024] Figure 2 This is a timing diagram of the comparator in a traditional SAR structure.
[0025] Figure 3 This is a timing diagram of the loop delay of the adaptive comparator of the present invention.
[0026] Figure 4 This is a circuit diagram of the adaptive comparator loop delay of the present invention.
[0027] Figure 5 This is a circuit schematic of the adjustable delay unit that controls the DAC setup time of the MSB in the embodiment.
[0028] Figure 6This is a circuit schematic for the adjustable delay stage of the subsequent comparison period in the embodiment.
[0029] Figure 7 This is a logic diagram of the adaptive adjustment module for subsequent comparison periods in the embodiment.
[0030] Figure 8 This is a timing diagram of the adaptive adjustment module for subsequent comparison cycles in the embodiment.
[0031] Figure 9 This is the circuit schematic of an eighth-order loop delay module.
[0032] Figure 10 The circuit diagram of a fifth-order loop delay module with adjusted delay unit capacitance. Detailed Implementation
[0033] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.
[0034] In traditional binary SAR ADCs, to ensure the accuracy of each quantization, the setup error of the DAC voltage should be less than LSB / 2. The setup time is expressed as:
[0035] t(i)=R(i)*C(i)*ln(2*W(i))=τln(2*W(i))
[0036] In the formula, R(i) is the on-resistance of the sampling switch, C(i) is the capacitor to be charged and discharged, and W(i) is the weight of the i-th capacitor. In the DAC capacitor array, the sampling switch and the sampling capacitor change at the same ratio, so τ is a time constant. Therefore, the settling time of the DAC voltage is affected by the weight of each capacitor.
[0037] In non-binary SARADCs, due to the presence of redundancy, the setup error of the DAC voltage does not necessarily have to be LSB / 2. The redundancy R(i) in the i-th comparison cycle is expressed as:
[0038]
[0039] In the formula, W(j) is the weight of the j-th capacitor in the DAC capacitor array. Therefore, the DAC voltage settling error can be increased to R(i)×LSB / 2, which shortens the DAC voltage settling time. The non-binary DAC voltage settling time can be expressed as:
[0040]
[0041] This embodiment is a non-binary SARADC based on integer weights. The capacitor weights, redundancy design, and DAC voltage settling time for each comparison cycle are shown in Table 1.
[0042] Table 1:
[0043] Number of digits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Weight W(i) 2048 1056 544 304 176 96 48 24 16 8 4 4 2 1 Redundancy R(i) 236 176 140 76 28 12 12 12 4 4 4 N / A N / A N / A DAC setup time T(i) 2.9τ 2.6τ 2.1τ 2.1τ 2.6τ 2.8τ 2.1τ 1.4τ 2.1τ 1.4τ 0.7τ 2.1τ 1.4τ 0.7τ
[0044] Figure 1 This is a schematic diagram of a single SAR unit circuit with a comparator. The SAR unit consists of a quasi-dynamic latch, a clock generation circuit, and an EOS (End of SAR) generation circuit. During quantization, the clock generation circuit controls the comparator to start the first comparison. After the comparison is completed, the SAR logic is enabled. After the SAR unit finishes latching, it generates an EOS (End of SAR) signal, which is then delayed by an inverter and returned to the clock generation circuit to control the start of the next comparison.
[0045] Figure 2 This is a timing diagram of the comparator in a traditional SAR structure. Where T... CMP T represents the comparator's operating time. CMP_RST The comparator's reset time is determined by the inverter's delay (T) on the transmission path. INV ) and additional logical delay (T) to meet the delay requirements d Composed of ) T CLK It is the logic delay of the clock generation circuit. T d1 It is the time the clock waits. T SAR It is the logic delay of the quasi-dynamic latch. T SW This is the delay time of the DAC switching circuit. T DAC This refers to the settling time of the DAC capacitor array. In traditional SARADCs, to ensure the correctness of each bit quantization result, T... CMP_RST A constant delay time with sufficient margin must be selected, that is, the setup time of the DAC in the MSB, which greatly limits the time utilization of the ADC.
[0046] Figure 3 This is the timing diagram for the adaptive comparator loop delay proposed in this embodiment. In this embodiment, an adaptive asynchronous logic comparator loop delay is designed to optimize the reset time of the comparator in each comparison cycle, thereby improving time utilization. The delay is related to the DAC voltage setup time T required for each comparison. DAC The change in the comparator's reset time T CMP_RST Corresponding matching is also performed, reducing the overall loop delay and facilitating the implementation of high-speed SARADCs. In this SAR logic, the clock generation circuit generates the necessary clock for the SAR unit before the comparator comparison is completed, which also improves the speed of the SAR logic.
[0047] Figure 4 This is the circuit schematic for the adaptive comparator loop delay proposed in this invention. After sampling is completed, the sampling clock (CLK)... TThe falling edge of the clock is controlled by the adjustable delay unit dt[3:0], which triggers the first comparison of the comparator. The subsequent clock cycle is generated by the comparator loop of the adaptive asynchronous logic. That is, the comparison results DCMP and DCMN of the comparator plus the adaptive delay loop dc[2:0] and df[2:0] are used to control the start time of each comparison in order to obtain the optimal delay.
[0048] Figure 5 This is a circuit schematic of the adjustable delay unit controlling the DAC setup time of the MSB in the embodiment. dt[3:0] are control bits, provided by an external SPI. Adjusting dt[3:0] to a high level controls the sampling clock CLK. T The falling edge is delayed to generate the signal CLK. OUT Then clk is generated. c When the signal enable comparator is turned on for the first time, the comparator can be turned on quickly after the DAC voltage of the MSB is fully established by adjusting the dt[3:0] control word, thus ensuring the speed and accuracy of the ADC.
[0049] Figure 6 This is a circuit schematic for the adjustable delay stage in subsequent comparison cycles in the embodiment. In the adaptive comparator loop delay logic designed in this invention, the comparator reset time T in subsequent comparison cycles... CMP_RST The ADC is jointly controlled by dc[2:0] and df[2:0], both of which are active high. dc[2:0] is provided by an external SPI, and by adjusting dc[2:0], as much remaining time as possible can be allocated to the establishment of each DAC, ensuring the accuracy of the ADC. df[2:0] is generated by adaptive asynchronous logic. This embodiment designs a four-level delay control, with one normally open level and the other three controlled by control bits. The four-level control design is only a choice made after considering the overall overhead and performance improvement for this embodiment. If overhead is not a concern, more delay levels can be implemented to ensure that the comparator's reset time perfectly matches the DAC establishment time.
[0050] Figure 7 This is the logic diagram of the adaptive adjustment module for subsequent comparison cycles in the embodiment. Qi is the flag indicating that the i-th quantization of the SAR ADC is complete. When the ADC samples, all Qi are reset to low level. After the i-th bit is quantized, Qi becomes high level until the next ADC sampling cycle. Among them, Q2, Q4, Q6, Q14 control df[2] through XOR gate and AND gate, Q7, Q8, Q9, Q11 control df[1] through XOR gate and AND gate, and Q10, Q11, Q13, Q14 control df[0] through XOR gate and AND gate. Therefore, when the i-th bit is quantized, Qi becomes high level, which can control the reset time of the i+1 comparator to match the establishment time of the DAC voltage.
[0051] Figure 8This is a timing diagram of the adaptive adjustment module for subsequent comparison cycles in this embodiment. It represents the change of df[2:0] as Qi changes from low to high. The settling times of each DAC voltage in this embodiment are shown in Table 1: 2.9τ, 2.6τ, 2.1τ, 2.1τ, 2.6τ, 2.8τ, 2.1τ, 1.4τ, 2.1τ, 1.4τ, 0.7τ, 2.1τ, 1.4τ, 0.7τ. Figure 8 The time corresponding to the column containing Qi is the reset delay time of the (i+1)th comparator in the design, which corresponds one-to-one with the establishment time of the subsequent DAC voltages excluding the MSB. df[2:0] has three control words, meaning there are three adjustable delay levels, plus one fixed delay level, for a total of four levels of control. Each delay level is designed to be 0.7τ. Increasing the number of delay levels can improve the accuracy of each delay level and more precisely adjust the comparator's reset time. For other ADCs with different weight designs, the comparator reset time and DAC voltage establishment time can also be matched by changing the delay time of each level or adjusting the number of delay levels.
[0052] Combination Figure 8 , Figure 7 It can be concluded that when Q1 to Q14 are all low, df[2:0] are all high; when Q2 becomes high, df[2] becomes low, and df[1:0] remains high; when Q4 becomes high, df[2] returns to high, and df[1:0] remains high; when Q6 becomes high, df[2] becomes high, and df[1:0] remains high; when Q7 becomes high, df[2] remains low, df[1] becomes low, and df[0] remains high; when Q8 becomes high, df[2] remains low, df[1] returns to high, and df[0] remains high; when Q9 After Q10 becomes high, df[2] remains low, df[1] becomes low, and df[0] remains high. After Q10 becomes high, df[2] remains low, and df[0] becomes low. After Q11 becomes high, df[2] remains low, df[1] becomes high, and df[0] becomes high. After Q12 becomes high, df[2] remains low, df[1] becomes low, and df[0] remains high. After Q13 becomes high, df[2] remains low, df[1] remains low, and df[0] becomes low. This process repeats after Q14 becomes high.
[0053] Figure 9This is a schematic diagram of an eight-stage adjustable loop delay module. To address the settling time of different DAC voltages, the number of adjustable delay stages can be increased to improve the accuracy of each adjustment. The diagram shows eight stages: seven adjustable delay stages plus one fixed delay stage. Each stage has a control step size of 0.35τ, allowing for an adjustment range from 0.35τ to 2.8τ. Theoretically, increasing the delay to 28 stages would achieve an accuracy of 0.1τ per stage, resulting in 100% time utilization. Figure 10 The schematic diagram of the adjustable loop delay module circuit with fifth-order delay and changed capacitor value of the delay unit is shown. For different DAC voltage set-up times, the delay controlled by each control word can be specifically set by increasing the capacitor value. In the figure, df[3] has a control step of 0.2τ, df[2] has a control step of 0.5τ, and df[1:0] has a control step of 0.7τ. With the addition of a first-order fixed delay, this structure can realize the adjustment of the comparator reset time delay from 0.7τ, 1.4τ, 2.1τ, 2.6τ, and 2.8τ. Then the comparator reset time and DAC voltage set-up time can be perfectly matched, achieving 100% time utilization. Figure 9 and Figure 10 The structural method only requires adjusting the number of delay stages and the value of the capacitor to cover the different comparator delay times caused by the different DAC voltage set-up times in all ADC designs, thereby maximizing time utilization.
[0054] Table 2 (Comparison of time utilization between traditional SARADC and the ADC of this invention):
[0055] Traditional SAR ADC Second-order modulation ADC Fourth-order ADC Fifth-order modulated ADC Total time required to build 27τ 27τ 27τ 27τ Required quantification time 40.6τ 32.3τ 27.4τ 27τ Time utilization 66.50％ 83.59％ 98.40％ 100％
[0056] In this example, the adaptive comparator loop delay module described above is applied to a high-speed SAR ADC. Table 2 shows a comparison of the time utilization of SAR ADCs using different control schemes. The quantization time required by the traditional delay SAR ADC is 14 times the setup time of the highest bit DAC voltage, which is 40.6τ, resulting in a time utilization of 66.5%. The quantization time of the second-order controlled ADC is 32.3τ, with a time utilization of 83.59%. The quantization time of the fourth-order controlled ADC is 27.4τ, with a time utilization of 98.4%. The quantization time of the fifth-order controlled ADC, which also changes the capacitance value, is 27τ, achieving a time utilization of 100%, demonstrating a significant improvement.
[0057] As can be seen from the above embodiments, this invention, based on the inconsistency in the MSB to LSB establishment time in the DAC capacitor array, sets the number N of the adjustable delay stage of the loop delay module so that after the first comparison, the comparator adjusts the reset time T for each subsequent comparison. CMP_RSTBy matching the DAC voltage establishment time, the comparator loop delay is adaptively adjusted to reduce the comparator loop delay time. Depending on the different designs of the delay stages N in the adaptive adjustment module, the time utilization rate can reach 100%. This invention minimizes the comparator loop delay time to the greatest extent while ensuring accurate DAC voltage establishment.
Claims
1. A SAR ADC with an adaptive comparator delay loop, characterized in that: This includes a DAC capacitor array, comparator enable logic, loop delay module, and SAR logic circuit; The DAC capacitor array consists of cascaded sampling capacitors and switches, which samples the input signal. The comparator enable logic consists of a sampling clock and an adjustable delay unit; After the sampling clock CLKT is sampled by the DAC capacitor array, it is delayed by the adjustable delay unit to generate the comparator enable signal, which triggers the comparator's first comparison. The adjustable delay unit consists of an inverter and a transmission gate, which controls the start time of the first comparison of the comparator, so that the DAC voltage of the first capacitor is fully established. The loop delay module consists of an adjustable delay stage and a fixed delay stage. The fixed delay stage provides the comparator reset time required for the least significant bit DAC voltage setup time. Then, the adjustable delay stage adaptively controls the reset time T of the comparator for the (i+1)th comparison as the DAC voltage setup time required for the (i+1)th comparison changes. CMP_RST Matching the settling time of the DAC voltage, 1≤i≤M-1, where M is the number of capacitors in the DAC capacitor array; The fixed delay stage is composed of cascaded inverters to provide a fixed delay. The adjustable delay stage consists of an inverter and a transmission gate. The delay is changed by the high or low level digital signal dc[N:0] from the external SPI module and the delay control signal df[N:0] generated by the internally designed adaptive adjustment module. N is the number of the adjustable delay stage. The digital signal from the external SPI module ensures that the remaining time is allocated as much as possible to the establishment of the DAC voltage while ensuring that the ADC quantization is completed. The adaptive adjustment module adjusts the delay by generating a control signal from the flag signal after each quantization step using internal logic. Specifically: The comparator reset time T of the (i+1)th comparison cycle CMP_RST It is jointly controlled by dc[N:0] and df[N:0], both of which are active high; dc[N:0] is provided by an external SPI module. By adjusting dc[N:0], as much of the remaining time as possible is allocated to the establishment of each DAC voltage, so as to ensure the accuracy of the ADC. df[N:0] is generated by the adaptive adjustment module. For N-level delay control, there is one normally open stage, and the remaining N-1 stages are controlled by control bits to make the comparator's reset time perfectly match the DAC voltage establishment time. The logic of the adaptive adjustment module: Qi is the flag indicating that the i-th quantization of the SAR ADC is complete. When the ADC samples, all Qi are reset to low level. After the i-th bit is quantized, Qi becomes high level until the next cycle of ADC sampling. The Qi signal, which indicates that each bit has been quantized, is connected by an XOR gate and an AND gate to generate a delay control signal df[N:0]. When the quantization of the i-th bit is completed, Qi becomes high, and the generated delay control signal df[N:0] can adaptively control the reset time of the (i+1)-th comparator to match the establishment time of the DAC voltage. Timing of the adaptive adjustment module: As Qi changes from low to high, the time corresponding to the column containing Qi is the reset delay time of the (i+1)th comparator in the design, which corresponds one-to-one with the establishment time of the (i+1)th DAC voltage; df[N:0] has N control words, which are N levels of adjustable delay. Adding the fixed delay level, there are a total of N+1 levels of adjustment. By increasing the number of delay levels, the accuracy of each delay level is improved, allowing for more precise adjustment of the comparator's reset time T. CMP_RST The matching degree with the DAC voltage settling time is adjusted until a perfect match is achieved, resulting in 100% time utilization. The SAR logic circuit consists of a latch circuit and a logic circuit that controls the switching of the DAC capacitor array. The result of the comparator comparison is latched by the latch circuit. After latching, the logic circuit generates a control signal to control the switching of the DAC capacitor array, and performs successive approximation quantization on the sampled input signal. During the sampling phase, after the input signal is sampled by the DAC capacitor array, the comparator enable logic enables the first comparison. The output signal after the first comparison is received by the SAR logic circuit, which controls the switching of the DAC capacitor array to establish the DAC voltage for the (i+1)th time. After the DAC voltage is established, the comparator performs the (i+1)th comparison again. This process is repeated until the least significant bit is quantized. The entire ADC completes one sampling and quantization of the input signal.
2. The SAR ADC with adaptive comparator delay loop as described in claim 1, characterized in that: The number of adjustable delay stages, N, is greater than or equal to 3.
3. The SAR ADC with adaptive comparator delay loop as described in claim 1, characterized in that: By adjusting the capacitor value of the adjustable delay stage, the delay value of each stage can be specifically set, so that the reset time T of the (i+1)th comparator is... CMP_RST The settling time of the DAC voltage is matched to reduce the number of adjustable delay stages, thereby optimizing area and power consumption.
4. The SAR ADC with adaptive comparator delay loop as described in claim 1, characterized in that: It is applied to ultra-high-speed SARADC.