A Polarization Mode Dispersion Adaptive Equalizer Based on Approximate Computing

Abstract

The present invention belongs to the technical field of coherent optical communication, and specifically relates to a polarization mode dispersion adaptive equalizer based on approximate calculation. The adaptive equalizer of the present invention is a 16-channel parallel equalizer, and each channel adopts a 9-1 equalizer structure; in this parallel equalizer, a parameter sharing scheme is adopted, and all multipliers are implemented using approximate multipliers; the present invention can reduce the parameters of the equalizer by 38.9%, greatly reduce the scale of the parameters, and reduce the computational complexity; this multiplier can reduce the number of full adders by about 44.6% while ensuring that the average absolute error loss is only 0.31; it can greatly reduce the area and power consumption while ensuring a very small loss of calculation accuracy; the comprehensive results show that compared with the fixed-point structure, the area of the approximate base equalizer is increased by 27.86%, and the power efficiency is increased by 37.88%.

Description

Technical Field

[0001] The present invention belongs to the technical field of coherent optical communication, and particularly relates to a polarization mode dispersion adaptive equalizer based on approximate calculation. Background Art

[0002] In long-haul optical fiber communication, coherent optical communication has taken the leading position. It has the trend of replacing impulse modulation direct decode (IMDD) as the next-generation digital center communication technology. Adaptive equalizers, such as the constant modulus algorithm (CMA) and the multi-modules algorithm (MMA), are key components in the digital signal processing module of coherent receivers and are used to compensate for the impairments caused by the transmission of optical fiber links. However, due to its high computational complexity, large footprint, and high power consumption, this module is greatly restricted in its application in short-distance communication, and thus has become a recent research hotspot.

[0003] In recent years, reducing the computational complexity from the equalizer structure has been the most popular method. In [1] and [2], Zhang et al. and Cheng et al. verified the N-1 and 1-N equalizer structures. In [3], Matsuda et al. found that the downsampling consumes less computational amount and has less accuracy loss by comparing the order of downsampling. In [4], Zhang et al. found that there are different effects between the real part and the imaginary part parameters of the filter, and proposed a filter with unequal parameters to further reduce multiplications. However, these studies mainly focus on the system and do not give specific hardware implementations.

[0004] The research focus of the adaptive equalizer hardware lies in the update of filter parameters. In [5], Zhou et al. proposed a grouping method to calculate the loss of the equalizer. In [6], a sign-sign structure was proposed to reduce the computational complexity. In [7], an error accumulation module that accumulates odd (or even) signals was proposed to handle the parallel filter structure. However, these works used full-precision multiplication in the calculation, which incurred huge hardware overhead and left ample room for optimization. Fixed-point multiplication is the mainstream in the design of adaptive equalizers. Experiments show that 5-bit data and 11-bit parameters can already meet the bit error rate requirements of QPSK. This means that full-precision fixed-point multipliers are a waste of area and power. Therefore, approximate calculation methods that reduce the multiplication complexity by truncating partial products have great potential in the application of equalizers. In [8] and [9], Liu et al. and Jiang et al. divided the partial product summation into error accumulation and "OR" operations, avoiding the use of half adders and full adders. In

[10] and

[11] , Zhang et al. and He et al. used booth encoders to implement multipliers, dividing the partial product into three parts, each part making a different contribution to the final result. Summary of the Invention

[0005] The object of the present invention is to provide a polarization mode dispersion adaptive equalizer based on approximate calculation applied to a coherent optical communication system, so as to greatly reduce the area and power consumption of the equalizer with very little performance loss. Applied to a coherent optical communication system

[0006] The adaptive equalizer designed based on approximate calculation in the present invention is a 16-way parallel equalizer, and each way adopts a 9-1 equalizer structure; in this parallel equalizer, a parameter sharing scheme is adopted, and all multipliers are implemented using approximate multipliers;

[0007] The 9-1 equalizer of the equalizer proposed in the present invention has a structure as Figure 1 shown. This structure is divided into two levels: the front stage of the equalizer consists of a 9-Taps 2×2 MIMO filter, which is used to compensate for the inter-symbol interference (ISI: InterSymbol Interference) within the polarization state; the rear stage of the equalizer consists of a 1-Taps 2×2 MIMO filter, which is used to compensate for the data between the two polarization states. For the general N-1 equalizer front stage, the processing process is as follows:

[0008] X mid,r = X in,r × H X,rr + X in,i × H X,ri , #(1)

[0009] X mid,i = Xin,r ×H X,ir +X in,i ×H X,ii ,#(2)

[0010] The processing of only X requires 4 groups of parameters: H X,rr 、H X,ri 、H X,ir 、H X,ii ;

[0011] According to the parameter sharing scheme designed by the present invention, on the basis of the original equalizer, the parameters of the input data and its orthogonal data use the same parameters and participate in the parameter update together, which can ensure the performance of the equalizer while greatly reducing the number of parameters. The processing process of the parameter sharing scheme is as follows:

[0012] X mid,r = X in,r ×H X,r +X in,i ×H X,i ,#(3)

[0013] X mid,i = X in,r ×H X,i +X in,i ×H X,i ,#(4)

[0014] Only two groups of parameters are needed: H X,r 、H X,i Because the number of parameters used in the front stage of the entire equalizer is much larger than that in the rear stage. Similarly, the processing of the input Y will also reduce the number of parameters. Therefore, this scheme can greatly reduce the parameter scale.

[0015] The adaptive equalizer has a large number of multipliers, and all of them need to be implemented using full-precision fixed-point multipliers, which will result in a large hardware overhead for this circuit. Therefore, the present invention proposes an approximate multiplier to solve this problem. When studying the multiplication distribution of each module in the adaptive equalizer, it is found that the multiplication of the equalizer is mainly used in the following three processes: (1) forward equalization, (2) modulus calculation, and (3) parameter update. For the adaptive equalizer designed by the present invention, the number of multipliers used in each process and the bit widths of their inputs and outputs are statistically shown in Table 1. The number of multipliers used in the forward equalization process is much larger than the other two processes. Therefore, the present invention designs a 13×7 (i.e., the multiplicand is 13 bits and the multiplier is 7 bits) approximate multiplier for area optimization of the forward equalization module.

[0016] For signed number multiplication, assuming that the multiplier A is an n-bit data and the multiplicand B is an m-bit data, then:

[0017]

[0018]

[0019] The result of multiplying A and B is:

[0020]

[0021] The approximate multiplier designed in the present invention divides the partial products (obtained according to Equation (7)) into four parts according to the quantization bits of the input data of the multiplier: (1) exact column, (2) retention column (RC), (3) approximate column (AC), (4) truncation column (TC) (as Figure 2 shown). The exact column is used to ensure a certain accuracy of the calculation result. The retention column is used to balance the accuracy of the calculation result and the hardware consumption. The approximate column performs an "OR" operation on all the data and retains the result. The approximate column increases the accuracy of the calculation result with almost unchanged hardware consumption. The truncation column is completely discarded. The truncation column can greatly reduce the hardware overhead with little reduction in accuracy; the retained data is compressed using 31 full adders and 4 half adders into two columns of partial products, and finally the final product result is obtained using an OR gate and a carry look-ahead adder.

[0022] Assume that the probabilities of 0 and 1 appearing in an integer are both 0.5. Then the probability of 1 appearing in the partial products is 0.25. As shown in Table 1, the multiplicand and the multiplier are 13 bits and 7 bits respectively. It can be seen from Equation (8) that the expected value of a certain column in the partial products is 2.25, which is close to the expected value obtained by performing an "OR" operation on all the current numbers. Therefore, the approximate column can be approximated as a 7-input OR gate. Since Figure 2 the influence of the expected value of the column on the right side of the approximate column on the result is very small, so there is only 1 column in the approximate column.

[0023]

[0024] where i represents the number of 1s in the partial product column.

[0025] Therefore, in the partial products, the exact column and the retention column are partially retained for subsequent calculations. The result after performing an "OR" operation on all the data in the approximate column is retained; the truncation column is completely discarded, and then the retained partial products are accumulated using a dadda tree (as Figure 3As shown. In the 13×7 approximate multiplier of the present invention, only 31 full adders and 4 half adders are required. Compared with the general partial product accumulation addition based on the Dadda tree, this structure reduces the number of FAs from 56 to 31. In addition, at the last stage of the Dadda tree, the approximate multiplier of the present invention uses a 4-input OR gate to calculate the carry input to the carry propagate adder (CPA).

[0026] Adopt the normalized mean error expressed by Equation (9) The maximum absolute error |ε| max and the mean absolute error to evaluate the performance of the approximate multiplier of the present invention:

[0027]

[0028] where P A is the result of the approximate multiplier, P T is the standard result, N is the number, and n is the truncated number of bits. As shown in Table 2, the results show that the performance of retaining 2 columns and 3 columns is similar, and both are better than 1 column.

[0029] Features of the present invention

[0030] The adaptive equalizer based on approximate calculation designed in the present invention combines the parameter sharing scheme with the general N-1 equalizer to design a 16-way parallel adaptive equalizer. The designed parameter sharing scheme reduces the scale of parameters (reducing the parameters of the equalizer by 38.9%) and the computational complexity of the present invention compared with the general equalizer.

[0031] In the present invention, the forward equalization calculation of the equalizer uses a 13×7 approximate multiplier, which can greatly reduce the hardware overhead with little performance loss. Therefore, the adaptive equalizer based on approximate calculation proposed in the present invention greatly reduces the area and power consumption compared with the ordinary fixed-point calculation-based adaptive equalizer. This multiplier reduces the number of full adders by about 44.6% while ensuring that the loss of the mean absolute error is only 0.31. Compared with the fixed-point structure, the area of the approximate base equalizer is increased by 27.86%, and the power efficiency is increased by 37.88%. Brief description of the drawings

[0032] Figure 1 is the proposed adaptive equalizer structure based on approximate calculation.

[0033] Figure 2 is the block diagram of the approximate multiplier proposed in the present invention.

[0034] Figure 3This is the partial product compression process of the approximate multiplier proposed by the present invention.

[0035] Figure 4 This is the performance comparison between the adaptive equalizer proposed by the present invention and several other equalizers.

[0036] Figure 5 These are the results of CMA and DSP when OSNR = 17dB. (a)(d) are the inputs of CMA, (b)(e) are the outputs of CMA, and (c)(f) are the outputs of DSP. Detailed implementation manners

[0037] The present invention will be further described in detail below with reference to the accompanying drawings.

[0038] As Figure 1 shown, the input data of the equalizer is I X , Q X , I Y , Q Y . According to the shared parameter scheme designed by the present invention, the calculation is performed according to Equation (10 - 13) when using a 9 - Taps 2×2 MIMO filter in the front stage of the equalizer.

[0039] X mid,r = X in,r ×H X,r + X in,i ×H X,i , #(10)

[0040] X mid,i = X in,r ×H X,i + X in,i ×H X,i , #(11)

[0041] Y mid,r = Y in,r ×H Y,r + Y in,i ×H Y,i , #(12)

[0042] Y mid,i = Y in,r ×H Y,i + Y in,i ×H Y,i , #(13)

[0043] In the 1 - Taps 4×4 MIMO in the back stage of the equalizer, the inputs are the outputs X mid,r , X mid,i , Y mid,r , Y mid,i of the front stage, and the calculation is performed according to Equation (14):

[0044]

[0045] Among them, represents the final result. All Hs before and after the adaptive equalizer represent parameters, and the parameters are updated according to Equation (15):

[0046]

[0047] Among them, r represents the average energy of the receiver, usually a constant value. μ represents the adaptive coefficient that controls the convergence of the update process. represents the result, and x represents the input. The update of the parameter related to the input y is similar.

[0048] According to the above analysis, the multiplier is used for three purposes in total, namely for forward equalization in the front and rear stages of the equalizer, for modulo calculation and parameter update during parameter update. The different purposes are counted separately as shown in Table 1. In the present invention, the 13×7 multiplier (the multiplier has a bit width of 13 bits and the multiplicand has a bit width of 7 bits) used in the forward equalization operation with the largest multiplier ratio is replaced by an approximate multiplier.

[0049] The following details the specific operations of the approximate multiplier used in the present invention, as Figure 2 shown. First, partial products are obtained according to the signed number multiplication rule; then the partial products are divided into four parts: the exact column, the retention column, the approximation column, and the truncation column. The carry obtained after performing an "OR" operation on the data in the exact column, the retention column, and all approximation columns is used for subsequent calculations; then the retained partial products are compressed using a full adder and a half adder to obtain two columns of data with a length of 10 bits; finally, the last two bits of the two columns of data are "OR"ed using a 4-input OR gate as the carry, and the remaining 8-bit data is used as the input, and a multiplication result is obtained by calculating with an 8-bit carry-lookahead adder.

[0050] In the experiment, the adaptive equalizer proposed in the present invention was verified under the condition that the optical signal-to-noise ratio (OSNR: optical signal noise rate) ranges from 13 to 18 Db. In the case of 80 km single-mode fiber transmission, 64 Kb of 112 Gb / s DQPSK data is generated for each OSNR. The test platform uses a coherent optical system built with floating-point calculations using other modules. These data and the test platform are used to compare the performance of the adaptive equalizer proposed in the present invention and several other adaptive equalizers. The results are as Figure 4 shown. It can be seen that the adaptive equalizer based on the N-1 equalizer structure can bring performance improvement compared with the traditional adaptive equalizer, but quantization will cause its performance to decline, and the introduction of approximate calculation will cause the performance to decline further. In addition, it can be seen that the performance difference is not significant when the retention column takes 2 and when the retention column takes 3. Figure 5The results of the two coherent optical input signals processed by CMA and DSP when OSNR = 17 dB are given.

[0051] Table 3 lists the hardware efficiencies of the adaptive equalizers based on approximate calculation when retaining columns 2 and 3 proposed by the present invention, and compares them with general adaptive equalizers based on fixed-point calculation. All equalizers are synthesized using the 28nm process library with Synopsys Design Compiler. All equalizers operate at a frequency of 1.78 GHz and a throughput of 114 Gbps. The results show that compared with the adaptive equalizer based on fixed-point calculation, the adaptive equalizer based on approximate calculation with 2 columns retained proposed by the present invention saves 27.86% of the area and 37.82% of the power. Measured by the power consumption per transmitted bit for power efficiency, the energy efficiency is increased by approximately 37.88%; the adaptive equalizer based on approximate calculation with 3 columns retained saves 21.11% of the area and 34.06% of the power.

[0052] Table 1, Multiplier Type Statistics

[0053] Forward Equalization Modulus Calculation Parameter Update Multiplicand 7(2,5)* 8(3,5)* 8(3，5)* Multiplier 13(2,11)* 8(3,5)* 13(2,11)* Product 7(2,5)* 8(3,5)* 6(4,2)* Quantity 704 20 132

[0054] * Data bit width (number of integer bits, number of fractional bits)

[0055] Table 2, Multiplier Performance Results

[0056] Number of Reserved Columns 1 2 3 Normalized Mean Error 0.3993 0.0137 0.0277 Maximum Absolute Error 2.9692 1.7192 1.2193 Mean Absolute Error 0.4983 0.3117 0.2793 BER(15dB) 0.0093 0.0014 0.0013

[0057] Table 3, Comparison of Synthesis Results of the Adaptive Equalizer Proposed by the Present Invention and Other Equalizers

[0058] Multiplier Structure Fixed-Point Number Reserve 2 Columns Reserve 3 Columns Frequency (MHz) 1785.7 1785.7 1785.7 <![CDATA[Area (mm 2 )]]> 505.43 364.62 398.74 Power Consumption (mW) 744.69 436.05 491.07 Throughput (Gb / s) 114.28 114.28 114.28 Energy Efficiency (J / bit) 6.52 4.05 4.30 。

[0059] References

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[0069]

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[0070]

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Claims

1. An adaptive equalizer based on approximate computing, characterized in that, It is a 16-way parallel equalizer, and each path adopts a 9-1 equalizer structure; in this parallel equalizer, a parameter sharing scheme is adopted, and all multipliers are implemented by approximate multipliers; For the 9-1 equalizer of the equalizer, its structure is divided into two levels: the front stage of the equalizer is composed of a 9-Taps 2×2 MIMO filter, which is used to compensate for the inter-symbol interference within the polarization state; the rear stage of the equalizer is composed of a 1-Taps 2×2 MIMO filter, which is used to compensate for the data between two polarization states; for the front stage of the N-1 equalizer, the processing process is as follows: X mid，r = X in，r × H X，rr + X in，i × H X，ri , #(1) X mid，i = X in，r × H X，ir + X in，i × H X，ii , #(2) The parameter sharing scheme mentioned above is based on the original equalizer, making the parameters of the input data and its orthogonal data use the same parameters and participate in the parameter update together, which is used to ensure the performance of the equalizer while greatly reducing the number of parameters; The processing process of the parameter sharing scheme mentioned above is as follows: X mid，r = X in，r × H X，r + X in，i × H X，i , #(3) X mid，i = X in，r × H X，i + X in，i × H X，i , #(4) Only two sets of parameters are required: H X，r , H X，i ; For the approximate multiplier mentioned above, according to the quantization bits of the multiplier input data, the partial products are divided into four parts: the exact column, the reserved column, the approximate column, and the truncated column; the exact column is used to ensure a certain accuracy of the calculation result, the reserved column is used to balance the accuracy of the calculation result and the hardware consumption, the approximate column performs an "OR" operation on all the data and then retains the result, the approximate column increases the accuracy of the calculation result with almost unchanged hardware consumption, and the truncated column is completely discarded; the retained data is compressed into two columns of partial products by using 31 full adders and 4 half adders, and finally the final product result is obtained by using an OR gate and a carry look-ahead adder.

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