A process method for improving mtp programming capability

Abstract

The application provides a process method for improving MTP programming capability, which comprises the following steps: providing a substrate with MTP unit area and NMOS area, forming a gate on the surface of the substrate; covering the NMOS area with a first mask layer, performing ion implantation on the MTP unit area to form MTP implantation area and MTP source-drain area, and removing the first mask layer; forming a side wall on both sides of the gate; covering the MTP unit area with a second mask layer, performing ion implantation on the NMOS area to form LDD oblique implantation area and NMOS source-drain area. The process method of the application only needs two times of mask and photoetching, so that the process flow is relatively simplified, the cost is reduced, and the MTP unit area is protected by the mask during LDD oblique implantation, so that the influence of LDD oblique implantation on the programming capability of the MTP unit is avoided, and the programming capability of the MTP unit is ensured at a high level.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, in particular to a process method for improving MTP programming capacity. BACKGROUND

[0002] Compared with one time program memory (OTP), multi-time program memory (MTP) has the advantages of multiple data storage, reading, erasing and other actions, and the stored data will not disappear after power off. It has gradually become a widely used memory device in the fields of personal computers, electronic devices, mobile storage and other fields.

[0003] In the prior art, the conventional process for making MTP is as follows: 1) providing a substrate with MTP cell area and NMOS area, forming a gate on the substrate; 2) covering the MTP cell area with a mask, only injecting NMOS to form NLDD (N-type lightly doped drain region); 3) covering the NMOS area with a mask, only injecting the MTP cell area to form the MTP injection area; 4) making sidewalls on both sides of the gate; 5) simultaneously injecting the NMOS area and the MTP cell area to form the source-drain injection area.

[0004] Considering the complexity of the above method, the technicians simplified the process, and the reduced process is as follows: 1) providing a substrate with MTP cell area and NMOS area, forming a gate on the substrate; 2) covering the NMOS area with a mask, only injecting the MTP cell area to form the MTP injection area; 3) making sidewalls on both sides of the gate; 4) simultaneously injecting the NMOS area and the MTP cell area to form the LDD oblique injection area and the source-drain injection area. This method is simpler than the conventional process, but because of the LDD oblique injection in step 4), the MTP cell hot carrier effect is weakened, so the programming capacity is poor, about 10mS slower, and it cannot be adjusted and compensated by injecting the MTP cell area.

[0005] To solve the above problems, the general solution is: 1) providing a substrate with MTP cell area and NMOS area, forming a gate on the substrate; 2) covering the NMOS area with a mask, only implanting the MTP cell area to form an MTP implantation area; 3) making a sidewall on both sides of the gate; 4) covering the MTP cell area with a mask, only implanting the NMOS to form an LDD oblique implantation area and a source-drain implantation area; 5) covering the NMOS area with a mask, only implanting the MTP cell area to form the source-drain implantation area of the area. It can be seen that although this method can solve the problems of the reduction process, this solution performs multiple photolithography, which increases the process cost and makes the reduction process meaningless.

[0006] Therefore, it is a subject for those skilled in the art to provide a new process method for improving the programming capability of MTP. SUMMARY

[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide a process method for improving the programming capability of MTP, which solves the problems of poor programming capability and high cost of MTP in the prior art.

[0008] To achieve the above-mentioned purposes and other related purposes, the present application provides a process method for improving the programming capability of MTP, which at least comprises:

[0009] 1) providing a substrate with MTP cell area and NMOS area, forming a gate on the surface of the substrate;

[0010] 2) covering the NMOS area with a first mask layer, implanting ions to the MTP cell area to form an MTP implantation area and an MTP source-drain area, and removing the first mask layer;

[0011] 3) forming a sidewall on both sides of the gate;

[0012] 4) covering the MTP cell area with a second mask layer, implanting ions to the NMOS area to form an LDD oblique implantation area and an NMOS source-drain area.

[0013] Preferably, in the step 2), a full-coverage first mask layer is first formed on the surface of the structure obtained in the step 1), and then the first mask layer is patterned by using photolithography and development technology, so that the first mask layer only covers the NMOS area and exposes the MTP cell area for ion implantation.

[0014] Preferably, in the step 4), a second mask layer is formed on the structure surface obtained in the step 3) to form full coverage, then the second mask layer is patterned by using photoetching and developing technology, so that the second mask layer only covers the MTP cell region and exposes the NMOS region for ion implantation on the NMOS region.

[0015] Preferably, the first mask layer and the second mask layer comprise a photoresist layer.

[0016] Preferably, the MTP cell region and the NMOS region are isolated by a shallow trench isolation region.

[0017] Preferably, the substrate further has a PMOS region, in the step 2), the first mask layer covers the NMOS region and covers the PMOS region at the same time; in the step 4), the second mask layer covers the MTP cell region and covers the PMOS region at the same time.

[0018] Preferably, in the step 4), a part of the LDD oblique implantation region extends into the substrate under the side wall.

[0019] As described above, the process method for improving the programming ability of MTP of the present application comprises: 1) providing a substrate with a MTP cell region and a NMOS region, and forming a gate on the surface of the substrate; 2) covering the NMOS region by using a first mask layer, and performing ion implantation on the MTP cell region to form a MTP implantation region and a MTP source-drain region, and removing the first mask layer; 3) forming a side wall on both sides of the gate; 4) covering the MTP cell region by using a second mask layer, and performing ion implantation on the NMOS region to form an LDD oblique implantation region and a NMOS source-drain region. The process method of the present application only uses two times of mask and photoetching, so that the process flow is relatively simplified and the cost is reduced, and the MTP cell region is protected by mask during LDD oblique implantation, so that the influence of LDD oblique implantation on the programming ability of MTP cell is avoided, and the programming ability of MTP cell is ensured at a high level. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 It is a flowchart of the process method for improving the programming ability of MTP of the present application.

[0021] Figures 2 to 6 It is a structural schematic view of each step of the process method for improving the programming ability of MTP of the present application.

[0022] ELEMENT NUMBER EXPLANATION

[0023] 1 substrate

[0024] 2 gate

[0025] 3 Shallow Ditch Isolation Zone

[0026] 4 Oxide layer

[0027] 5 First mask layer

[0028] 6 MTP Injection Area

[0029] 7 MTP source / drain region

[0030] 8 side walls

[0031] 9 Second mask layer

[0032] 10 LDD angled injection area

[0033] 11 NMOS source and drain regions Detailed Implementation

[0034] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] Please refer to the accompanying drawings. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0036] like Figure 1 As shown, this embodiment provides a process method for improving MTP programming capabilities, the process method including the following steps:

[0037] like Figure 1 and Figure 2 As shown, step S1 is first performed, providing a substrate 1 having an MTP cell region and an NMOS region, and forming a gate 2 on the surface of the substrate 1.

[0038] As an example, the substrate 1 can be a silicon substrate. Of course, in other embodiments, the substrate 1 can also be a silicon carbide substrate, a germanium silicon substrate, etc., and there is no limitation here.

[0039] As an example, the MTP cell region and the NMOS region are separated by a shallow trench isolation (STI) 3. The gate 2 is formed in both the MTP cell region and the NMOS region, and of course, the gate 2 can also be formed in other positions according to the needs of the device.

[0040] In addition, an oxide layer 4 needs to be formed on the surface of the substrate 1 before the gate 2 is formed. Specifically, the oxide layer 4 can be formed by a thermal oxidation method or a plasma enhanced chemical vapor deposition method, but is not limited thereto.

[0041] As shown in Figure 1 and Figure 3 , then step S2 is performed, the first mask layer 5 is used to cover the NMOS region, and ion implantation is performed on the MTP cell region to form the MTP implant region 6 and the MTP source / drain region 7, and then as shown in Figure 4 , the first mask layer 5 is removed.

[0042] As an example, the first mask layer 5 is composed of a material with photosensitive properties, for example, it can be a photoresist layer.

[0043] As an example, a full-coverage first mask layer 5 is first formed on the surface of the structure obtained in step S1, and then the first mask layer 5 is patterned using photolithography and development techniques, so that the first mask layer 5 only covers the NMOS region, and the MTP cell region is exposed for ion implantation.

[0044] By means of the first mask layer 5, an opening is formed only above the MTP cell region, so that ion implantation is first performed to form the MTP implant region 6 in the shallow surface layer of the substrate 1, and then ion implantation is performed to form the MTP source / drain region 7. The type of ion selected for ion implantation is determined by the specific device and is not limited herein.

[0045] As can be seen, by using the first mask layer 5, only one photolithography process is required to complete the two implantations to form the MTP implant region and the MTP source / drain region, respectively. After the implantation is completed, the first mask layer 5 is removed.

[0046] As an example, the substrate 1 also has a PMOS region, and in this step, the first mask layer 5 is used to cover the NMOS region while covering the PMOS region, so that ion implantation is only performed on the MTP cell region.

[0047] As shown in Figure 1 and Figure 5 , then step S3 is performed to form a side wall 8 on both sides of the gate 2.

[0048] As an example, the material of the side wall 8 can be silicon dioxide or silicon nitride or a stack of silicon dioxide and silicon nitride, without being limited thereto.

[0049] As shown in Figure 1 and Figure 6 Finally, step S4 is performed to cover the MTP cell region with the second mask layer 9 and perform ion implantation on the NMOS region to form the LDD implantation region 10 and the NMOS source / drain region 11.

[0050] As an example, the second mask layer 9 is made of a material with photosensitive properties, for example, a photoresist layer.

[0051] As an example, in this step, a full-coverage second mask layer 9 is first formed on the structure surface obtained in step S3, and then the second mask layer 9 is patterned using photolithography and development techniques to cover only the MTP cell region and expose the NMOS region for ion implantation.

[0052] As an example, the substrate 1 also has a PMOS region, and in this step, the second mask layer 9 is used to cover the MTP cell region and the PMOS region at the same time so as to perform ion implantation only on the NMOS region.

[0053] Since the LDD (lightly doped drain) is formed after the side wall 8, it is necessary to use an oblique implantation method to form the region below the side wall 8. As an example, the LDD implantation region 10 extends partially into the substrate 1 below the side wall 8.

[0054] Therefore, by using the second mask layer 9, only one photolithography process is needed to complete two implantations to form the LDD implantation region and the NMOS source / drain region, respectively. After the implantation is completed, the second mask layer 9 is removed.

[0055] The present application provides a process method for improving the programming ability of MTP, comprising: 1) providing a substrate 1 with MTP cell area and NMOS area, forming a gate 2 on the surface of the substrate 1; 2) covering the NMOS area with a first mask layer 5, ion implantation is performed on the MTP cell area to form MTP implantation area 6 and MTP source-drain area 7, and the first mask layer 5 is removed; 3) forming a sidewall 8 on both sides of the gate 2; 4) covering the MTP cell area with a second mask layer 9, ion implantation is performed on the NMOS area to form LDD oblique injection area 10 and NMOS source-drain area 11. The process method of the present application only uses two masks and performs two photoetchings, so that the process flow is relatively simplified, the cost is reduced, and the MTP cell area is protected during LDD oblique injection, avoiding the influence of LDD oblique injection on the programming ability of MTP cell, and ensuring the programming ability of MTP cell at a high level.

[0056] Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0057] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A process method for improving MTP programming capability, characterized by, The process method comprises at least: 1) providing a substrate with MTP cell region and NMOS region, forming gate on the surface of the substrate; 2) covering the NMOS region with a first mask layer, ion implanting the MTP cell region to form MTP implant region and MTP source-drain region, and removing the first mask layer; 3) forming side wall on both sides of the gate; 4) covering the MTP cell region with a second mask layer, ion implanting the NMOS region to form LDD oblique implant region and NMOS source-drain region; a part of the LDD oblique implant region extends into the substrate under the side wall.

2. The process method of improving MTP programming capability according to claim 1, wherein: In the step 2), a full-coverage first mask layer is formed on the surface of the structure obtained in the step 1), then the first mask layer is patterned by using photoetching and developing technology, so that the first mask layer only covers the NMOS region, and the MTP cell region is exposed for ion implantation.

3. The process method of improving MTP programming capability of claim 1, wherein: In the step 4), a full-coverage second mask layer is formed on the surface of the structure obtained in the step 3), then the second mask layer is patterned by using photoetching and developing technology, so that the second mask layer only covers the MTP cell region, and the NMOS region is exposed for ion implantation.

4. The process for improving MTP programming capability according to any one of claims 1 to 3, characterized in that: The first mask layer and the second mask layer comprise photoresist layer.

5. The process method of improving MTP programming capability of claim 1, wherein: The MTP cell region and the NMOS region are isolated by shallow trench isolation region.

6. The process method of improving MTP programming capability of claim 1, wherein: The substrate also has PMOS region, in the step 2), the first mask layer covers the NMOS region, and the PMOS region is also covered; in the step 4), the second mask layer covers the MTP cell region, and the PMOS region is also covered.

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