Duty cycle adjustment circuit

Abstract

The present application discloses a duty cycle adjustment circuit, comprising: first and second clock transmission channels, each including several stages of inverters, and the first-stage inverters each receive a clock signal; a current adjustment circuit, which includes a first adjustment branch and a second adjustment branch, each including: first to fourth PMOS transistors, first to third NMOS transistors, the sources of the first to fourth PMOS transistors are all connected to the power supply terminal, the drains of the second PMOS transistor, the first NMOS transistor, and the gates of the first to third NMOS transistors are all connected, and the sources of the first to third NMOS transistors are all connected to the ground terminal. This duty cycle adjustment circuit has advantages such as a relatively simple circuit structure, strong duty cycle adjustment ability, and ultra-low power consumption. It has advantages such as a relatively simple circuit structure, strong duty cycle adjustment ability, and ultra-low power consumption.

Description

Technical Field

[0001] The present invention generally relates to the field of integrated circuit technology, and particularly relates to a clock duty cycle adjustment circuit for a digital-to-analog converter. Background Art

[0002] Currently, there are clock duty cycle adjustment circuits in pure analog mode and pure digital mode. The digital-mode duty cycle adjustment circuit is relatively simple and stable, but is mainly applied to relatively low-speed fields.

[0003] The analog-mode duty cycle adjustment circuit is generally based on a pseudo-inverter adjustment stage and can be applied to high-speed fields. However, its disadvantages are high power consumption, low linearity, narrow adjustment range, and large influence of PVT on accuracy. In the field of high-speed communication, the demand for a clock duty cycle adjustment circuit with low power consumption and strong adjustment ability is increasing. Summary of the Invention

[0004] The purpose of the present invention is to provide a duty cycle adjustment circuit, which has the advantages of relatively simple circuit structure, strong duty cycle adjustment ability, and ultra-low power consumption.

[0005] The present application discloses a duty cycle adjustment circuit, including:

[0006] A first clock transmission channel, which includes several stages of inverters, and the first-stage inverter receives a clock signal;

[0007] A second clock transmission channel, which includes several stages of inverters, and the first-stage inverter receives another clock signal; and

[0008] A current regulation circuit, which includes a first regulation branch and a second regulation branch. Each of the first and second regulation branches includes: a first to fourth PMOS transistor, and a first to third NMOS transistor. Among them, the sources of the first to fourth PMOS transistors are all connected to the power supply terminal, the drain of the second PMOS transistor, the drain of the first NMOS transistor, and the gates of the first to third NMOS transistors are all connected together, and the sources of the first to third NMOS transistors are all connected to the ground terminal; Among them, in the first regulation branch, the drain of the first PMOS transistor and the gates of the first to fourth PMOS transistors are all connected to the first output terminal of the digital-to-analog converter, the drain of the second NMOS transistor is connected to the input terminal of the second inverter of the first clock transmission channel, the drain of the third NMOS transistor is connected to the input terminal of the third inverter of the second clock transmission channel, the drain of the third PMOS transistor is connected to the input terminal of the second inverter of the second clock transmission channel, and the drain of the fourth PMOS transistor is connected to the input terminal of the third inverter of the first clock transmission channel; Among them, in the second regulation branch, the drain of the first PMOS transistor and the gates of the first to fourth PMOS transistors are all connected to the second output terminal of the digital-to-analog converter, the drain of the second NMOS transistor is connected to the input terminal of the second inverter of the second clock transmission channel, the drain of the third NMOS transistor is connected to the input terminal of the third inverter of the first clock transmission channel, the drain of the third PMOS transistor is connected to the input terminal of the second inverter of the first clock transmission channel, and the drain of the fourth PMOS transistor is connected to the input terminal of the third inverter of the second clock transmission channel.

[0009] In a preferred example, the digital-to-analog converter includes: a fourth to sixteenth NMOS transistor, a fifth PMOS transistor, a binary-to-temperature encoding circuit, and a first to fifth group of NOR gates;

[0010] The drain of the fourth NMOS transistor is connected to the gates of the fourth to ninth NMOS transistors and is connected to a bias input signal. The sources of the fourth to ninth NMOS transistors are connected to the ground terminal. The drain of the fifth NMOS transistor is connected to the sources of the tenth and eleventh NMOS transistors. The drain of the sixth NMOS transistor is connected to the sources of the twelfth and thirteenth NMOS transistors. The source of the seventh NMOS transistor is connected to the sources of the fourteenth to sixteenth NMOS transistors. The drains of the ninth, eleventh, thirteenth, and fifteenth NMOS transistors are connected together as the first output terminal of the digital-to-analog converter. The drains of the eighth, tenth, twelfth, and fourteenth NMOS transistors are connected together as the second output terminal of the digital-to-analog converter. The drain of the sixteenth NMOS transistor is connected to the drain and gate of the fifth PMOS transistor. The source of the fifth PMOS transistor is connected to the power supply terminal; wherein, each of the fifth, tenth, and eleventh NMOS transistors includes a group of NMOS transistors connected in parallel; wherein, each of the seventh, fourteenth, fifteenth, and sixteenth NMOS transistors includes a group of NMOS transistors connected in parallel;

[0011] The binary-to-temperature encoding circuit outputs a pair of complementary temperature encodings and is respectively connected to one input terminal of the first group and the second group of NOR gates. The output terminal of the first group of NOR gates is connected to the gates of the respective NMOS transistors in the eleventh NMOS transistor. The output terminal of the second group of NOR gates is connected to the gates of the respective NMOS transistors in the tenth NMOS transistor;

[0012] The output terminal of the third group of NOR gates is respectively connected to the gate of the twelfth NMOS transistor, the gates of the respective NMOS transistors in the fourteenth NMOS transistor, and one input terminal of the fifth group of NOR gates. The output terminal of the fourth group of NOR gates is respectively connected to the gate of the thirteenth NMOS transistor, the gates of the respective NMOS transistors in the fifteenth NMOS transistor, and the other input terminal of the fifth group of NOR gates. The output terminal of the fifth group of NOR gates is respectively connected to the gates of the respective NMOS transistors in the sixteenth NMOS transistor.

[0013] In a preferred example, the digital-to-analog converter has an 8-bit data signal D<8:1>, and the binary-to-thermometer code circuit receives the data signal D<7:4> and converts it into a pair of 15-bit complementary thermometer codes T<15:1> and TB<15:1>. Another input terminal of the first group of NOR gates receives the data signal DB<8>, another input terminal of the second group of NOR gates receives the data signal D<8>, one input terminal of the third group of NOR gates receives the data signal D<8>, and another input terminal receives the data signal D<3:1>. One input terminal of the fourth group of NOR gates receives the data signal DB<8>, and another input terminal receives the data signal DB<3:1>.

[0014] In a preferred example, one input terminal of the first group of NOR gates receives the data signal TB<15:1>, and another input terminal receives the data signal DB<8>, and outputs the data signal PTD<15:1>. One input terminal of the second group of NOR gates receives the data signal T<15:1>, and another input terminal receives the data signal D<8>, and outputs the data signal NTD<15:1>. One input terminal of the third group of NOR gates receives the data signal D<8>, and another input terminal receives the data signal D<3:1>, and outputs the data signal ND<3:1>. One input terminal of the fourth group of NOR gates receives the data signal DB<8>, and another input terminal receives the data signal DB<3:1>, and outputs the data signal PD<3:1>. Two input terminals of the fifth group of NOR gates respectively receive the data signals ND<2:1> and PD<2:1>, and output the data signal CD<2:1>. The gates of the NMOS transistors in the tenth NMOS transistor are controlled by the data signal NTD<15:1>. The gates of the NMOS transistors in the eleventh NMOS transistor are controlled by the data signal PTD<15:1>. The gate of the twelfth NMOS transistor is controlled by the data signal ND<3>. The gate of the thirteenth NMOS transistor is controlled by the data signal PD<3>. The gates of the NMOS transistors in the fourteenth NMOS transistor are controlled by the data signal ND<2:1>. The gates of the NMOS transistors in the fifteenth NMOS transistor are controlled by the data signal PD<2:1>. The gates of the NMOS transistors in the sixteenth NMOS transistor are controlled by the data signal CD<2:1>.

[0015] Compared with the prior art, the present application has at least the following beneficial effects:

[0016] The duty cycle adjustment circuit has the advantages of relatively simple circuit structure. Basically, only an inverter and a digital-to-analog converter are required to effectively adjust the clock signal. It has a small area, strong duty cycle adjustment ability, ultra-low power consumption, and high linearity.

[0017] The description of this application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features (i.e., technical solutions) of this application are to be listed, the description will become overly long. To avoid this problem, each technical feature disclosed in the above-mentioned invention content of this application, each technical feature disclosed in the following embodiments and examples, and each technical feature disclosed in the drawings can be freely combined with each other to form various new technical solutions (all these technical solutions should be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, features A+B+C are disclosed, and in another example, features A+B+D+E are disclosed. Features C and D are equivalent technical means that perform the same function, and only one of them can be used technically and it is impossible to use both at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been recorded because it is technically infeasible, while the solution of A+B+C+E should be regarded as having been recorded. Brief Description of the Drawings

[0018] Figure 1 It is a schematic diagram of a clock transmission channel in an embodiment of this application.

[0019] Figure 2 It is a circuit diagram of a current regulation circuit in an embodiment of this application.

[0020] Figure 3 It is a circuit diagram of a digital-to-analog converter in an embodiment of this application. Detailed Description of the Embodiments

[0021] In the following description, many technical details are presented to enable the reader to better understand this application. However, those of ordinary skill in the art can understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can still be implemented.

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be further described in detail below with reference to the drawings.

[0023] This application discloses a duty cycle regulation circuit, including: a first clock transmission channel, a second clock transmission channel, a current regulation circuit, and a digital-to-analog converter. Figure 1The schematic diagram of a clock transmission channel in an embodiment is shown. Taking two clock transmission channels as an example for illustration, the first clock transmission channel includes several stages of inverters. For example, it includes four stages of inverters INV1, INV2, INV3, and INV4. The first-stage inverter INV1 receives a clock signal CKINP, and the fourth-stage inverter INV4 outputs a clock signal CKOUTP. The second clock transmission channel includes several stages of inverters. For example, it includes four stages of inverters INV1’, INV2’, INV3’, and INV4’. The first-stage inverter INV1’ receives another clock signal CKINN, and the fourth-stage inverter INV4’ outputs a clock signal CKOUTN.

[0024] Figure 2 The circuit diagram of a current regulation circuit in an embodiment is shown. The current regulation circuit includes a first regulation branch and a second regulation branch. Each of the first regulation branch and the second regulation branch includes: a first to fourth PMOS transistor, and a first to third NMOS transistor. Specifically, the first regulation branch includes: a first to fourth PMOS transistor PM1, PM2, PM3, and PM4, and a first to third NMOS transistor NM1, NM2, and NM3. The second regulation branch includes: a first to fourth PMOS transistor BPM1, BPM2, BPM3, and BPM4, and a first to third NMOS transistor BNM1, BNM2, and BNM3.

[0025] Among them, in the first regulation branch, the sources of the first to fourth PMOS transistors PM1, PM2, PM3, and PM4 are all connected to the power supply terminal VDD. The drain of the second PMOS transistor PM2, the drain of the first NMOS transistor NM1, and the gates of the first to third NMOS transistors NM1, NM2, and NM3 are all connected. The sources of the first to third NMOS transistors NM1, NM2, and NM3 are all connected to the ground terminal. The drain of the first PMOS transistor PM1 and the gates of the first to fourth PMOS transistors PM1, PM2, PM3, and PM4 are all connected to the first output terminal OUT of the digital-to-analog converter (DAC). The drain TP1 of the second NMOS transistor NM2 is connected to the input terminal of the second-stage inverter INV2 of the first clock transmission channel. The drain TP2 of the third NMOS transistor NM3 is connected to the input terminal of the third-stage inverter INV3’ of the second clock transmission channel. The drain TN2 of the third PMOS transistor PM3 is connected to the input terminal of the second-stage inverter INV2 of the second clock transmission channel. The drain TN2 of the fourth PMOS transistor PM4 is connected to the input terminal of the third-stage inverter INV3 of the first clock transmission channel.

[0026] Among them, in the second adjustment branch, the sources of the first to fourth PMOS transistors BPM1, BPM2, BPM3, and BPM4 are all connected to the power supply terminal VDD. The drain of the second PMOS transistor BPM2, the drain of the first NMOS transistor BNM1, and the gates of the first to third NMOS transistors BNM1, BNM2, and BNM3 are all connected. The sources of the first to third NMOS transistors BNM1, BNM2, and BNM3 are all connected to the ground terminal. The drain of the first PMOS transistor BPM1 and the gates of the first to fourth PMOS transistors BPM1, BPM2, BPM3, and BPM4 are all connected to the second output terminal OUTB of the digital-to-analog converter. The drain TN1 of the second NMOS transistor BNM2 is connected to the input terminal of the second-stage inverter INV2' of the second clock transmission channel. The drain TN2 of the third NMOS transistor BNM3 is connected to the input terminal of the third-stage inverter INV3 of the first clock transmission channel. The drain TP1 of the third PMOS transistor BPM3 is connected to the input terminal of the second-stage inverter INV2 of the first clock transmission channel. The drain TP2 of the fourth PMOS transistor BPM4 is connected to the input terminal of the third-stage inverter INV3' of the second clock transmission channel.

[0027] Figure 3 The circuit diagram of a digital-to-analog converter in an embodiment of the present application is shown. The digital-to-analog converter includes: a fourth NMOS transistor NS, a fifth NMOS transistor N3C<15:1>, a sixth NMOS transistor N2C, a seventh NMOS transistor N1C<2:1>, an eighth NMOS transistor N0CB, a ninth NMOS transistor N0C, a tenth NMOS transistor N3B<15:1>, an eleventh NMOS transistor N3<15:1>, a twelfth NMOS transistor N2B, a thirteenth NMOS transistor N2, a fourteenth NMOS transistor N1B<2:1>, a fifteenth NMOS transistor N1<2:1>, a sixteenth NMOS transistor N1D<2:1>, a fifth PMOS transistor PS, a binary-to-temperature encoding circuit, a first set of NOR gates I1<15:1>, a second set of NOR gates I2<15:1>, a third set of NOR gates I3<3:1>, a fourth set of NOR gates I4<3:1>, and a fifth set of NOR gates I5<2:1>.

[0028] The drain of the fourth NMOS transistor NS is connected to the gates of the fourth NMOS transistor NS, the fifth NMOS transistor N3C<15:1>, the sixth NMOS transistor N2C, the seventh NMOS transistor N1C<2:1>, the eighth NMOS transistor N0CB, and the ninth NMOS transistor N0C and is connected to the bias input signal IB_IN. The sources of the fourth NMOS transistor NS, the fifth NMOS transistor N3C<15:1>, the sixth NMOS transistor N2C, the seventh NMOS transistor N1C<2:1>, the eighth NMOS transistor N0CB, and the ninth NMOS transistor N0C are connected to the ground terminal. The drain of the fifth NMOS transistor N3C<15:1> is connected to the sources of the tenth NMOS transistor N3B<15:1> and the eleventh NMOS transistor N3<15:1>. The drain of the sixth NMOS transistor N2C is connected to the sources of the twelfth NMOS transistor N2B and the thirteenth NMOS transistor N2. The source of the seventh NMOS transistor N1C<2:1> is connected to the sources of the fourteenth NMOS transistor N1B<2:1>, the fifteenth NMOS transistor N1<2:1>, and the sixteenth NMOS transistor N1D<2:1>. The drains of the ninth NMOS transistor N0C, the eleventh NMOS transistor N3<15:1>, the thirteenth NMOS transistor N2, and the fifteenth NMOS transistor N1<2:1> are connected together as the first output terminal OUT of the digital-to-analog converter. The drains of the eighth NMOS transistor N0CB, the tenth NMOS transistor N3B<15:1>, the twelfth NMOS transistor N2B, and the fourteenth NMOS transistor N1B<2:1> are connected together as the second output terminal OUTB of the digital-to-analog converter. The drain of the sixteenth NMOS transistor N1D<2:1> is connected to the drain and gate of the fifth PMOS transistor PS, and the source of the fifth PMOS transistor PS is connected to the power supply terminal.

[0029] It should be understood that each of the fifth NMOS transistor N3C<15:1>, the tenth NMOS transistor N3B<15:1>, and the eleventh NMOS transistor N3<15:1> includes 15 NMOS transistors. The 15 NMOS transistors are connected in parallel with each other and are respectively connected to the node net3<15:1>. For example, the drain of the NMOS transistor N3C<15>, the source of the NMOS transistor N3B<15>, and the source of the NMOS transistor N3<15> are connected to the node net3<15>. The drain of the MOS transistor N3C<14>, the source of the NMOS transistor N3B<14>, and the source of the NMOS transistor N3<14> are connected to the node net<14>, and so on. Each of the seventh NMOS transistor N1C<2:1>, the fourteenth NMOS transistor N1B<2:1>, the fifteenth NMOS transistor N1<2:1>, and the sixteenth NMOS transistor N1D<2:1> includes 2 NMOS transistors. The 2 NMOS transistors are connected in parallel with each other and are respectively connected to the node net1<2:1>. For example, the drain of the NMOS transistor N1C<2>, the source of the NMOS transistor N1B<2>, the source of the NMOS transistor N1<2>, and the source of the NMOS transistor N1D<2> are connected to the node net1<2>. The drain of the NMOS transistor N1C<1>, the source of the NMOS transistor N1B<1>, the source of the NMOS transistor N1<1>, and the source of the NMOS transistor N1D<1> are connected to the node net1<1>. The sixth NMOS transistor N2C, the twelfth NMOS transistor N2B, and the thirteenth NMOS transistor N2 are connected to the node net2.

[0030] The binary-to-temperature encoding circuit outputs a pair of complementary temperature encodings and respectively connects them to an input terminal of the first group of NOR gates and an input terminal of the second group of NOR gates. The output terminal of the first group of NOR gates is connected to the gates of the respective NMOS transistors in the eleventh NMOS transistor. The output terminal of the second group of NOR gates is connected to the gates of the respective NMOS transistors in the tenth NMOS transistor. The output terminal of the third group of NOR gates is respectively connected to the gate of the twelfth NMOS transistor N2B, the gates of the respective NMOS transistors in the fourteenth NMOS transistor, and an input terminal of the fifth group of NOR gates. The output terminal of the fourth group of NOR gates is connected to the gates of the respective NMOS transistors in the thirteenth NMOS transistor, the gate of the fifteenth NMOS transistor, and the other input terminal of the fifth NOR gate. The output terminal of the fifth group of NOR gates is connected to the gates of the respective NMOS transistors in the sixteenth NMOS transistor.

[0031] In one embodiment, the digital-to-analog converter has an 8-bit data signal D<8:1>, and the binary-to-thermometer code circuit receives the data signal D<7:4> and converts it into a pair of 15-bit complementary thermometer codes T<15:1> and TB<15:1>. One input terminal of the first group of NOR gates I1<15:1> receives the data signal TB<15:1>, and the other input terminal receives the data signal DB<8>, and outputs the data signal PTD<15:1>. One input terminal of the second group of NOR gates I2<15:1> receives the data signal T<15:1>, and the other input terminal receives the data signal D<8>, and outputs the data signal NTD<15:1>. One input terminal of the third group of NOR gates I3<3:1> receives the data signal D<8>, and the other input terminal receives the data signal D<3:1>, and outputs the data signal ND<3:1>. One input terminal of the fourth group of NOR gates I3<3:1> receives the data signal DB<8>, and the other input terminal receives the data signal DB<3:1>, and outputs the data signal PD<3:1>. The two input terminals of the fifth group of NOR gates I5<2:1> respectively receive the data signals ND<2:1> and PD<2:1>, and output the data signal CD<2:1>. The gates of the NMOS transistors in the tenth NMOS transistor N3B<15:1> are controlled by the data signal NTD<15:1>, and the gates of the NMOS transistors in the eleventh NMOS transistor N3<15:1> are controlled by the data signal PTD<15:1>. The gate of the twelfth NMOS transistor N2B is controlled by the data signal ND<3>, and the gate of the thirteenth NMOS transistor N2 is controlled by the data signal PD<3>. The gates of the NMOS transistors in the fourteenth NMOS transistor N1B<2:1> are controlled by the data signal ND<2:1>, and the gates of the NMOS transistors in the fifteenth NMOS transistor N1<2:1> are controlled by the data signal PD<2:1>. The gates of the NMOS transistors in the sixteenth NMOS transistor N1D<2:1> are controlled by the data signal CD<2:1>.

[0032] The output terminals OUTB and OUT of the digital-to-analog converter output an adjustable current. When the most significant bit of the digital-to-analog converter is at a low level, only the output terminal OUTB generates an adjustable output current. And when the seven least significant digital inputs of the digital-to-analog converter increase gradually from 0000000 to 1111111, the output current of the output terminal OUTB will decrease gradually from large to small. After the input clock signal CKINP passes through an inverter, its output signal is regulated by the rising time of the TP1 current regulation signal from the PMOS transistor BPM3. After this signal passes through the subsequent inverter, it is regulated by the falling time of the TN2 current regulating the output clock from the NMOS transistor BNM3. After the input clock signal CKINN passes through an inverter, its output signal is regulated by the falling time of the TN1 current regulation signal from the NMOS transistor BNM2. After this signal passes through the subsequent inverter, it is regulated by the rising time of the TP2 current regulating the output clock from the PMOS transistor BPM1. In this way, the duty cycles of the clocks of CKINP and CKINN are regulated to the same extent. At this time, the regulating currents TN1, TN2, TP1, and TP2 all come from the OUTB port of the digital-to-analog converter.

[0033] When the most significant bit of the digital-to-analog converter is at a high level, only the output terminal OUT generates an adjustable output current. And when the seven least significant digital inputs of the digital-to-analog converter increase gradually from 0000000 to 1111111, the output current of the output terminal OUT will increase gradually from low to high. After the input clock signal CKINP passes through an inverter, its output signal is regulated by the falling time of the TP1 current regulation signal from the NMOS transistor NM2. After this signal passes through the subsequent inverter, it is regulated by the rising time of the TN2 current regulating the output clock from the PMOS transistor PM1. After the clock signal of CKINN passes through an inverter, its output signal is regulated by the falling time of the TN1 current regulation signal from the PMOS transistor PM3. After this signal passes through the subsequent inverter, it is regulated by the falling time of the TP2 current regulating the output clock from the NMOS transistor NM3. During this stage, the regulating currents TN1, TN2, TP1, and TP2 all come from the OUT port of the digital-to-analog converter.

[0034] This duty cycle adjustment circuit has the advantages of relatively simple circuit structure, strong duty cycle adjustment ability, and ultra-low power consumption.

[0035] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one" does not exclude the existence of additional identical elements in the process, method, article or device comprising said element. In the application documents of this patent, if it is mentioned that an act is performed according to a certain element, it means that the act is performed at least according to that element, including two cases: the act is performed only according to that element, and the act is performed according to that element and other elements. Expressions such as multiple, many times, various, etc. include 2, 2 times, 2 kinds, as well as more than 2, more than 2 times, more than 2 kinds.

[0036] All documents mentioned in this specification are considered to be integrally included in the disclosure of this application so that they can be used as a basis for modification if necessary. In addition, it should be understood that the above are only preferred embodiments of this specification and are not used to limit the protection scope of this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of one or more embodiments of this specification shall be included in the protection scope of one or more embodiments of this specification.

Claims

1. A duty cycle adjustment circuit, characterized in that, Including: A first clock transmission channel, which includes several stages of inverters, and the first stage of inverter receives a clock signal; A second clock transmission channel, which includes several stages of inverters, and the first stage of inverter receives another clock signal; And A current regulation circuit, which includes a first regulation branch and a second regulation branch. Each of the first and second regulation branches includes: a first to fourth PMOS transistors, and a first to third NMOS transistors. Wherein, the sources of the first to fourth PMOS transistors are all connected to the power supply terminal, the drain of the second PMOS transistor, the drain of the first NMOS transistor, and the gates of the first to third NMOS transistors are all connected, and the sources of the first to third NMOS transistors are all connected to the ground terminal; wherein, in the first regulation branch, the drain of the first PMOS transistor and the gates of the first to fourth PMOS transistors are all connected to the first output terminal of the digital-to-analog converter, the drain of the second NMOS transistor is connected to the input terminal of the second stage inverter of the first clock transmission channel, the drain of the third NMOS transistor is connected to the input terminal of the third stage inverter of the second clock transmission channel, the drain of the third PMOS transistor is connected to the input terminal of the second stage inverter of the second clock transmission channel, and the drain of the fourth PMOS transistor is connected to the input terminal of the third stage inverter of the first clock transmission channel; wherein, in the second regulation branch, the drain of the first PMOS transistor and the gates of the first to fourth PMOS transistors are all connected to the second output terminal of the digital-to-analog converter, the drain of the second NMOS transistor is connected to the input terminal of the second stage inverter of the second clock transmission channel, the drain of the third NMOS transistor is connected to the input terminal of the third stage inverter of the first clock transmission channel, the drain of the third PMOS transistor is connected to the input terminal of the second stage inverter of the first clock transmission channel, and the drain of the fourth PMOS transistor is connected to the input terminal of the third stage inverter of the second clock transmission channel.

2. The duty cycle adjustment circuit according to claim 1, characterized in that, The digital-to-analog converter includes: a fourth to sixteenth NMOS transistors, a fifth PMOS transistor, a binary-to-temperature encoding circuit, and a first to fifth NOR gates; The drain of the fourth NMOS transistor is connected to the gates of the fourth to ninth NMOS transistors and is connected to a bias input signal. The sources of the fourth to ninth NMOS transistors are connected to the ground terminal. The drain of the fifth NMOS transistor is connected to the sources of the tenth and eleventh NMOS transistors. The drain of the sixth NMOS transistor is connected to the sources of the twelfth and thirteenth NMOS transistors. The source of the seventh NMOS transistor is connected to the sources of the fourteenth to sixteenth NMOS transistors. The drains of the ninth, eleventh, thirteenth, and fifteenth NMOS transistors are connected together as the first output terminal of the digital-to-analog converter. The drains of the eighth, tenth, twelfth, and fourteenth NMOS transistors are connected together as the second output terminal of the digital-to-analog converter. The drain of the sixteenth NMOS transistor is connected to the drain and gate of the fifth PMOS transistor. The source of the fifth PMOS transistor is connected to the power supply terminal. Among them, the fifth, tenth, and eleventh NMOS transistors each include a group of NMOS transistors connected in parallel with each other. Among them, the seventh, fourteenth, fifteenth, and sixteenth NMOS transistors each include a group of NMOS transistors connected in parallel with each other. The binary-to-temperature encoding circuit outputs a pair of complementary temperature encodings and is respectively connected to one input terminal of the first group and the second group of NOR gates. The output terminal of the first group of NOR gates is connected to the gates of the NMOS transistors in the eleventh NMOS transistor. The output terminal of the second group of NOR gates is connected to the gates of the NMOS transistors in the tenth NMOS transistor. The output terminal of the third group of NOR gates is respectively connected to the gate of the twelfth NMOS transistor, the gates of the NMOS transistors in the fourteenth NMOS transistor, and one input terminal of the fifth group of NOR gates. The output terminal of the fourth group of NOR gates is respectively connected to the gate of the thirteenth NMOS transistor, the gates of the NMOS transistors in the fifteenth NMOS transistor, and the other input terminal of the fifth group of NOR gates. The output terminal of the fifth group of NOR gates is respectively connected to the gates of the NMOS transistors in the sixteenth NMOS transistor.

3. The duty cycle adjustment circuit according to claim 2, wherein The digital-to-analog converter has an 8-bit data signal D<8:1>. The binary-to-temperature encoding circuit receives the data signal D<7:4> and converts it into a pair of 15-bit complementary temperature encodings T<15:1>, TB<15:1>. The other input terminal of the first group of NOR gates receives the data signal DB<8>. The other input terminal of the second group of NOR gates receives the data signal D<8>. One input terminal of the third group of NOR gates receives the data signal D<8>, and the other input terminal receives the data signal D<3:1>. One input terminal of the fourth group of NOR gates receives the data signal DB<8>, and the other input terminal receives the data signal DB<3:1>.

4. The duty cycle adjustment circuit according to claim 3, characterized in that One input terminal of the first group of NOR gates receives the data signal TB<15:1>, and the other input terminal receives the data signal DB<8>, and outputs the data signal PTD<15:1>; one input terminal of the second group of NOR gates receives the data signal T<15:1>, and the other input terminal receives the data signal D<8>, and outputs the data signal NTD<15:1>; one input terminal of the third group of NOR gates receives the data signal D<8>, and the other input terminal receives the data signal D<3:1>, and outputs the data signal ND<3:1>; one input terminal of the fourth group of NOR gates receives the data signal DB<8>, and the other input terminal receives the data signal DB<3:1>, and outputs the data signal PD<3:1>; two input terminals of the fifth group of NOR gates respectively receive the data signals ND<2:1> and PD<2:1>, and output the data signal CD<2:1>; the gates of the NMOS transistors in the tenth NMOS transistor are controlled by the data signal NTD<15:1>, the gates of the NMOS transistors in the eleventh NMOS transistor are controlled by the data signal PTD<15:1>, the gate of the twelfth NMOS transistor is controlled by the data signal ND<3>, the gate of the thirteenth NMOS transistor is controlled by the data signal PD<3>, the gates of the NMOS transistors in the fourteenth NMOS transistor are controlled by the data signal ND<2:1>, the gates of the NMOS transistors in the fifteenth NMOS transistor are controlled by the data signal PD<2:1>, and the gates of the NMOS transistors in the sixteenth NMOS transistor are controlled by the data signal CD<2:1>.

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