Monolithic electronic device

Abstract

A method of forming and testing a plurality of monolithic electronic devices is provided. As part of the method, an array of monolithic devices including a Group III nitride is formed on a sacrificial substrate. A test substrate including electrical contacts is aligned with electrical contacts of the array of monolithic devices and bonded to the array of monolithic devices by a bonding dielectric layer. Power is supplied from the test substrate to test the monolithic devices of the array of monolithic devices. The sacrificial substrate is then selectively removed to isolate each monolithic electronic device, wherein the sacrificial dielectric layer is removed to separate each monolithic electronic device from the test substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to Group III nitride semiconductors. In particular, the present disclosure relates to electronic devices comprising Group III nitride semiconductors. BACKGROUND

[0002] A micro LED (Micro LED) is generally defined as an LED having a size of 100 pm x 100 pm or less. Micro LEDs can be arranged in an array to form a self-emissive micro display / projector, which can be suitable for use in a variety of devices, such as smart watches, head-mounted displays, micro projectors for AR and VR applications, and large area displays.

[0003] One known form of micro LED array comprises a plurality of LEDs formed from Group III nitride. Group III nitride LEDs are inorganic semiconductor LEDs containing GaN and its alloys with InN and AlN in the active light emitting region. Group III nitride LEDs can be driven at significantly higher current densities and emit higher optical power densities than conventional large area LEDs, such as Organic Light Emitting Diodes (OLEDs) where the light emitting layer is an organic compound. The higher luminance (brightness), defined as the amount of light emitted by a light source per unit area in a given direction, makes micro LEDs suitable for applications where high brightness is required or beneficial.

[0004] Known micro LED fabrication techniques include forming one or more GaN layers on a sapphire substrate to produce LEDs that emit blue or green light. For LEDs that emit red light, known fabrication techniques include forming one or more InAlGaP layers on a GaAs substrate.

[0005] A large area display comprising micro LEDs can be formed from a plurality of red, green and blue micro LEDs. For example, for a 4K resolution display, each display can provide approximately 8,300,000 pixels. Accordingly, 8,300,000 red, green and blue LEDs can be provided to form a single display (i.e. a total of 24,900,000 LEDs per display). The red, green and blue LEDs can be assembled on a display substrate using pick and place technology. Pick and place technology includes stamp systems, laser assisted systems and fluidic assembly. Assembly speeds vary from 1,000 to 10,000 components per second. Accordingly, assembly time for a 4K screen is approximately 1 hour.

[0006] When assembling displays using pick and place components, the failure rate of the pick and place components can impact the yield of the display. For example, the above example of a 4K resolution display includes 24,900,000 LEDs. Thus, for such a large number of LEDs, even a relatively small failure rate can result in many failed LEDs being included in the display.

[0007] Against this background, it is an object of the present invention to provide an improved electronic device formation method suitable for assembly using a pick and place process. SUMMARY

[0008] The present inventors have realised that, in an attempt to reduce the failure rate of pick and place components such as monolithic electronic devices including Group III nitrides, it is desirable to test each component before it is used in a pick and place component. However, testing each component individually is very time consuming.

[0009] Accordingly, there is provided a method of forming and testing a plurality of monolithic electronic devices. The method comprises:

[0010] a) forming an array of monolithic electronic devices comprising:

[0011] forming a common semiconducting layer including Group III nitrides on a sacrificial substrate;

[0012] forming an array of monolithic electronic devices on a surface of the common semiconducting layer on a side of the common semiconducting layer opposite the sacrificial substrate, each monolithic electronic device of the array of monolithic electronic devices comprising a plurality of Group III nitride layers;

[0013] forming a planarising dielectric layer on the array of monolithic electronic devices to provide a planarising dielectric surface that is substantially aligned with the surface of the common semiconducting layer;

[0014] forming a trench grid by etching the planarising dielectric layer and the common semiconducting layer from the planarising dielectric surface all the way to the sacrificial substrate, wherein the trench grid surrounds each of the monolithic electronic devices;

[0015] forming first electrical contacts to each of the monolithic electronic devices through the planarising dielectric layer,

[0016] forming a sacrificial dielectric layer over the trench grid and the planarising surface of the planarising dielectric layer to form a first bonding surface that is substantially aligned with the surface of the common semiconducting layer, wherein the first bonding surface comprises first apertures aligned with each of the first electrical contacts;

[0017] b) providing a test substrate comprising:

[0018] an electronic substrate comprising electronic test circuitry configured to supply power to each of the monolithic electronic devices of the array of monolithic electronic devices; and

[0019] a plurality of second electrical contacts arranged on the electronic substrate to correspond to the arrangement of the first electrical contacts in the array of monolithic electronic devices;

[0020] wherein a bonding dielectric layer is formed on the electronic substrate to provide a second bonding surface comprising a second aperture aligned with each of the second electrical contacts;

[0021] c) aligning the second electrical contacts of the test substrate with the first electrical contacts of the array of monolithic electronic devices and bonding the second bonding surface of the test substrate to the first bonding surface of the sacrificial dielectric layer such that the first and second electrical contacts are in electrical contact;

[0022] d) supplying power from the test substrate to the array of monolithic electronic devices to test each of the monolithic electronic devices in the array of monolithic electronic devices through the plurality of first and second electrical contacts; and

[0023] e) selectively removing a first portion of the sacrificial substrate through the thickness of the sacrificial substrate to isolate each monolithic electronic device; and

[0024] removing the sacrificial dielectric layer to isolate each of the monolithic electronic devices from the test substrate.

[0025] The method according to the first aspect comprises bonding an array of monolithic electronic devices to a test substrate. In this way, the test substrate provides a handling substrate to allow removal of a sacrificial substrate on which the monolithic electronic devices are formed. Furthermore, the test substrate allows for the integration of testing of each monolithic electronic device into the manufacturing process. Thus, the method according to the first aspect provides a more efficient method of forming and testing a plurality of monolithic electronic devices due to the integration of device testing into the method.

[0026] The different aspects of the application are defined in more detail in the following paragraphs. Each aspect so defined can be combined with any other aspect or aspects unless clearly indicated to the contrary. In particular, any feature indicated as being optional can be combined with any other feature or features indicated as being optional.

[0027] In some embodiments, the bonding dielectric layer is a sacrificial bonding dielectric layer, where the sacrificial bonding dielectric layer is configured to be selectively removed along with the sacrificial dielectric layer to separate each monolithic electronic device from the test substrate. In some embodiments, the test substrate can be bonded to the bonding surface of the sacrificial dielectric layer by direct bonding (i.e., fusion bonding). For example, in some embodiments, the sacrificial bonding dielectric layer can include Si02or SiN x .

[0028] In some embodiments, after the sacrificial dielectric layer is removed to separate each monolithic electronic device from the test substrate, the test substrate can be reused in the method of forming and testing a plurality of monolithic devices.

[0029] In some embodiments, the electronic test circuitry of the test substrate is configured to supply power in parallel to each monolithic electronic device. Thus, the test substrate can provide an efficient method for testing an array of monolithic devices.

[0030] In some embodiments, the common semiconductor layer can include an n-type doped III-nitride. For example, in some embodiments, the common semiconductor layer can include GaN and an n-type dopant, such as Si or Ge. The common semiconductor layer can have a thickness (in a direction perpendicular to the sacrificial substrate) of at least 500 nm. The common semiconductor layer can have a thickness (in a direction perpendicular to the sacrificial substrate) of no more than 5 pm.

[0031] The sacrificial substrate can be formed from a substrate configured to provide a sacrificial substrate surface having an in-plane lattice constant suitable for growing a III-nitride layer thereon. For example, the sacrificial substrate can include a sapphire or silicon substrate.

[0032] In some embodiments, the array of monolithic electronic devices can be formed as a regularly spaced array. The regularly spaced array can be similar to any configuration for a close packing of circles (or polygons), such as a square packing or a hexagonal packing. Each monolithic electronic device within the array can have a surface area on the common semiconductor layer that is generally elliptical or polygonal in shape.

[0033] In some embodiments, the planarization dielectric layer can be formed from a plurality of passivation layers. Each passivation layer can include a dielectric, such as silicon dioxide or silicon nitride. The planarization dielectric layer can be subjected to a chemical mechanical polishing process to improve the smoothness (i.e., reduce the surface roughness) of the planarization dielectric surface.

[0034] In some embodiments, the trench grid can have a width (in a direction between adjacent monolithic electronic devices in the array of monolithic electronic devices) on the surface of the sacrificial substrate of at least 500 nm. As such, the pixel-defining trenches can separate each monolithic LED pixel from an adjacent monolithic LED pixel on the sacrificial substrate. As such, the pixel-defining trenches can surround (i.e., encircle) a perimeter of each monolithic LED pixel on the sacrificial substrate.

[0035] In some embodiments, the sacrificial dielectric layer can include one or more of silicon dioxide or silicon nitride. The sacrificial dielectric layer can be formed as a substantially continuous gap fill layer. As such, the sacrificial dielectric layer can be disposed to fill any gaps or voids to provide a bonding surface. As such, the bonding surface formed can be a substantially continuous planar surface aligned with the surface of the common semiconductor layer. In some embodiments, the bonding surface is parallel to the surface of the common semiconductor layer. In some embodiments, the sacrificial dielectric layer is formed such that it has a thickness on the planarized surface of at least 500 nm. It can be appreciated that the thickness of the sacrificial dielectric layer in other regions can be thicker (or thinner) due to the non-uniform nature of the intermediate structure. In some embodiments, the sacrificial dielectric layer is formed such that it has a thickness on the planarized surface of no more than 2 pm.

[0036] In some embodiments, each monolithic electronic device of the array of monolithic electronic devices includes a light emitting diode (LED). Each LED can be formed from a plurality of Group III nitride layers. In some embodiments, each monolithic electronic device can include one or more electronic devices selected from: a transistor, a capacitor, a resistor, a diode. For example, in one embodiment, a monolithic electronic device can include a transistor, an LED, and a capacitor.

[0037] In some embodiments, each monolithic electronic device is a monolithic light emitting diode (LED) pixel that includes a plurality of LED sub-pixels on a surface of a common semiconductor layer. Each LED sub-pixel comprises a stack of Group III nitride layers. The monolithic LED pixels can each be suitable for assembly in an LED display. Each LED sub-pixel of a monolithic LED pixel can have an associated light extraction feature. Thus, each monolithic LED pixel can include a plurality of LED devices monolithically formed on a common semiconductor layer. Once separated, the monolithic LED pixels can be assembled to form a display, for example by using a pick-and-place method. By monolithically forming a plurality of LED devices (LED sub-pixels), the number of discrete elements to be assembled to form a display can be reduced.

[0038] In some embodiments, each LED sub-pixel is configured to produce light having a first wavelength of at least 380 nm. In this way, each LED sub-pixel can produce visible light. In some embodiments, each LED sub-pixel is configured to produce light having a first wavelength of no more than 490 nm. Thus, each LED sub-pixel can produce substantially blue visible light. In the present disclosure, when an LED is referred to as producing light of a particular wavelength, it is to be understood that this refers to the peak wavelength of the light produced by the LED.

[0039] In some embodiments for forming monolithic LED pixels, after bonding the test substrate to the monolithic array of electronic devices, the method comprises forming light extraction features for each monolithic LED pixel, comprising: selectively removing a second portion of the sacrificial substrate aligned with each LED sub-pixel.

[0040] Thus, in some embodiments, a plurality of monolithic electronic devices (e.g. LED sub-pixels) can be provided on a common semiconductor layer comprising Group III nitride. The common semiconductor layer is formed on a sacrificial substrate.

[0041] Thus, the method according to the first aspect allows for processing both major surfaces of the common semiconductor layer by providing a sacrificial substrate and a test substrate. The sacrificial substrate provides an initial substrate on which the common semiconductor layer and monolithic electronic devices can be formed. Subsequently, the monolithic electronic devices can be attached to the test substrate to allow for removing portions of the sacrificial substrate in order to form further device features (e.g. light extraction features) on the opposite side of the common semiconductor layer. By processing both major surfaces of the common semiconductor layer, a plurality of monolithic electronic devices can be monolithically formed on the common semiconductor layer.

[0042] In some embodiments, forming light extraction features for each monolithic LED pixel comprises patterning the first portion of the surface of the common semiconductor layer with scattering features configured to increase the light extraction efficiency of each LED sub-pixel. Thus, the common semiconductor layer can be further processed to improve the efficiency of the LED sub-pixels.

[0043] In some embodiments, forming light extraction features for each monolithic LED pixel includes selectively removing a second portion of the sacrificial substrate aligned with each LED sub-pixel to form a container volume for each LED sub-pixel, and disposing a first color conversion layer in at least one of the container volumes of each of the monolithic LED pixels. The first color conversion layer can be configured to absorb light having a first wavelength and emit converted light having a first converted light wavelength that is longer than the first wavelength. In some embodiments, the first converted light wavelength is at least 500 nm. Thus, the monolithic LED pixel can include LED sub-pixels that emit light having a first wavelength and LED sub-pixels that emit light having a first converted light wavelength. In some embodiments, the first converted light wavelength can be no more than 650 nm. Thus, the monolithic pixel can be configured to provide visible light having a color selected from a red, green, or blue LED.

[0044] In some embodiments, a second color conversion layer is disposed in at least one other container volume of each of the monolithic LED pixels, the second color conversion layer being configured to absorb light of the first wavelength and emit converted light having a second converted light wavelength that is longer than the first converted light wavelength. Thus, the monolithic LED pixel according to the first aspect can be configured to emit light comprising three different wavelengths (the first wavelength, the first converted light wavelength, the second converted light wavelength).

[0045] In some embodiments, the first color conversion layer and / or the second color conversion layer includes a phosphor, an organic molecule, or a quantum dot. Thus, the first and / or second color conversion layer can be provided to convert light of the first wavelength so that the monolithic LED pixel can emit light having a combination of different wavelengths.

[0046] In some embodiments, each Ill-nitride layer of each LED sub-pixel can include one or more of AlInGaN, AlGaN, InGaN, and GaN. As used herein, any reference to a material by constituent elements includes all stoichiometries available for that material. Thus, for example, AlGaN includes all alloys thereof, such as Al x Ga 1-x N, where x is not equal to 1 or 0. The stoichiometry of each layer can vary depending on the function of the particular layer.

[0047] For example, in some embodiments, each LED sub-pixel can include a superlattice of Ill-nitride layers, an active layer configured to produce light, an electron blocking layer, and one or more p-type semiconductor layers. The active layer can include one or more quantum well layers configured to produce light.

[0048] In some embodiments, after forming the planarization dielectric layer, a third portion of the planarization dielectric layer can be selectively removed, and anode contact metallization can be formed between the anode of each LED sub-pixel and the planarization dielectric surface. In some embodiments, after forming the planarization dielectric layer, a fourth portion of the planarization dielectric layer can be selectively removed, and common cathode contact metallization can be formed for each monolithic LED pixel between the common semiconductor layer and the planarization dielectric surface.

[0049] In some embodiments, the surface of the common cathode contact metallization forming a portion of the planarization dielectric surface overlaps at least one of the LED sub-pixels forming each monolithic LED pixel. Thus, electrical contact can be provided for each LED sub-pixel of a monolithic LED pixel in a spatially efficient manner.

[0050] In some embodiments, one of the LED sub-pixels of each monolithic LED pixel has a larger surface area on the common semiconductor layer than the other LED sub-pixel of each monolithic LED pixel.

[0051] In some embodiments, each monolithic LED pixel includes at least three or at least four LED sub-pixels of a monolithically formed LED array on the common semiconductor layer. For example, in one embodiment, each monolithic LED pixel can include four LED sub-pixels of a square packed array.

[0052] In some embodiments, each monolithic LED pixel formed can be a monolithic micro-LED pixel. Thus, each LED sub-pixel can be a micro-LED sub-pixel having a size no larger than 100 pm x 100 pm. In some embodiments, the surface area of each LED sub-pixel on the common semiconductor layer can define an area no larger than 100 pm x 100 pm. In some embodiments, the surface area of each LED sub-pixel on the common semiconductor layer can define an area no larger than 50 pm x 50 pm, 30 pm x 30 pm, 20 pm x 20 pm, or 10 pm x 10 pm.

[0053] According to a second aspect of the disclosure, there is provided a monolithic device array for bonding to a test substrate of the third aspect. The monolithic device array comprises a sacrificial substrate, a common semiconductor layer, a monolithic array of electronic devices, a planarization dielectric layer, first electrical contacts, and a sacrificial dielectric layer. The common semiconductor layer comprises a group III nitride and is disposed on the sacrificial substrate. The monolithic array of electronic devices is disposed on a surface of the common semiconductor layer on a side of the common semiconductor layer opposite the sacrificial substrate. Each monolithic electronic device of the monolithic array of electronic devices comprises a plurality of group III nitride layers. The planarization dielectric layer is disposed on the monolithic array of electronic devices to provide a planarization dielectric surface that is aligned with the surface of the common semiconductor layer. The planarization dielectric layer defines a grid of trenches extending from the planarization dielectric surface to the sacrificial substrate, wherein the grid of trenches surrounds each monolithic electronic device. The first electrical contacts are provided for each monolithic electronic device. The first electrical contacts extend from each monolithic electronic device to the planarization dielectric surface. The sacrificial dielectric layer is disposed within the grid of trenches and over the planarization surface of the planarization dielectric layer to provide a first bonding surface that is generally aligned with the surface of the common semiconductor layer. The first bonding surface comprises a first aperture aligned with each first electrical contact.

[0054] Accordingly, the second aspect of the disclosure provides a monolithic device array configured to be bondable to a test substrate of the third aspect of the disclosure. The monolithic device array of the second aspect of the disclosure can form part of the method of the first aspect. The second aspect of the disclosure provides a monolithic array of electronic devices that can be tested in parallel by bonding them to a test substrate of the third aspect of the disclosure. It will be appreciated that the monolithic device array can comprise any of the optional features of the monolithic device array discussed above in relation to the first aspect of the disclosure.

[0055] In some embodiments, each monolithic electronic device of the monolithic array of electronic devices comprises a light emitting diode (LED). Accordingly, the monolithic device array of the second aspect provides an as-formed array of monolithic LEDs that can be efficiently tested.

[0056] In some embodiments, each monolithic electronic device is a monolithic light emitting diode (LED) pixel comprising a plurality of LED sub-pixels on the surface of the common semiconductor layer, each LED sub-pixel comprising a stack of group III nitride layers.

[0057] According to a third aspect of the present disclosure, a test substrate for bonding to the monolithic device array of the second aspect of the present disclosure is provided. The test substrate includes an electronic substrate, a plurality of second electrical contacts, and a bonding dielectric layer. The electronic substrate includes an electronic test circuit configured to supply power to each monolithic electronic device in the monolithic electronic device array. The plurality of second electrical contacts are arranged on the electronic substrate to correspond to the arrangement of the first electrical contacts of the monolithic electronic device array. The bonding dielectric layer is formed on the electronic substrate to provide a second bonding surface. The second bonding surface includes a second hole aligned with each second electrical contact.

[0058] Thus, a third aspect of the present disclosure provides a test substrate configured to be bonded to the monolithic device array of the second aspect of the present disclosure. The test substrate may be provided according to the method described in the first aspect of the present disclosure. It should be understood that the test substrate may include any of the optional features of the test substrate discussed above with respect to the first aspect of the present disclosure.

[0059] In some embodiments, the bonding dielectric layer is a sacrificial bonding dielectric layer configured to be selectively removed along with the sacrificial dielectric layer to separate each monolithic electronic device from the test substrate.

[0060] In some embodiments, the sacrificial bonding dielectric layer is configured to be selectively removed so that the test substrate can be reused for bonding to a monolithic electronic device.

[0061] In some embodiments, an etch stop layer may be provided between the bonding dielectric layer and the electronic substrate.

[0062] In some embodiments, the electronic test circuitry of the test substrate is configured to supply power to each monolithic electronic device in parallel. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The present disclosure will now be described in conjunction with the following non-limiting drawings. Further advantages of the present disclosure will become apparent by reference to the detailed description when considered in conjunction with the accompanying drawings, which are not to scale so as to more clearly show details, wherein like reference numerals indicate like elements throughout the several views, and wherein:

[0064] Figure 1 shows an isometric view of the light emitting side of a monolithic LED pixel according to an embodiment of the present disclosure;

[0065] Figure 2 Shown Figure 1 Plan view of the contact side of a monolithic LED pixel.

[0066] Figure 3 shows a first intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the present disclosure;

[0067] Figure 4 A second intermediate step in a method of forming monolithic LED pixels according to embodiments of the disclosure is shown;

[0068] Figure 5 A third intermediate step in a method of forming monolithic LED pixels according to embodiments of the disclosure is shown;

[0069] Figure 6 A fourth intermediate step in a method of forming monolithic LED pixels according to embodiments of the disclosure is shown;

[0070] Figure 7 A fifth intermediate step in a method of forming monolithic LED pixels according to embodiments of the disclosure is shown;

[0071] Figure 8 A sixth intermediate step in a method of forming monolithic LED pixels according to embodiments of the disclosure is shown;

[0072] Figure 9 A seventh intermediate step in a method of forming monolithic LED pixels according to embodiments of the disclosure is shown;

[0073] Figure 10 An eighth intermediate step in a method of forming monolithic LED pixels according to embodiments of the disclosure is shown;

[0074] Figure 11 A ninth intermediate step in a method of forming monolithic LED pixels according to embodiments of the disclosure is shown;

[0075] Figure 12 A tenth intermediate step in a method of forming monolithic LED pixels according to embodiments of the disclosure is shown;

[0076] Figure 13 An eleventh intermediate step in a method of forming monolithic LED pixels according to embodiments of the disclosure is shown;

[0077] Figure 14 A twelfth intermediate step in a method of forming monolithic LED pixels according to embodiments of the disclosure is shown;

[0078] Figure 15 A thirteenth intermediate step in a method of forming monolithic LED pixels according to embodiments of the disclosure is shown;

[0079] Figure 16 A fourteenth intermediate step in a method of forming monolithic LED pixels according to embodiments of the disclosure is shown;

[0080] Figure 17 A fifteenth intermediate step in a method of forming monolithic LED pixels according to embodiments of the disclosure is shown;

[0081] Figure 18 A sixteenth intermediate step in a method of forming a monolithic LED pixel according to embodiments of the disclosure is shown;

[0082] Figure 19 A monolithic LED pixel according to embodiments of the disclosure is shown.

[0083] Figure 20 A cross-section along line B-B’ of an intermediate step is shown, corresponding to the intermediate step of Figure 4 ;

[0084] Figure 21 A cross-section along line B-B’ of an intermediate step is shown, corresponding to the intermediate step of Figure 5 ;

[0085] Figure 22 A cross-section along line B-B’ of an intermediate step is shown, corresponding to the intermediate step of Figure 7 ;

[0086] Figure 23 A cross-section along line B-B’ of an intermediate step is shown, corresponding to the intermediate step of Figure 9 ;

[0087] Figure 24 A cross-section along line B-B’ of an intermediate step is shown, corresponding to the intermediate step of Figure 10 ;

[0088] Figure 25 A cross-section along line B-B’ of an intermediate step is shown, corresponding to the intermediate step of Figure 10 , further comprising a sacrificial dielectric layer;

[0089] Figure 26 A cross-section along line B-B’ of an intermediate step is shown, corresponding to the intermediate step of Figure 11 ;

[0090] Figure 27 A cross-section along line B-B’ of an intermediate step is shown, corresponding to the intermediate step of Figure 13 ;

[0091] Figure 28 A cross-section along line B-B’ of a test substrate step is shown, corresponding to the intermediate step of Figure 14 ;

[0092] Figure 29 A cross-section along line B-B’ of an intermediate step is shown, corresponding to the intermediate step of Figure 17 ;

[0093] Figure 30 A cross-section along line B-B’ of a monolithic LED pixel is shown. DETAILED DESCRIPTION

[0094] According to the present disclosure, a method of forming and testing monolithic electronic devices is provided. According to a first embodiment of the present disclosure, the monolithic electronic devices formed and tested are monolithic LED pixels 1. Of course, it will be appreciated that the present disclosure is not limited to forming monolithic LED pixels, but other monolithic electronic devices can be formed instead of monolithic LED pixels 1. For example, the monolithic electronic devices according to the present disclosure can comprise one or more of the following: capacitors, transistors, resistors, diodes, LEDs. For example, in one embodiment, each monolithic electronic device can comprise an LED and a transistor formed on a common semiconductor layer 102. The transistor can be configured to control a drive current to the LED, such that each monolithic electronic device is configured to provide an LED and an associated drive transistor.

[0095] According to a first embodiment of the present disclosure, the monolithic LED pixel 1 can comprise a plurality of LED sub-pixels 10, 20, 30. An isometric view of the monolithic LED pixel 1 of the first embodiment is shown in Figure 1 Figure 1 The monolithic LED pixel of the first embodiment comprises three LED sub-pixels 10, 20, 30. The three LED sub-pixels 10, 20, 30 are each configured to emit light of a different (peak) wavelength.

[0096] A plan view of the monolithic LED pixel 1 is shown in Figure 2 Figures 3 to 19 and Figures 20 to 30 The method of forming the monolithic LED pixel 1 will be described next with reference to Figures 3 to 19 A cross-section of the monolithic LED pixel 1 along the line A-A’ shown in Figure 2 is shown during an intermediate step of the method of forming the monolithic LED pixel 1. Figures 20 to 30 A cross-section of the monolithic LED pixel 1 along the line B-B’ shown in Figure 2 is shown during an intermediate step of the method of forming the monolithic LED pixel 1.

[0097] The method of forming the monolithic LED pixel 1 according to the first embodiment comprises forming an intermediate array of LED sub-pixels 100. The intermediate array of LED sub-pixels 100 comprises a plurality of LED sub-pixels 103 formed on a sacrificial substrate 101.

[0098] To form the intermediate array of LED sub-pixels 100, a common semiconductor layer 102 comprising a III-nitride is formed on a first major surface 131 of a sacrificial substrate 101. Thus, the method of forming the monolithic LED pixel 1 comprises forming a common semiconductor layer 102 comprising a III-nitride on a sacrificial substrate 101.

[0099] ​​The sacrificial substrate 101 can comprise a silicon substrate, a silicon carbide substrate, or a sapphire substrate. In Figure 3 In embodiments, the sacrificial substrate 101 comprises a silicon substrate having a plurality of Group III nitride buffer layers formed thereon.

[0100] As shown in Figure 3 , the common semiconductor layer 102 can be formed as a substantially continuous film on the surface of the sacrificial substrate 101. In this way, the common semiconductor layer 102 substantially covers the entire surface of the sacrificial substrate 101. The common semiconductor layer 102 can comprise an n-type doped Group III nitride semiconductor. For example, in Figure 3 embodiments, the common semiconductor layer 102 comprises GaN. Figure 3 The common semiconductor layer 102 in may be n-type, doped with any suitable n-type dopant, such as Si or Ge. The common semiconductor layer 102 can be formed on the sacrificial substrate 101 by any suitable method for forming Group III nitrides, such as Metal- Organo Chemical Vapour Deposition (MOCVD) or Molecular Beam Epitaxy (MBE).

[0101] Next, an array of LED sub-pixels can be formed on the surface 132 of the common semiconductor layer 102. The array of LED sub-pixels is formed on the side of the common semiconductor layer 102 opposite the sacrificial substrate 101. Each LED sub-pixel 103 comprises a stack of Group III nitride layers. Various methods for forming an array of LED sub-pixels are known to those skilled in the art.

[0102] In Figure 3 embodiments, the array of LED sub-pixels is formed from a continuous stack 140 of Group III nitride layers. The deposited continuous stack 140 of Group III nitride layers substantially covers the entire second major surface 132 of the common semiconductor layer 102. The continuous stack 140 of Group III nitride layers can subsequently be patterned using a selective removal process to define the array of LED sub-pixels 103. One possible selective removal process comprises coating the continuous stack 140 of Group III nitride layers with a masking layer using a photolithography process, and etching regions of the continuous stack 140 of Group III nitride layers to be selectively removed. An example of the resulting array of LED sub-pixels 103 is shown in Figure 4 of the present disclosure.

[0103] In some embodiments, for example as Figure 3As shown, the continuous stack of Ill-nitride layers 140 can include a superlattice 155 of Ill-nitride layers, an active layer 156 configured to generate light, an electron blocking layer 157, and one or more p-type semiconductor layers 158. The active layer can include one or more quantum well layers configured to generate light. In Figure 3 In embodiments, the active layer of each LED sub-pixel is configured to generate light having a wavelength of at least 380 nm and no more than 490 nm.

[0104] Accordingly, each LED sub-pixel 103 formed from the continuous stack of Ill-nitride layers 140 can include a superlattice 155 of Ill-nitride layers, an active layer 156 configured to generate light, an electron blocking layer 157, and one or more p-type semiconductor layers 158. The formation of each layer of the LED sub-pixel is known to the skilled person, for example, at least in GB 1811109.6 discussed subsequently.

[0105] Although Figure 3 and Figure 4 embodiments use a selective removal process to define the array of LED sub-pixels, it will be appreciated that the methods of the present disclosure are not limited to such LED sub-pixels. For example, a selective area growth method can be used to define the array of LED sub-pixels comprising a stack of Ill-nitride layers. Further details of suitable selective area growth methods can be found at least in GB 1811109.6.

[0106] As Figure 4 shown, each LED sub-pixel 103 forms a mesa structure extending from the common semiconductor layer 102. Each LED sub-pixel 103 is spaced apart from other LED sub-pixels 103 on the common semiconductor layer 102. Figure 4 The spacing between each LED sub-pixel 103 in the array can be different. In Figure 4 In embodiments, the spacing between adjacent LED sub-pixels 103 intended to form sub-pixels of the same monolithic LED pixel 1 can be less than the spacing between adjacent LED sub-pixels of different monolithic LED pixels.

[0107] After forming the plurality of LED sub-pixels 103, the intermediate array 100 can be further processed to include first electrical contacts to each LED sub-pixel 103. It will be appreciated that the skilled person is aware of various methods for forming electrical contacts to semiconductor devices. Accordingly, the first electrical contacts can be formed at various stages during the method of forming the monolithic LED pixel. Accordingly, the present disclosure, which relates to monolithic formation and testing of monolithic electronic devices, is not limited to any particular arrangement of first electrical contacts or method of forming first electrical contacts.

[0108] According to a first embodiment, a first electrical contact to each LED sub-pixel 103 can be formed by a plurality of contact layers. The contact layers can extend from each LED sub-pixel 103 to the planarized dielectric surface. The contact layers can each be formed in a plurality of steps. For example, as shown in Figure 5 a plurality of first contact layers 106 can be formed on the common semiconductor layer 102. The first contact layers 106 are configured to provide electrical contact to the common semiconductor layer 102. In some embodiments, a single first contact layer can be provided for each monolithic LED pixel 1 (i.e. a common contact), or in some embodiments, a first contact layer 106 can be provided for each LED sub-pixel 103. As shown in Figure 5 a first contact layer 106 is provided for each LED sub-pixel 103. The first contact layer 106 can comprise any suitable material for forming an ohmic contact with the common semiconductor layer 102. For example, the first contact layer 106 can comprise one or more of titanium, aluminium, titanium nitride, gold or copper. In Figure 5 embodiments, the first contact layer 106 can be deposited using thermal evaporation and patterned using a photolithographic method, such that the first contact layer 106 is disposed in the spaces between the LED sub-pixels 103 on the common semiconductor layer 102. In Figure 5 embodiments, the first contact layer 106 can be subjected to an annealing process after formation to improve the electrical conductivity of the contact between the first contact layer 106 and the common semiconductor layer 102.

[0109] Next, a first passivation layer 107 can be formed over the plurality of LED sub-pixels 103. The first passivation layer 107 can comprise an insulating layer, for example a dielectric. For example in Figure 5 embodiments, the first passivation layer 107 can comprise silicon dioxide or silicon nitride. The first passivation layer 107 can be formed using a plasma-enhanced chemical vapour deposition process, a chemical vapour deposition process, a physical vapour deposition process, evaporation or atomic layer deposition.

[0110] After formation of the first passivation layer 107, a plurality of openings can be formed through the first passivation layer 107 using a selective removal process such as photolithography and etching. The plurality of openings can be provided so as to provide areas for forming electrical connections to the common semiconductor layer 102 and p-type semiconductor layers of the LED sub-pixels 103. For example, in Figure 5 embodiments, a plurality of first openings 141 in the first passivation layer 107 are provided to allow formation of a cathode contact layer 109 in contact with the first contact layer 106 (i.e. in electrical connection with the common semiconductor layer 102), and a plurality of second openings 142 are formed to allow formation of an anode contact layer 108 in electrical contact with the p-type semiconductor layers of the LED sub-pixels 103.

[0111] An anode contact layer 108 can be formed in the second openings 142 on the p-type semiconductor layer of the LED sub-pixels 103. The anode contact layer 108 can be configured to form an ohmic contact with the p-type semiconductor layer of the LED sub-pixels 103. For example, in some embodiments, the anode contact layer can comprise one or more of nickel, silver, titanium or titanium nitride. The second contact layer 108 can be formed using an evaporation technique and patterned using a photolithographic method. Thus, the anode contact layer 108 can be provided in alignment with the plurality of second openings 142 in the passivation layer, which are aligned with each p-type semiconductor layer of each LED sub-pixel 103.

[0112] In some embodiments, the common semiconductor layer 102 for each monolithic LED pixel 1 can be further processed to provide a cross-talk reduction feature. For example, in Figure 1 embodiments, the common semiconductor layer 102 is subjected to a selective removal process to remove portions of the common semiconductor layer 102 that fall in regions of each monolithic LED pixel 1 between each LED sub-pixel. Thus, a portion of the common semiconductor layer 102 between two adjacent LED sub-pixels 103 of a monolithic LED pixel 1 (i.e. not covered by the adjacent LED sub-pixels 103) can be selectively removed. An example of such a cross-talk reduction feature is shown in Figure 6 where a cross-talk reduction trench 111 is formed by a selective removal process. As Figure 6 shown, the selective removal process (i.e. an etching process) is used to etch out the cross-talk reduction trench 111 from the second surface 132 of the common semiconductor layer 102 all the way to the first surface 131 of the sacrificial substrate 101. The cross-talk reduction trench is provided in a region of the monolithic LED pixel 1 between adjacent LED sub-pixels 103. Effectively, the cross-talk reduction trench 111 serves to separate the regions of the common semiconductor layer 102 corresponding to each sub-pixel 103. This in turn can prevent or reduce light from one LED sub-pixel 103 from passing through the common semiconductor layer 102 and being emitted through the light extraction features of another LED sub-pixel 103.

[0113] The cross-talk reduction trench 111 can be formed using any suitable photolithographic and etching techniques known to those skilled in the art, such as Reactive Ion Etching (RIE) or Inductively Coupled Plasma Etching (ICP).

[0114] After the optional cross-talk reduction features are formed, a planarization dielectric layer is formed over the intermediate array 100 of LED sub-pixels. Due to the topology of the intermediate array of LED sub-pixels (e.g., cross-talk reduction features, LED sub-pixels 130) and the process of forming electrical contacts, the planarization dielectric layer can be formed in another process step. Figure 7 、 8 And 9 provide one example of a method of forming a planarization dielectric layer according to the first embodiment. Those skilled in the art will appreciate that other methods of forming a planarization dielectric layer are known to those skilled in the art.

[0115] According to the first embodiment, a second passivation layer 112 can be formed over the intermediate array of LED pixels as shown in Figure 6 The second passivation layer 112 can include an insulating dielectric, such as silicon dioxide or silicon nitride. The second passivation layer 112 can be formed in a similar manner to the first passivation layer 107. The second passivation layer 112 can be formed over the intermediate structure to provide a first planarization surface 215 that is generally aligned with the first surface 131 of the sacrificial substrate 101 on which the monolithic LED pixels 1 are formed. The second passivation layer 112 can be formed in a manner that fills the cross-talk reduction trenches 111 and extends beyond the exposed surfaces of the LED sub-pixels 103.

[0116] After the second passivation layer 112 is formed, a plurality of third openings 143 can be formed in the second passivation layer 112 for forming a first contact metallization 114 to form electrical contact with the anode contact layer 108 and / or the cathode contact layer 109. The plurality of third openings can extend from the passivation surface 215 to the first contact layer 106 and / or the second contact layer 108. An example of such a first contact metallization is shown in Figure 8 where a first contact metallization 114 is formed for each second contact layer 108.

[0117] As part of forming a planarization dielectric layer according to the first embodiment, a third passivation layer 115 is formed on the passivation surface 215, such as shown in Figure 9 The third passivation layer 115 can be formed in a similar manner to the second passivation layer 112. The third passivation layer 115 provides a third passivation layer surface 217 on an opposite side of the third passivation layer 115 from the second passivation layer 112.

[0118] Similar to the second passivation layer 112, the third passivation layer 115 can also include a plurality of fourth openings 144 aligned with each LED sub-pixel for providing contact metallization. The fourth openings 144 can be subsequently filled with a second contact metallization 117 to form electrical contact to the p-type semiconductor layer of each LED sub-pixel 103. Each second contact metallization 117 can include a plurality of stacks of conductive layers. For example, the second contact metallization 117 can include one or more of titanium, tungsten, gold, and copper.

[0119] After forming the third passivation layer 115 and various contact metallizations, the third passivation layer surface 217 can be further planarized using a polishing process such as chemical mechanical polishing (CMP). Providing a CMP process can reduce the surface roughness of the third passivation layer surface 217 to improve the bonding of the intermediate array 100 of LED sub-pixels to the test substrate 200. Accordingly, a chemical mechanical polishing process can be provided in order to improve the smoothness of the surface and reduce any defects or irregularities in the surface that can be formed as a result of the etching and contact metallization deposition processes.

[0120] Accordingly, the processes provided in the present embodiments Figure 7 , 8 and 9 provide a method of forming a planarized dielectric layer over an array of LED sub-pixels to provide a planarized dielectric surface (i.e., third passivation layer surface 217) that is substantially aligned with the second surface 132 of the common semiconductor layer 102. Figure 7 , 8 and 9 also demonstrate the formation of first electrical contacts to each monolithic device. As shown in Figure 7 , 8 and 9, the first contact layer can be formed from a plurality of contact metallization layers 114, 117. The first contact layer can also include an anode or cathode contact layer for improving electrical contact with each LED sub-pixel 103. It should be appreciated that the first embodiment is one example of forming first electrical contacts. Accordingly, the first electrical contacts can be provided in various other manners known to those skilled in the art. For example, the formation of electrical contacts can be provided after forming a planarized dielectric layer over the intermediate array 100 of LED sub-pixels.

[0121] After forming the planarized dielectric surface 217 over the plurality of LED sub-pixels 103, the intermediate array 100 of LED sub-pixels is partially divided into a plurality of monolithic LED pixels 1 by etching a grid of trenches (i.e., pixel defining trenches 118). The pixel defining trenches 118 are formed by selectively removing layers that form the planarized dielectric layer from the planarized dielectric surface 217 to the sacrificial substrate 101. An example of the formation of pixel defining trenches 118 is shown in the disclosure of Figure 10 Figure 10 ​As shown, each monolithic LED pixel 1 includes at least two LED sub-pixels 103. Pixel-defining trenches 118 can be formed in a manner similar to the crosstalk reduction trenches 111 described above. After forming the pixel-defining trenches 118, it will be appreciated that the plurality of monolithic LED pixels 1 remain in a fixed arrangement due to the presence of the sacrificial substrate 101. Thus, due to the presence of the sacrificial substrate 101, the plurality of monolithic pixels 1 can still be handled and aligned as part of an intermediate array 100 of LED sub-pixels.

[0122] After forming the pixel-defining trenches 118 , a sacrificial dielectric layer 121 is formed over the pixel trenches and the planarized dielectric surface 217 to form a bonding surface 221 that is substantially aligned with the surface of the common semiconductor layer 102 .

[0123] In the method according to the first embodiment, an etch stop layer 119 may be provided before forming the sacrificial dielectric layer 121. For example, Figure 11 As shown, an etch stop layer 119 is formed as a substantially continuous layer over the pixel-defining trenches 118 and the planarized dielectric surface 217. The etch stop layer 119 may have a plurality of fifth openings 145 formed therethrough. Each of the fifth openings 145 of the etch stop layer 119 may be aligned with any contact metallization 117 present at the planarized dielectric surface 217. In some embodiments, the etch stop layer 119 may include silicon dioxide or silicon nitride. The etch stop layer 119 may be configured to provide a dielectric layer that is resistant to a subsequent etching process used to remove the sacrificial dielectric layer 121. As such, the etch stop layer 119 may increase process tolerances in a subsequent selective removal step for removing the sacrificial dielectric layer 121.

[0124] After the (optional) etch stop layer 119 is formed, a sacrificial dielectric layer 121 may be formed over the pixel defining trenches 118 and the planarized surface to form a bonding surface. The formation of the sacrificial dielectric layer 121 may include a multi-stage process for forming multiple layers. The sacrificial dielectric layer 121 may include one or more of silicon dioxide and silicon nitride. Figure 11 As shown, a plurality of sixth openings 146 can also be formed in the sacrificial dielectric layer 121 to allow electrical connections to the plurality of LED sub-pixels 103. Each sixth opening 146 can extend from the bonding surface through the thickness of the sacrificial dielectric layer to the underlying layer (e.g., contact metallization 117). The plurality of sixth openings 146 in the sacrificial dielectric layer 121 can be aligned with at least a portion of each contact metallization 117.

[0125] After the formation of the sacrificial dielectric layer 121, the bonding surface 221 can be further planarized using a chemical mechanical polishing process. Thus, the sacrificial dielectric layer 121 can provide a substantially planar surface aligned with the second surface 132 of the common semiconductor layer 102 for bonding the plurality of monolithic LED pixels 1 on the sacrificial substrate 101 to the test substrate 200.

[0126] Figure 12 An example of a test substrate 200 is shown in Fig. 1. The test substrate 200 provides a surface to which the bonding surface 221 of the sacrificial dielectric layer 121 can be bonded.

[0127] According to a first embodiment of the present disclosure, the test substrate 200 provides a test substrate surface 210 that will be in contact with the bonding surface 221 of the intermediate array 100 of LED sub-pixels. Figure 11 The test substrate 200 is shown in contact with the bonding surface 221 of the intermediate array 100 of LED sub-pixels.

[0128] In some embodiments, for example as shown in Fig. 1, the test substrate 200 comprises an electronic substrate 201. In some embodiments, the electronic substrate 201 can comprise a silicon wafer or any other substrate suitable for forming electronic circuits. In some embodiments, for example as shown in Fig. 1, a plurality of electronic layers 202, 203, 204, 205 can be provided on a surface of the electronic substrate 201. The plurality of electronic layers can comprise insulating layers 202, 204 and metal layers 203, 205 in order to form electronic connections and / or circuits on the first electronic substrate 201. The test substrate 200 is configured to provide test circuits for the monolithic LED pixels 1. The test substrate 200 will be discussed in more detail below. The electronic layers 202, 203, 204, 205 can be deposited on the first electronic substrate 201 using any suitable technique such as CVD, PECVD, thermal evaporation, PVD or ALD. Figure 12 Figure 12 In some embodiments, for example as shown in Fig. 1, the test substrate 200 comprises an electronic substrate 201. In some embodiments, the electronic substrate 201 can comprise a silicon wafer or any other substrate suitable for forming electronic circuits. In some embodiments, for example as shown in Fig. 1, a plurality of electronic layers 202, 203, 204, 205 can be provided on a surface of the electronic substrate 201. The plurality of electronic layers can comprise insulating layers 202, 204 and metal layers 203, 205 in order to form electronic connections and / or circuits on the first electronic substrate 201. The test substrate 200 is configured to provide test circuits for the monolithic LED pixels 1. The test substrate 200 will be discussed in more detail below. The electronic layers 202, 203, 204, 205 can be deposited on the first electronic substrate 201 using any suitable technique such as CVD, PECVD, thermal evaporation, PVD or ALD.

[0129] In some embodiments, the test substrate 200 can comprise a sacrificial test dielectric layer 206. The sacrificial test dielectric layer 206 can provide a test substrate surface 210 of the test substrate 200 for bonding. The sacrificial test dielectric layer 206 can be configured to be at least partially removed together with the sacrificial dielectric layer 121 in order to separate the monolithic LED pixels 1 from the test substrate 200.

[0130] In some embodiments, for example as shown in Fig. 1, the test substrate 200 comprises an electronic substrate 201. In some embodiments, the electronic substrate 201 can comprise a silicon wafer or any other substrate suitable for forming electronic circuits. In some embodiments, for example as shown in Fig. 1, a plurality of electronic layers 202, 203, 204, 205 can be provided on a surface of the electronic substrate 201. The plurality of electronic layers can comprise insulating layers 202, 204 and metal layers 203, 205 in order to form electronic connections and / or circuits on the first electronic substrate 201. The test substrate 200 is configured to provide test circuits for the monolithic LED pixels 1. The test substrate 200 will be discussed in more detail below. The electronic layers 202, 203, 204, 205 can be deposited on the first electronic substrate 201 using any suitable technique such as CVD, PECVD, thermal evaporation, PVD or ALD. Figure 12 ​In some embodiments shown, the test substrate 200 can further include a test etch stop layer 207. The test etch stop layer 207 can be disposed between the sacrificial test dielectric layer 206 and other layers 201, 202, 203, 204, 205 of the test substrate 200. The test etch stop layer 207 can be configured to provide a surface that is more resistant to a selective removal process used to selectively remove the sacrificial test dielectric layer 206. Thus, the test etch stop layer 207 provides a layer configured to protect other layers of the test substrate 200 from the selective removal process. Thus, the test etch stop layer 207 can improve reusability of the test substrate 200.

[0131] The sacrificial test dielectric layer 206 and the test etch stop layer 207 can be formed as a stack of dielectric layers including at least one or more of silicon dioxide and silicon nitride. The sacrificial test layer 206 can be formed to have a thickness of at least 50 nm in a direction perpendicular to a surface of the electronic substrate 201. In some embodiments, the thickness of the sacrificial test dielectric layer 206 can be no greater than 1 pm. The test etch stop layer 207 can have a thickness of at least 20 nm in a direction perpendicular to a surface of the electronic substrate 201. In some embodiments, the thickness of the test etch stop layer 207 can be no greater than 100 nm.

[0132] In some embodiments of the present disclosure, the test substrate 200 can provide a substrate on which a plurality of monolithic LED pixels 1 are held while, on the substrate, the light emission surface 130 of the sacrificial substrate 101 is further processed.

[0133] As Figure 13 shown, the test substrate can include an electronic substrate 201 including electronic test circuitry configured to supply power to each monolithic electronic device of the array of monolithic electronic devices. The test substrate can further include a plurality of test substrate electrical contacts arranged on the electronic substrate 201 to correspond to the arrangement of contact metallization 117 of the intermediate array of LED sub-pixels. In some embodiments, a sacrificial test dielectric layer 206 is formed on the electronic substrate 201 to provide a test bonding surface including apertures aligned with each test substrate electrical contact.

[0134] After the bonding process, the test substrate 200 can be configured to test each monolithic electronic device (e.g., each LED sub-pixel 103) by supplying power from the test substrate 200 to the array of LED sub-pixel arrays to test each LED sub-pixel 103. Thus, the test substrate 200 can form an electrical circuit between the test substrate electrical contacts and the contact metallization of the intermediate array of LED sub-pixels. Thus, each LED sub-pixel 103 can be tested in parallel using a testing process integrated into the method of forming the monolithic LED pixels 1.

[0135] In such embodiments, an electrical connection can be formed between the test substrate 200 and each monolithic LED pixel 1. Various methods for forming an electrical connection between two substrates to be brought into contact with each other are known to those skilled in the art. One example of such a method according to the first embodiment is shown in Figure 13 and 14 .

[0136] As shown in Figure 13 , a plurality of seventh openings 212 can be formed in the test substrate surface 210 of the test substrate 200. Each seventh opening extends from the test substrate surface 210 to one or more of the electronic layers 205 and 203 of the test substrate 200. The plurality of seventh openings 212 can each be aligned with one of the metal contacts of each LED sub-pixel 103. That is, the arrangement of the seventh openings 212 on the test substrate 200 corresponds to the arrangement of the sixth openings 146 on the intermediate array 100 of LED sub-pixels.

[0137] In some embodiments, as shown in Figure 13 , a plurality of conductive contacts 208 can be formed within the seventh openings 212 of the test substrate 200. Each of the conductive contacts 208 can extend from the electronic layers 203, 205 beyond the test surface 210 in a direction perpendicular to the test substrate 200. Thus, the conductive contacts 208 can protrude from the test surface 210. The conductive contacts 208 can be configured to extend from the test surface 210 in such a way that, when the test surface 210 is brought into contact with the bonding surface 121, the conductive contacts 208 form an electrical connection between the respective contact metallization of the intermediate array 100 of LED sub-pixels and the second contacts of the test substrate 200. In embodiments, the conductive contacts 208 can comprise a metal contact, such as one or more of titanium, gold, copper, or tin.

[0138] According to the forming method of the first embodiment of the present disclosure, the test substrate 200 can be bonded to the bonding face 221 of the sacrificial dielectric layer 121. Figure 14 One example of the test substrate 200 bonded to the intermediate array 100 of LED sub-pixels is shown. The test substrate 200 can be bonded to the bonding surface 221 using an aligner bonder (not shown). The aligner bonder enables the bonding surface 221 to be arranged parallel to the test surface 210 and enables the conductive contacts 208 of the test substrate 200 to be aligned with the sixth openings 146 of the sacrificial dielectric layer 121. The aligner bonder is then configured to bring the two surfaces into contact, whereby the sacrificial dielectric layer 121 forms a bond with the test substrate surface 210 of the test substrate 200. In some embodiments, the aligner bonder can apply one or more of heat and pressure to improve the bond formed between the test substrate surface 210 and the bonding surface 221.

[0139] For example, in some embodiments, the aligner bonder can apply a compressive force of at least 10 kN to bond the test substrate 200 to the intermediate array 100 of LED sub-pixels. In some embodiments, the aligner bonder can apply a compressive force of at least 20 kN, 30 kN, or 40 kN. By applying a greater compressive force, the reliability of forming a bond between the substrates can be improved. In some embodiments, the pressure can apply a compressive force of no more than 45 kN to reduce the risk of the substrates breaking or other undesirable deformation of the substrates during bonding.

[0140] In some embodiments, the aligner bonder can also be configured to heat the test substrate 200 and / or the intermediate array 100 of LED sub-pixels. For example, the aligner bonder can be configured to heat the test substrate 200 and / or the intermediate array 100 of LED sub-pixels to a temperature of at least 100 °C. In some embodiments, the aligner bonder can be configured to heat the test substrate 200 and / or the intermediate array 100 of LED sub-pixels to a temperature of at least: 200 °C, 300 °C, 400 °C, or 500 °C. The aligner bonder can be configured to maintain the temperature under compression and, optionally, for a period of time at the temperature. In some embodiments, the period of time can be at least: 1 minute, 2 minutes, 5 minutes, 10 minutes, or 1 hour. Thus, the use of pressure can improve the formation of a direct fusion bond at the interface between the test substrate 200 and the intermediate array 100 of LED sub-pixels.

[0141] Various methods for bonding two substrates together are known. For example, in the embodiments of FIGS. 1-3, the sacrificial dielectric layer 121 forms a direct bond with the sacrificial test dielectric layer 206. In other embodiments, different bonding techniques and bonding layers can be provided on one or both of the test substrate 200 and / or the intermediate array 100 of LED sub-pixels in order to bond the test substrate 200 to the bonding surface 221. The aligner bonder can also be configured to form an electrical connection between the conductive contacts 208 and the first and second contacts of each LED sub-pixel 103. Figure 14 In a first embodiment, as shown in FIG. 4, it will be appreciated that the sacrificial dielectric layer 121 and the sacrificial test dielectric layer 206 can extend as substantially continuous layers through the sacrificial substrate 101 and the electronic substrate 201, respectively. Thus, the sacrificial dielectric layer 121 and the sacrificial test dielectric layer 206 form a direct bond over a majority of the bonding surface of the intermediate array 100 of LED sub-pixels to securely bond the wafer together. In addition, a low resistance contact bond can be formed between the electronic layers 203, 205 of the test substrate 200 and each LED sub-pixel 30 through the conductive contacts 208.

[0142] Figure 14 In a second embodiment, as shown in FIG. 5, it will be appreciated that the sacrificial dielectric layer 121 and the sacrificial test dielectric layer 206 can extend as substantially continuous layers through the sacrificial substrate 101 and the electronic substrate 201, respectively. Thus, the sacrificial dielectric layer 121 and the sacrificial test dielectric layer 206 form a direct bond over a majority of the bonding surface of the intermediate array 100 of LED sub-pixels to securely bond the wafer together. In addition, a low resistance contact bond can be formed between the electronic layers 203, 205 of the test substrate 200 and each LED sub-pixel 30 through the conductive contacts 208.

[0143] ​Once the intermediate array of LED sub-pixels 100 is bonded to the test substrate 200, the intermediate array of LED sub-pixels 100 can be tested. Thus, each monolithic electronic device of the monolithic electronic device array (i.e., the intermediate array of LED sub-pixels 100) can be tested by powering the monolithic electronic device array from the test substrate 200 through the plurality of first and second electrical contacts. Reference is made below to Figure 29 The testing process is discussed in more detail.

[0144] In addition to the testing procedure, the light emitting side of each monolithic LED pixel 1 can be further processed to isolate each monolithic LED pixel 1 and form light extraction features for each monolithic LED pixel 1. The testing procedure can be performed at any time prior to removal of each monolithic LED pixel 1 from the test substrate 200.

[0145] Thus, the method of forming the first embodiment further includes selectively removing a first portion of the sacrificial substrate 101 that is aligned with the grid of pixel defining trenches 118 through the thickness of the sacrificial substrate 101 for isolating each monolithic LED pixel. For example, as shown in FIG. 1 1, the first portion of the sacrificial substrate 101 is removed to define a plurality of eighth openings 148 through the thickness of the sacrificial substrate 101 in a direction perpendicular to the light emission surface 130. The eighth openings can be formed using any selective removal process known to those skilled in the art, including, for example, a process of photolithography and etching of the sacrificial substrate 101. The pixel defining trenches and the first portion of the sacrificial substrate 101 surround each monolithic LED pixel 1. Thus, by removing the first portion of the sacrificial substrate 101 that is aligned with the pixel defining trenches 118, the sacrificial substrate 101 no longer connects each monolithic LED pixel 1 together. Rather, the bond formed between the sacrificial dielectric layer 121 and the test substrate 200 serves to maintain the relative position of each monolithic LED pixel 1 on the test substrate 200. Figure 15 The method of forming the first embodiment further includes forming light extraction features for each monolithic LED pixel 1. In some embodiments, the light extraction features of each monolithic pixel 1 can improve the efficiency of extracting light from each monolithic LED pixel. In some embodiments, the light extraction features can modulate the light emitted by each monolithic LED pixel 1. For example, the light extraction features can provide a color conversion layer for one or more LED sub-pixels of the monolithic LED pixel 1 such that the monolithic LED pixel 1 can output light having at least two different light (peak) wavelengths.

[0146] In some embodiments, for example, as shown in FIG. 12, a first light extraction feature 151 of each sub-pixel of the monolithic LED pixel 1 is formed by selectively removing a second portion of the sacrificial substrate 101 that is aligned with each LED sub-pixel 103.

[0147] Figure 15 In some embodiments, for example, as shown in FIG. 12, a first light extraction feature 151 of each sub-pixel of the monolithic LED pixel 1 is formed by selectively removing a second portion of the sacrificial substrate 101 that is aligned with each LED sub-pixel 103. ​

[0148] The second portions of the sacrificial substrate 101 can be selectively removed through the thickness of the sacrificial substrate 101 in a direction normal to the light emission surface 130. Thus, the second portions of the sacrificial substrate 101 can be removed to define a plurality of ninth openings 149 through the thickness of the sacrificial substrate 101. By removing the second portions of the sacrificial substrate 101, the light emission area of each LED sub-pixel 103 is able to more effectively output light through the light emission surface 130.

[0149] Each second portion of the sacrificial substrate 101 to be selectively removed is aligned with each LED sub-pixel 103. Thus, each monolithic LED pixel 1 can have a plurality of second portions of the sacrificial substrate 101 to be selectively removed to define a plurality of ninth openings 149 through the thickness of the sacrificial substrate 101. The number of second portions to be selectively removed corresponds to the number of LED sub-pixels 103 of each monolithic LED pixel 1. As shown, the area of the ninth openings 149 can be at least as large as the emission area of each LED sub-pixel. Thus, the light produced by each LED sub-pixel can be directed through the respective ninth opening 149 of each LED sub-pixel. Figure 15

[0150] As shown, the remaining portions of the sacrificial substrate 101 effectively separate each light emission surface of each LED sub-pixel from other light emission surfaces of other LED sub-pixels 103. Thus, in some embodiments, the remaining portions of the sacrificial substrate 101 can reduce or eliminate cross-talk between LED sub-pixels. Figure 15 In embodiments, the second portions of the sacrificial substrate 101 can be selectively removed so as to form a container volume 151 for each LED sub-pixel. Thus, the container volume can correspond to the plurality of ninth openings 149 shown in FIG. 1 IB. The container volume 151 can be a volume defined by the ninth openings 149 formed through the sacrificial dielectric layer 101 and the exposed first portion 170 of the surface of the common semiconductor layer 102. Each container volume 151 can be used to provide a volume in which a color conversion layer can be disposed.

[0151] Figure 15 In embodiments, the second portions of the sacrificial substrate 101 can be selectively removed so as to form a container volume 151 for each LED sub-pixel. Thus, the container volume can correspond to the plurality of ninth openings 149 shown in FIG. 1 IB. The container volume 151 can be a volume defined by the ninth openings 149 formed through the sacrificial dielectric layer 101 and the exposed first portion 170 of the surface of the common semiconductor layer 102. Each container volume 151 can be used to provide a volume in which a color conversion layer can be disposed. Figure 15 In some embodiments, as shown for example in FIG. 11C, a first color conversion layer 160 can be provided in at least one container volume 151 of each monolithic LED pixel 1. The first color conversion layer 160 can be configured to absorb light having a first wavelength and emit converted light having a first converted light wavelength that is longer than the first wavelength. Thus, the first color conversion layer 160 can be provided to convert light emitted by the LED sub-pixel on which the first color conversion layer 160 is provided into different, longer wavelength light.

[0152] Figure 16 In some embodiments, as shown for example in FIG. 11C, a first color conversion layer 160 can be provided in at least one container volume 151 of each monolithic LED pixel 1. The first color conversion layer 160 can be configured to absorb light having a first wavelength and emit converted light having a first converted light wavelength that is longer than the first wavelength. Thus, the first color conversion layer 160 can be provided to convert light emitted by the LED sub-pixel on which the first color conversion layer 160 is provided into different, longer wavelength light. ​​​

[0153] In some embodiments, the first color conversion layer 160 can comprise a phosphor, an organic molecule or a plurality of quantum dots. For LED sub-pixel arrays with a container volume having a surface area exceeding 1 mm 2 A larger particle size of the phosphor can be advantageous for LED sub-pixels with a container volume having a surface area less than 1 mm 2 For LED sub-pixels with a container volume having a surface area less than 1 mm

[0154] In some embodiments, the first color conversion layer 160 can completely fill the container volume 151 of the LED sub-pixel. In other embodiments, the first color conversion layer 160 can partially fill the container volume of the LED sub-pixel. For example, as shown in Figure 16 the first color conversion layer 160 substantially fills the entire volume of the first container volume.

[0155] In some embodiments, the first color conversion layer can be configured to first convert light having a first wavelength of approximately 380 nm to 490 nm into converted light having a first converted light wavelength of at least 500 nm to 650 nm. That is, the first color conversion layer 160 can be configured to convert substantially blue visible light produced by the LED sub-pixel 103 into substantially green visible light to be output by said LED sub-pixel.

[0156] In some embodiments, as shown in Figure 16 each monolithic LED pixel 1 can further comprise a second color conversion layer 161. The second color conversion layer 161 can be provided in at least another container volume of each monolithic LED pixel 1. Said second color conversion layer 161 can be configured to absorb light having a first wavelength and to emit converted light having a second converted light wavelength that is longer than the first converted light wavelength. Thus, a second color conversion layer 161 can be provided in addition to the first color conversion layer 160 in order to provide the monolithic LED pixel 1 with light of a further color. That is, the monolithic LED pixel 1 (which comprises: LED sub-pixels comprising no color conversion layer, LED sub-pixels comprising the first color conversion layer 160 and LED sub-pixels comprising the second color conversion layer 161) can output light comprising three different peak wavelengths. For example, in Figure 16In some embodiments, the monolithic LED pixel 1 can be configured to output visible light that includes substantially red, green, and blue components.

[0157] The second color conversion layer 161 can include a phosphor or a plurality of quantum dots. As such, the second color conversion layer 161 can be formed in a similar manner as the first color conversion layer 160. In some embodiments, the second color conversion layer can be configured to convert the first light having a wavelength of at least 380 nm and up to 490 nm to the second converted light having a second converted light wavelength of at least 550 nm and no greater than 680 nm.

[0158] Referring again to Figure 1 and 2 , it should be understood that the cross-section shown in Figures 3 to 16 illustrates two of the three LED sub-pixels included within the monolithic LED pixel 1. Thus, it should be understood that the other LED sub-pixel (not shown in Figure 16 ) can not include the first color conversion layer 160 or the second color conversion layer 161.

[0159] In some embodiments, the container volume 151 includes a light scattering medium (not shown) in place of the color conversion layer. For example, in the embodiment shown in Figure 1 , the B sub-pixel is configured to emit light having a first wavelength. Thus, the container volume 151 for the B sub-pixel does not include a color conversion layer 160, 161. In the embodiment shown in Figure 1 , the container volume 151 for the B pixel includes a light scattering medium. The light scattering medium can be configured to scatter light such that the light output by the B pixel can have a Lambertian light distribution, or a Full Width Half Max (FWHM) of 120 degrees (or wider). Thus, the light scattering medium can be provided to improve the light extraction efficiency and viewing angle of the light emitted from the LED sub-pixel B.

[0160] In some embodiments, the second portion of the sacrificial substrate 101 can be selectively removed by a thickness of the sacrificial substrate such that the first portion 170 of the surface of the common semiconductor layer 102 is exposed. In some embodiments, for example as shown in Figure 16 , a third light extraction feature can be formed for each monolithic LED pixel 1. The third light extraction feature can be formed by patterning the first portion 170 of the surface of the common semiconductor layer 102 to form a light scattering feature 171 configured to increase the light extraction efficiency of each LED sub-pixel.

[0161] For example, in the embodiment shown in Figure 16In embodiments, the light scattering features 171 are formed by selectively removing regions of the first portion 170 of the common semiconductor layer 102 to form a textured surface. Providing a textured surface at the interface between the common semiconductor layer 102 and each container volume can help reduce total internal reflection that occurs at the interface between the common semiconductor layer 102 and the container volume 151. Thus, the light scattering features 171 formed by patterning the first portion 170 of the surface of the common semiconductor layer 102 are configured to increase the light extraction efficiency of each LED sub-pixel. That is, the amount of light output by each LED sub-pixel can be increased by reducing the proportion of light that is reflected at the interface between the common semiconductor layer 102 and the container volume. Although in the embodiment shown the light scattering features 171 are formed by selectively removing regions of the first portion 170 of the common semiconductor layer 102, in other embodiments an anti-reflective coating or other similar optical coating aimed at improving the light extraction efficiency from a light emitting diode can be provided. Figure 16 In the embodiment shown, the light scattering features 171 are formed by selectively removing regions of the first portion 170 of the common semiconductor layer 102 to form a textured surface. Providing a textured surface at the interface between the common semiconductor layer 102 and each container volume can help reduce total internal reflection that occurs at the interface between the common semiconductor layer 102 and the container volume 151. Thus, the light scattering features 171 formed by patterning the first portion 170 of the surface of the common semiconductor layer 102 are configured to increase the light extraction efficiency of each LED sub-pixel. That is, the amount of light output by each LED sub-pixel can be increased by reducing the proportion of light that is reflected at the interface between the common semiconductor layer 102 and the container volume. Although in the embodiment shown the light scattering features 171 are formed by selectively removing regions of the first portion 170 of the common semiconductor layer 102, in other embodiments an anti-reflective coating or other similar optical coating aimed at improving the light extraction efficiency from a light emitting diode can be provided.

[0162] In some embodiments, for example Figure 17 As shown, a pump light reflector stack 180 can be provided over some of the LED sub-pixels of each monolithic LED pixel 1. The pump light reflector stack can be provided over the container volume of an LED sub-pixel that includes the first and / or second color conversion layer 160, 161. The pump light reflector stack can be configured to absorb pump light of the first wavelength and to transmit light of wavelengths having the first and / or second color conversion wavelength. Effectively, the pump light reflector stack is a band reject filter configured to have a narrow wavelength rejection band including the first wavelength, and a passband including the first and / or second conversion light wavelength.

[0163] One example of a suitable pump light reflector stack can be a distributed Bragg reflector. An example of a suitable distributed Bragg reflector can be found in US 11 / 508,166. Of course, it will be appreciated that for LED sub-pixels that do not include a color conversion layer (i.e. LED sub-pixels that emit the first wavelength, the pump light reflector stack can not be provided over said LED sub-pixels). In Figure 17 In embodiments, one pump light reflector stack 180 is provided across the container volume 151 that includes the first and second color conversion layers 160, 161. For example, in Figure 17 In embodiments, the pump light reflector stack can include alternating layers of Ti02 (index of refraction of approximately 2.6) and Si02 (index of refraction of approximately 1.5). In other embodiments, a different pump light reflector stack can be provided for each container volume 151.

[0164] After the light extraction features are formed, the sacrificial dielectric layer 121 can be selectively removed in order to separate each monolithic LED pixel 1 from the test substrate 200. For example, as shown in Figure 18 As shown, the sacrificial dielectric layer 121 has been selectively removed. According to the fabrication method of the first embodiment, the sacrificial test dielectric layer 206 has also been selectively removed. The etch stop layer 119 and the test etch stop layer 207 provide a surface upon which the selective removal process can more reliably terminate to protect other layers of the monolithic LED pixel 1 and the test substrate 200.

[0165] It will be appreciated that after removal of the sacrificial dielectric layer 121, each monolithic LED pixel includes a light emission surface 130 and a planarized dielectric surface 217. The light emission surface 130 and the planarized dielectric surface are separated by sidewalls defined by the planarized dielectric layer, the common semiconductor layer, and sidewall surfaces of the sacrificial substrate. These sidewall surfaces are formed as a result of previous etching processes performed during the method of forming the monolithic LED pixel 1. Thus, the planarized dielectric layer, the common semiconductor layer, and the sacrificial substrate define etched sidewalls around the light emission surface for each monolithic LED pixel 1.

[0166] As shown, after removal of the sacrificial dielectric layer 121, the monolithic LED pixel 1 can still be connected to the test substrate by the plurality of conductive contacts 208. It will be appreciated that the connection between the conductive contacts 208 and each monolithic LED sub-pixel 103 can be relatively weak. Thus, as shown, the monolithic LED sub-pixels 103 can each be peeled away from the test substrate, causing the contact between the conductive contacts 208 and the monolithic LED pixel 1 to break. For example, a pick-and-place machine can sequentially remove each monolithic LED pixel 1. After removal of the sacrificial dielectric layer 121, the spacing between each monolithic LED pixel 1 can provide space for the pick-and-place machine to more easily manipulate each monolithic LED pixel 1. Figure 18 Figure 18 It will be appreciated that after removal of the sacrificial dielectric layer 121, each monolithic LED pixel includes a light emission surface 130 and a planarized dielectric surface 217. The light emission surface 130 and the planarized dielectric surface are separated by sidewalls defined by the planarized dielectric layer, the common semiconductor layer, and sidewall surfaces of the sacrificial substrate. These sidewall surfaces are formed as a result of previous etching processes performed during the method of forming the monolithic LED pixel 1. Thus, the planarized dielectric layer, the common semiconductor layer, and the sacrificial substrate define etched sidewalls around the light emission surface for each monolithic LED pixel 1.

[0167] Thus, according to the first embodiment of the present disclosure, a monolithic LED pixel 1 is provided. The LED pixel 1 includes a sacrificial substrate 101, a common semiconductor layer 102, an array of LED sub-pixels, and a planarized dielectric layer. The common semiconductor layer 102 includes Ill-nitride disposed on the sacrificial substrate 101. The array of LED sub-pixels is disposed on a surface of the common semiconductor layer 102 on an opposite side of the common semiconductor layer 102 from the sacrificial substrate 101. Each LED sub-pixel of the array of LED sub-pixels includes a stack of Ill-nitride layers. The planarized dielectric layer provided on the array of LED sub-pixels provides a planarized dielectric surface 217 that is generally aligned with the surface of the common semiconductor layer 102. The planarized dielectric layer, the common semiconductor layer 102, and the sacrificial substrate 101 define etched sidewalls around a light emission surface of the monolithic LED sub-pixel 103. The monolithic LED pixel 1 further includes a light extraction feature that includes a first opening provided through a thickness of the sacrificial substrate that is aligned with each LED sub-pixel.​

[0168] An example of a monolithic LED pixel 1 according to the first embodiment is shown in Figure 1 and Figure 2 . A cross-section of the monolithic LED pixel 1 along line A-A’ is shown in Figure 19 . Further features of the monolithic LED pixel 1 will be apparent from the functions of the various layers discussed above for the method of forming the monolithic LED pixel 1 of the first embodiment.

[0169] Next, a description of the method of forming the monolithic LED pixel 1 according to the first embodiment will be provided with reference to a cross-section along line B-B’ shown in Figure 2 .

[0170] As shown in the plan view of Figure 2 , the monolithic LED pixel 1 comprises four contact metallisations 117. Three of the contact metallisations 117 are anode contact metallisations A R , A G , A B , one for each of the three LED sub-pixels 103. Thus, Figure 2 , the monolithic LED pixel 1 shown in comprises one anode contact metallisation A R , A G , A B for each of the red, green and blue LED sub-pixels R, G, B. Each anode contact metallisation A R , A G , A B is configured to form an electrical connection to a respective anode of the three LED sub-pixels 103 R, G, B.

[0171] Furthermore, as shown in Figure 2 , the monolithic LED pixel 1 comprises a common cathode contact metallisation C C . The common cathode contact metallisation C C is configured to provide an electrical connection to each cathode of the LED sub-pixels 103. Thus, the common cathode contact metallisation C C may be provided with a single contact point to the common semiconductor layer 102, or in some embodiments, such as in the first embodiment, multiple contact points to the common semiconductor layer. Thus, the monolithic LED pixel 1 can provide a common cathode contact metallisation C C and anode contact metallisations A R , A G , A B for each LED sub-pixel, such that each of the LED sub-pixels R, G, B can be controlled independently of the other LED sub-pixels R, G, B.

[0172] As shown in Figure 2The contact metallization C C The contact metallization C R The contact metallization C G The contact metallization C B The contact metallization C C The contact metallization C Figure 2 An example of this arrangement will now be described with reference to a cross-section along line B-B’ shown in

[0173] Figure 20 An intermediate step in the method of forming the first embodiment of the disclosure along line B-B’ is shown. As Figure 20 indicated, a sacrificial substrate 101 is provided. A common semiconductor layer 102 is provided on the sacrificial substrate 101. A plurality of LED sub-pixels 103 are then formed on the common semiconductor layer 102. Thus, Figure 20 The schematic diagram shown is an alternative view of the schematic diagram shown in the first embodiment of the disclosure. As Figure 4 can be seen, Figure 20 and Figure 1 LED sub-pixels 103 shown have a different surface area to other LED sub-pixels 103 of the monolithic LED pixel 1. For example, Figure 20 The surface area of the LED sub-pixel G shown is at least twice the surface area of the other LED sub-pixels R, B of the monolithic LED pixel 1. The increase in surface area of the LED sub-pixel G is provided by elongating one dimension of the LED sub-pixel G relative to the other LED sub-pixels R, B in alignment with the common semiconductor surface 102. That is, Figure 20 The LED sub-pixels 103 shown have a different size to other LED sub-pixels 103 forming the monolithic LED pixel 1. In the first embodiment, the LED sub-pixel 103 configured to output substantially green visible light, 103G, is provided as the largest of the three LED sub-pixels 103. Figure 20

[0174] Next, as shown in Figure 21 a plurality of first contact layers 106 are formed on the common semiconductor layer 102 in the region between the LED sub-pixels 103. The first contact layers 106 are configured to provide an electrical connection to the common semiconductor layer 102. As Figure 21 indicated, the plurality of first contact layers are provided on either side of the LED sub-pixels 103.

[0175] ​In addition, a first passivation layer 107 is formed over the plurality of LED sub-pixels 103. A plurality of first openings 141 are formed in the first passivation layer 107 aligned with each of the first contact layers 106. A cathode contact layer 109 is then formed within the first openings 141 of the first passivation layer 107. Thus, the cathode contact layer 109 is disposed on each of the first contact layers 106. A plurality of second openings 142 are also formed in the first passivation layer 107. Each of the second openings is aligned with one of the LED sub-pixels 103. An anode contact layer 108 is formed in the plurality of second openings 142 to form an electrical connection to the anode of each LED sub-pixel 103. Thus, Figure 21 The intermediate structure shown in Figure 5 An alternative view of the intermediate structure shown.

[0176] After forming the cathode contact layer 109 and the anode contact layer 108, a planarization dielectric layer is formed. As described above, part of the process of forming the planarization dielectric layer includes forming contact metallization 117 to allow electrical connections to be made to each LED sub-pixel 103 of each monolithic LED pixel 1. Figure 22 As shown in FIG, the planarization dielectric layer can be composed of multiple passivation layers. Figure 22 As shown, a second passivation layer 112 is formed over the array of LED sub-pixels 103. A plurality of third openings 143 may then be formed in the second passivation layer 112 to allow for the formation of a first contact metallization 114 to form electrical connections to the anode contact layer 108 and the cathode contact layer 109. Figure 22 As shown, a plurality of first contact metallizations 114 are disposed in the third openings 143. Figure 22 As shown, a plurality of first contact metallizations 114 extend through the second passivation layer 112 to the anode contact layer 108 , and another first contact metallization layer 114 extends through the second passivation layer 112 to the cathode contact layer 109 .

[0177] Next, if Figure 23 As shown, a third passivation layer 115 is formed over the second passivation layer 112. A fourth opening 144 is formed in the third passivation layer 115. The fourth opening 144 defines an area of ​​the third passivation layer where a second contact metallization 117 for each electrical contact to each LED sub-pixel 103 and the common cathode will be provided. Figure 23 In the embodiment shown, the common cathode contact metallization C C The fourth opening 144 of the third passivation layer 115 is provided to overlap the LED sub-pixel 103 in a plane perpendicular to the common semiconductor layer 102. By providing a common cathode contact metallization C that overlaps one or more LED sub-pixels C, a common cathode contact metallization can be provided in a more space-saving manner within a monolithic LED pixel 1. That is, the common cathode contact metallization C C Overlapping with a portion of the light emitting surface of the monolithic LED pixel 1. Thus, the cathode contact metallization C C A greater proportion of the light emitting surface 130 of the monolithic LED pixel is occupied by the light emitting element of each LED sub-pixel than the non-emitting surface portion providing space.

[0178] Also like Figure 23 As shown, an anode contact metallization layer A is provided in another fourth opening 144. G To form a Figure 23 The anode of the LED sub-pixel G shown in FIG is contacted with the metallization layer. Thus, a first electrical contact is provided for each LED sub-pixel. Figure 23 As shown, each LED sub-pixel is provided with an anode first electrical contact for each monolithic LED pixel and a common cathode first electrical contact. Of course, in other embodiments, the number of first electrical contacts will depend on the specific characteristics of the monolithic electronic device.

[0179] It should be understood that, when observing along line BB', Figure 23 The structure shown is consistent with the present disclosure Figure 9 Thus, it will be appreciated that the third passivation layer 115 and the cathode and anode contact metallizations form a planarized dielectric surface for the monolithic LED pixel 1 .

[0180] After forming the anode and cathode contact metallizations, the method of forming the monolithic LED pixel 1 continues as described above with respect to Figure 10 and Figure 11 As described. Therefore, Figure 24 As shown, pixel definition grooves 118 are formed. Figure 25 In the embodiment, an etch stop layer 119 and a sacrificial dielectric layer 121 are formed over the pixel defining trench 118 and the planarization dielectric layer to form the above-described Figures 3 to 11 An intermediate array 100 of LED sub-pixels is depicted.

[0181] Next, the intermediate array of LED sub-pixels 100 is bonded to a test substrate 200 as described above. Figure 27 A cross section of a test substrate 200 is shown, corresponding to a portion of the test substrate to be aligned with line BB' of a monolithic LED pixel 1. Thus, the test substrate 200 comprises an electronic substrate 201 and a plurality of electronic layers 202, 203, 204, 205. In a first embodiment, the test substrate 200 further comprises a test etch stop layer 207 and a sacrificial test dielectric layer 206.

[0182] like Figure 27As shown in FIG, the test substrate 200 is configured to test each monolithic LED pixel 1. Figure 27 As shown in FIG, multiple electronic layers 202, 203, 204, 205 are arranged to provide contact with the anode metallization A R 、A G 、A B and cathode contact metallization C C electrical connections.

[0183] For example, the test substrate 200 includes a first conductive layer 203 and a second conductive layer 205. Each conductive layer may include a conductive material, for example, a metal such as gold, aluminum, copper, or the like.

[0184] The test substrate may also include a first insulating layer 202 and a second insulating layer 204. The first and second insulating layers 202, 204 may include any suitable dielectric material, such as silicon dioxide. The first insulating layer 202 may provide a surface on which a first conductive layer 203 may be disposed. A second insulating layer 204 may then be provided over the first conductive layer 203 to encapsulate the first conductive layer 203. A second conductive layer 205 may then be formed over the second insulating layer 204. Thus, the stack of electronic layers 202, 203, 204, 205 may be formed to form an anode contact metallization A to the middle array of LED sub-pixels. R 、A G 、A B and cathode contact metallization C C Each of the plurality of electronic layers 202, 203, 204, 205 of the test substrate 200 can be configured to provide an electrical test circuit for each LED sub-pixel, and each LED sub-pixel can be bonded to the intermediate array of LED sub-pixels 100. That is, when the test substrate is bonded to the intermediate array of LED sub-pixels 100, the plurality of electronic layers 202, 203, 204, 205 are configured to provide power to each LED sub-pixel 103.

[0185] like Figure 27 As shown, a plurality of seventh openings 212 are formed in the test substrate surface 210 corresponding to the anode contact metallization A. R 、A G 、A B and cathode contact metallization C C A plurality of conductive contacts 208 are then formed within each seventh opening 212 of the test substrate 200 .

[0186] As described above, the intermediate array of LED sub-pixels 100 is configured to be bonded to the test substrate 200. A view of the intermediate array of LED sub-pixels 100 and the test substrate 200 bonded together along line BB' is shown in FIG. Figure 28 Therefore, from Figure 28 It can be understood that the cathode contact layer 109 is formed by the cathode contact metallization C C The anode contact layer 108 of the LED sub-pixel G is electrically connected to the first conductive layer 203 of the test substrate. G The second conductive layer 205 is electrically connected to the test substrate.

[0187] After the intermediate array of LED sub-pixels 100 is bonded to the test substrate 200, the light emitting surface 130 of the intermediate array of LED sub-pixels 100 may be further processed to form light extraction features. Figure 29 As shown, a container volume 151 is formed in the sacrificial substrate 101. The container volume 151 is filled with a first color conversion material 160, and a pump light reflector 180 is disposed above the container volume 151. In this way, Figure 29 The structure shown is Figure 17 Different views of the structure shown.

[0188] Finally, for example Figure 30 As shown, each monolithic LED pixel 1 can be removed from the test substrate 200, for example, using a mass transfer pick-and-place machine.

[0189] Before removing the sacrificial dielectric layer 121 and releasing each monolithic LED pixel 1 from the test substrate 200, each LED subpixel can be tested. As part of the testing process, the first and second conductive layers 203, 205 of the test substrate can be connected to a power source. Thus, a voltage can be applied across the first and second conductive layers 203, 205 to drive current through each LED subpixel in the intermediate array of LED subpixels 100. According to a first embodiment, the testing process is configured to simultaneously turn on each LED in the intermediate array of LED subpixels. A test analysis device, such as a camera or other light-sensitive sensor, can then detect light emitted from the LED subpixels in the intermediate array of LED subpixels 100. The information recorded by the test analysis device (e.g., images recorded by the camera) can then be used by a processor to determine whether any LED subpixels 103 are inoperative. Any monolithic LED pixels 1 in the intermediate array 100 identified as containing one or more inoperative LED subpixels 103 can be identified and not used in any subsequent pick-and-place processes. Thus, the test substrate 200 allows for parallel testing of an array of monolithic LED pixels 1. Such a parallel testing process is more efficient than testing each monolithic LED pixel 1 after removal from the test substrate 200. Therefore, the parallel testing process of each monolithic LED pixel 1 can be integrated into the method of manufacturing the monolithic LED pixels 1.

[0190] Of course, it should be understood that the present disclosure is not limited to the above-described testing process. For example, in some embodiments, the test substrate can be configured to independently test each monolithic electronic device. In some embodiments, the testing process can involve confirming that an expected amount of current flows through each monolithic electronic device when a predetermined voltage is applied. Thus, the testing procedure can be performed at any time after the test substrate 200 is bonded to the intermediate array of LED sub-pixels.

[0191] like Figure 30 As shown, after the monolithic LED pixel 1 is removed from the test substrate 20, the test circuitry of the test substrate 200 remains substantially unchanged. Therefore, the test substrate 200 can be reused in further fabrication processes for the monolithic LED pixel 1. In some embodiments, the test substrate 200 includes a surface for bonding a sacrificial test dielectric layer to the intermediate array of LED sub-pixels 100. The sacrificial test dielectric layer may need to be re-formed on the test substrate 200 before it is reused.

[0192] Thus, a monolithic LED pixel 1 according to a first embodiment of the present disclosure is provided. In some embodiments, each monolithic LED pixel can be a monolithic micro-LED pixel. Thus, each LED sub-pixel can be a micro-LED sub-pixel having a size no greater than 100 μm × 100 μm. In some embodiments, the surface area of ​​each LED sub-pixel on the common semiconductor layer can define an area no greater than 100 μm × 100 μm. In some embodiments, the surface area of ​​each LED sub-pixel on the common semiconductor layer can define an area no greater than: 50 μm × 50 μm, 30 μm × 30 μm, 20 μm × 20 μm, or 10 μm × 10 μm.

[0193] Although preferred embodiments of the present invention have been described in detail herein, those skilled in the art will appreciate that changes may be made thereto without departing from the scope of the invention or the appended claims.

Claims

1. A method of forming and testing a plurality of monolithic electronic devices, the method comprising: a) Forming a monolithic electronic device array, comprising: forming a common semiconductor layer comprising a Group III nitride on a sacrificial substrate; forming a monolithic electronic device array on a surface of the common semiconductor layer on a side of the common semiconductor layer opposite to the sacrificial substrate, each monolithic electronic device of the monolithic electronic device array comprising a plurality of Group III nitride layers; forming a planarized dielectric layer over the monolithic array of electronic devices to provide a planarized dielectric surface, the planarized dielectric surface being substantially aligned with a surface of the common semiconductor layer; forming a trench grid by etching the planarized dielectric layer and the common semiconductor layer from the planarized dielectric surface to the sacrificial substrate, wherein the trench grid surrounds each of the monolithic electronic devices; forming a first electrical contact to each of said monolithic electronic devices through said planarized dielectric layer, forming a sacrificial dielectric layer over the trench grid and the planarized dielectric surface of the planarized dielectric layer to form a first bonding surface substantially aligned with a surface of the common semiconductor layer, wherein the first bonding surface includes a first aperture aligned with each of the first electrical contacts; b) Setting up a test substrate, including: an electronic substrate comprising an electronic test circuit configured to provide power to each of said monolithic electronic devices of said array of monolithic electronic devices; and a plurality of second electrical contacts arranged on the electronic substrate to correspond to the arrangement of the first electrical contacts of the monolithic electronic device array; wherein a bonding dielectric layer is formed on the electronic substrate to provide a second bonding surface, the second bonding surface including a second hole aligned with each of the second electrical contacts; c) aligning the second electrical contact of the test substrate with the first electrical contact of the monolithic electronic device array and bonding the second bonding surface of the test substrate to the first bonding surface of the sacrificial dielectric layer such that the first electrical contact and the second electrical contact are in electrical contact; d) supplying power from the test substrate to the array of monolithic electronic devices to test each monolithic electronic device of the array of monolithic electronic devices through a plurality of the first electrical contacts and the second electrical contacts; and e) selectively removing a first portion of the sacrificial substrate through a thickness of the sacrificial substrate to separate each of the monolithic electronic devices from adjacent monolithic electronic devices; and The sacrificial dielectric layer is removed to separate each of the monolithic electronic devices from the test substrate.

2. The method according to claim 1, wherein The bonding dielectric layer is a sacrificial bonding dielectric layer, wherein the sacrificial bonding dielectric layer is configured to be selectively removed along with the sacrificial dielectric layer to separate each of the monolithic electronic devices from the test substrate.

3. The method according to claim 1 or 2, wherein: After removing the sacrificial dielectric layer to separate each of the monolithic electronic devices from the test substrate, the test substrate is reused in a method of forming and testing a plurality of monolithic devices.

4. The method according to claim 1, wherein The electronic test circuitry of the test substrate is configured to supply power in parallel to each of the monolithic electronic devices.

5. The method according to claim 1, wherein Each of the monolithic electronic devices in the array of monolithic electronic devices includes a light emitting diode (LED).

6. The method according to claim 1, wherein Each monolithic electronic device is a monolithic light emitting diode (LED) pixel located on a surface of the common semiconductor layer, the monolithic light emitting diode (LED) pixel comprising a plurality of LED sub-pixels, each of the LED sub-pixels comprising a stack of Group III nitride layers.

7. The method according to claim 6, wherein: After bonding the test substrate to the monolithic electronic device array, the method includes: Forming light extraction features for each of the monolithic light emitting diode (LED) pixels includes selectively removing a second portion of the sacrificial substrate aligned with each of the LED sub-pixels.

8. The method according to claim 7, wherein The light extraction features forming each of the monolithic light emitting diode (LED) pixels include: selectively removing a second portion of the sacrificial substrate aligned with each of the LED sub-pixels to form a container volume for each of the LED sub-pixels; and A first color conversion layer is provided in at least one of the container volumes of each of the monolithic light emitting diode (LED) pixels, the first color conversion layer being configured to absorb light having a first wavelength and emit converted light having a first converted light wavelength longer than the first wavelength.

9. The method according to claim 8, wherein The first converted light has a wavelength of at least 500 nm.

10. The method according to claim 8, wherein The first converted light has a wavelength of no greater than 650 nm.

11. The method according to claim 8, wherein A second color conversion layer is disposed in at least another of the container volumes of each of the monolithic light emitting diode (LED) pixels, the second color conversion layer being configured to absorb light having a first wavelength and emit converted light having a second converted light wavelength longer than the first converted light wavelength.

12. The method according to any one of claims 6 to 11, wherein Each of the LED sub-pixels is configured to generate light having a first wavelength of at least 380 nm.

13. The method according to any one of claims 6 to 11, wherein Each of the LED sub-pixels is configured to generate light having a first wavelength no greater than 490 nm.

14. The method according to any one of claims 6 to 11, wherein The surface area of ​​each of the LED sub-pixels on the common semiconductor layer is defined as an area no greater than 100 μm×100 μm.

15. A monolithic device array comprising: sacrificial substrate; a common semiconductor layer, disposed on the sacrificial substrate, comprising a Group III nitride; a monolithic electronic device array disposed on a surface of the common semiconductor layer on a side of the common semiconductor layer opposite to the sacrificial substrate, each monolithic electronic device of the monolithic electronic device array comprising a plurality of Group III nitride layers; a planarized dielectric layer disposed on the monolithic array of electronic devices to provide a planarized dielectric surface aligned with the surface of the common semiconductor layer, wherein The planarized dielectric layer defines a grid of trenches extending from the planarized dielectric surface to the sacrificial substrate, wherein the grid of trenches surrounds each monolithic electronic device; a first electrical contact for each monolithic electronic device, the first electrical contact extending from each monolithic electronic device to the planarized dielectric surface; and A sacrificial dielectric layer is disposed within the trench grid and over the planarized dielectric surface of the planarized dielectric layer to provide a first bonding surface substantially aligned with the surface of the common semiconductor layer, wherein the first bonding surface includes a first aperture aligned with each of the first electrical contacts.

16. The monolithic device array of claim 15, wherein Each monolithic electronic device of the array of monolithic electronic devices includes a light emitting diode (LED).

17. A monolithic device array according to claim 15 or 16, wherein Each monolithic electronic device is a monolithic light emitting diode (LED) pixel located on the surface of the common semiconductor layer, the monolithic light emitting diode (LED) pixel comprising a plurality of LED sub-pixels, each of the LED sub-pixels comprising a stack of Group III-nitride layers.

18. A test substrate for bonding the monolithic device array according to any one of claims 15 to 17, comprising: an electronic substrate comprising an electronic test circuit configured to provide power to each of said monolithic electronic devices of said array of monolithic electronic devices; a plurality of second electrical contacts arranged on the electronic substrate to correspond to the arrangement of the first electrical contacts of the monolithic electronic device array; and A bonding dielectric layer is formed on the electronic substrate to provide a second bonding surface including a second aperture aligned with each of the second electrical contacts.

19. The test substrate according to claim 18, wherein The bonding dielectric layer is a sacrificial bonding dielectric layer, wherein the sacrificial bonding dielectric layer is configured to be selectively removed along with the sacrificial dielectric layer to separate each monolithic electronic device from the test substrate.

20. The test substrate according to claim 19, wherein The sacrificial bonding dielectric layer is configured to be selectively removed such that the test substrate is reused for bonding to a monolithic electronic device.

21. The test substrate according to any one of claims 18 to 20, further comprising: An etch stop layer is disposed between the bonding dielectric layer and the electronic substrate.

22. The test substrate according to any one of claims 18 to 20, wherein The electronic test circuitry of the test substrate is configured to supply power in parallel to each of the monolithic electronic devices.

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