Method for realizing qspi function based on cpu-based gpio pin simulation

Abstract

The application discloses a method for realizing QSPI function based on CPU GPIO pin simulation, and comprises the following steps: S1, simulating QSPI pin through CPU GPIO pin; S2, communicating with a slave according to the CPU simulated QSPI pin. The method for realizing QSPI function based on CPU GPIO pin simulation provided by the application realizes QSPI function on a CPU without supporting QSPI only by using six GPIO pins, and has simple structure, easy realization and low cost. Compared with SPI, the QSPI has four data lines and realizes bidirectional transmission, while the SPI has only two data lines, so that the transmission efficiency is greatly improved. The method is also compatible with the function of simulating SPI communication through GPIO.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of embedded driving, and particularly relates to a method for realizing QSPI function based on CPU GPIO pin simulation. BACKGROUND

[0002] QSPI (Queued Serial Peripheral Interface) is an extension of SPI interface, and has a queue transmission mechanism and bidirectional data line on the basis of SPI protocol. QSPI is a special communication interface, and is connected with single, double or four SPI Flash storage media. In embedded system processors, a considerable part of processors do not have SPI interface, and if the number of processors is simply expanded, space layout difficulty will be caused. SUMMARY

[0003] In view of the above problems in the prior art, the method for realizing QSPI function based on CPU GPIO pin simulation provided by the application solves the problem that it is difficult to realize QSPI function on a CPU which does not support QSPI function.

[0004] In order to achieve the above-mentioned application purposes, the technical scheme adopted by the application is as follows: the method for realizing QSPI function based on CPU GPIO pin simulation comprises the following steps:

[0005] S1, simulating QSPI pins through GPIO pins of a CPU;

[0006] S2, communicating with a slave according to the QSPI pins simulated by the CPU.

[0007] Further, the S1 is specifically as follows:

[0008] Four GPIO pins are set to simulate data transmission signal IO0-IO3 pins in QSPI pins, one GPIO pin is set to simulate chip selection signal CS pin in QSPI pins, and one GPIO pin is set to simulate clock signal SCLK pin in QSPI pins.

[0009] Further, in the S2, the communication between the CPU and the slave is specifically as follows:

[0010] S21, communication transmission preparation stage;

[0011] S22, communication transmission stage;

[0012] S23, communication transmission end stage.

[0013] Further, the S21 is specifically as follows:

[0014] The chip select signal CS pin is pulled low to an active level, and the sampling level of the clock signal SCLK pin is determined according to the data transmitted in communication.

[0015] Further, the S22 comprises the following steps:

[0016] S221, transmitting address / command sub-stage;

[0017] S222, after completing the address / command, entering the no-operation sub-stage;

[0018] S223, after the no-operation sub-stage ends, performing the data transmission sub-stage, and completing the communication transmission stage.

[0019] Further, the S221 is specifically:

[0020] The CPU sets the output signal of the transmission signal IO0-IO3 pin, sets the first active level of the transmission address / command, sets the clock signal SCLK pin to be the non-first active level, and prepares the address / command to be sent through the transmission signal IO0-IO3 pin; the clock signal SCLK pin is set to the first active level, and the transmission signal IO0-IO3 pin is used to send the address / command to be transmitted to the slave;

[0021] After the transmission signal IO0-IO3 pin sends all the address / command, the clock signal SCLK pin is set to the non-first active level, and the transmission address / command sub-stage ends.

[0022] Further, the S222 is specifically:

[0023] After completing the address / command, the CPU sets the clock signal SCLK pin to high and low values for 1-31 times, and enters the no-operation sub-stage.

[0024] Further, in the S223, the data transmission sub-stage is specifically the CPU receiving data mode and the CPU sending data mode.

[0025] The CPU sending data mode is specifically:

[0026] The CPU sets the output signal of the transmission signal IO0-IO3 pin, sets the second active level of the transmission data, sets the clock signal SCLK pin to be the non-second active level, and prepares the data to be sent through the transmission signal IO0-IO3 pin; the clock signal SCLK pin is set to the second active level, and the transmission signal IO0-IO3 pin is used to send the data to be transmitted to the slave, and after the data transmission is completed, the communication transmission stage is completed.

[0027] The CPU receiving data mode is specifically:

[0028] The input signal is set through the CPU to the transmission signal IO0-IO3 pin, the third active level of the transmission data is set, when the clock signal SCLK pin is the third active level, the data transmitted by the slave is received through the transmission signal IO0-IO3 pin, and after the data transmission is completed, the communication transmission phase is completed.

[0029] Further, the S23 is specifically:

[0030] The chip selection signal CS pin and the clock signal SCLK pin are pulled high.

[0031] The beneficial effects of the present application are:

[0032] (1) The method for simulating QSPI function based on GPIO pin of CPU provided by the present application only needs 6 GPIO pins to realize QSPI function on a CPU that does not support QSPI, and has simple structure, easy realization and low cost.

[0033] (2) Compared with SPI, the data line of QSPI has 4 roots and is bidirectional transmission, while the SPI only has 2 data lines, which greatly improves the transmission efficiency. The method of the present application also compatible with the function of simulating SPI communication through GPIO. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 The flow chart of the method for simulating QSPI function based on GPIO pin of CPU.

[0035] Figure 2 The system principle block diagram of the method for simulating QSPI function based on GPIO pin of CPU in the embodiment of the present application.

[0036] Figure 3 The QSPI read timing waveform schematic diagram in the embodiment of the present application. DETAILED DESCRIPTION

[0037] The specific embodiments of the present application are described below, so that those skilled in the art can understand the present application, but it should be clear that the present application is not limited to the scope of the specific embodiments, and for those skilled in the art, it is obvious that various changes are within the spirit and scope of the present application defined and determined by the appended claims, and all the inventions utilizing the concept of the present application are within the scope of protection.

[0038] Embodiment 1:

[0039] The CPU of the host is A, the FLASH of the slave is B, and A reads a byte data 0x8a from the 16-bit address / command 0x1234 of B.

[0040] AsFigure 1 As shown in one embodiment of the application, the method for simulating QSPI function based on CPU GPIO pin includes the following steps:

[0041] S1, simulating QSPI pin through GPIO pin of CPU;

[0042] S2, communicating with slave according to the QSPI pin simulated by CPU.

[0043] The S1 is specifically:

[0044] Four GPIO pins are set to simulate data transmission signal IO0-IO3 pins in QSPI pin, one GPIO pin is set to simulate chip selection signal CS pin in QSPI pin, and one GPIO pin is set to simulate clock signal SCLK pin in QSPI pin.

[0045] In this embodiment, GPIO0 pin simulates data transmission signal IO0 pin, GPIO1 pin simulates data transmission signal IO1 pin, GPIO2 pin simulates data transmission signal IO2 pin, GPIO3 pin simulates data transmission signal IO3 pin, GPIO4 pin simulates data transmission signal SCLK pin, GPIO5 pin simulates data transmission signal CS pin, and the simulated data transmission signal IO0-IO3 pins are bidirectional transmission, the chip selection signal CS pin and the clock signal SCLK pin are both output signal pins; the CPU is the host and the FLASH is the slave.

[0046] In the S2, the communication between the CPU and the slave is specifically:

[0047] S21, communication transmission preparation stage;

[0048] S22, communication transmission stage;

[0049] S23, communication transmission end stage.

[0050] The S21 is specifically:

[0051] The chip selection signal CS pin is pulled low to become an effective level, and the sampling level of the clock signal SCLK pin is determined according to the data of the communication transmission.

[0052] In this embodiment, in the transmission preparation stage, the GPIO5 (CS) pin is pulled low, and is determined as a low-level sampling.

[0053] The S22 includes the following sub-steps:

[0054] S221, transmission address / command sub-stage;

[0055] S222, after the address / command is completed, entering the null instruction sub-stage;

[0056] S223, after the null instruction sub-stage is ended, the data transmission sub-stage is performed, and the communication transmission stage is completed.

[0057] The S221 is specifically:

[0058] The output signal is set through the CPU setting transmission signal IO0-IO3 pin, the first active level of the transmission address / command is set, the clock signal SCLK pin is set as the non-first active level, and the address / command to be sent is prepared through the transmission signal IO0-IO3 pin; the clock signal SCLK pin is set as the first active level, and the address / command to be transmitted is sent to the slave through the transmission signal IO0-IO3 pin.

[0059] When the transmission signal IO0-IO3 pin sends all the address / command, the clock signal SCLK pin is set as the non-first active level, and the transmission address / command sub-stage is ended.

[0060] In the embodiment, as shown in Figure 2 The 1-4 byte address is sent to the FLASH. In this stage, the address transmission is performed by 4 IOs in the general FLASH, and when the GPIO is simulated, the GPIO4 output is high, the GPIO3-0 is used as the output pin, and the address high 4 bits are output respectively, the highest bit is placed in the GPIO3, the GPIO4 output is low, and then the other bits of the address are transmitted by the GPIO4 and the GPIO3-0 until the bit0. In a clock cycle, 4 bits of the address are transmitted each time, when the address is 16 bits, 4 clock cycles are needed, and the sequentially transmitted address is addr15-12…addr3-0.

[0061] Step 1: the CPU host A sets the GPIO0(IO0)-GPIO3(IO3) direction as output;

[0062] Step 2: according to the address 0x1234, the highest 4 bits are all b’0001, the GPIO4(SCLK) is pulled high, the GPIO3(IO3)-GPIO0(IO0) are pulled low, and then the GPIO4(SCLK) is pulled low;

[0063] Step 3: the GPIO4(SCLK) is pulled high, 0x2(b’0010) of the address 0x1234 is transmitted, the GPIO3(IO3) is pulled low, the GPIO2(IO2) is pulled low, the GPIO1(IO1) is pulled high, the GPIO0(IO0) is pulled low, and finally the GPIO4(SCLK) is pulled low;

[0064] Step4: pull up GPIO4 (SCLK), transmit 0x3 (b'0011) of address 0x1234, pull down GPIO3 (IO3), pull down GPIO2 (IO2), pull up GPIO1 (IO1), pull up GPIO0 (IO0), and finally pull down GPIO4 (SCLK);

[0065] Step5: pull up GPIO4 (SCLK), transmit 0x4 (b'0100) of address 0x1234, pull down GPIO3 (IO3), pull up GPIO2 (IO2), pull down GPIO1 (IO1), pull down GPIO0 (IO0), and finally pull down GPIO4 (SCLK);

[0066] The S222 is specifically:

[0067] After completing the address / command, the clock signal SCLK pin is set to 1-31 high-low values by the CPU to enter the empty instruction sub-stage.

[0068] In the present embodiment, if data is received from the FLASH, a certain empty instruction needs to be set for the data preparation of the FLASH. The CPU host A completes the empty instruction stage by pulling up and then pulling down GPIO4 (SCLK) multiple times;

[0069] In the S223, the data transmission sub-stage is specifically the CPU receiving data mode and the CPU sending data mode.

[0070] The CPU sending data mode is specifically:

[0071] The output signal is set through the CPU setting the data transmission signal IO0-IO3 pin, the second active level of the transmission data is set, the clock signal SCLK pin is set to the non-second active level, and the data to be sent is prepared through the transmission signal IO0-IO3 pin; the clock signal SCLK pin is set to the second active level, and the data to be transmitted is sent to the slave through the transmission signal IO0-IO3 pin. After the data transmission is completed, the communication transmission stage is completed.

[0072] The CPU receiving data mode is specifically:

[0073] The input signal is set through the CPU setting the data transmission signal IO0-IO3 pin, the third active level of the transmission data is set, and the data transmitted by the slave is received through the transmission signal IO0-IO3 pin when the clock signal SCLK pin is in the third active level. After the data transmission is completed, the communication transmission stage is completed.

[0074] For data transmission, first set IO0-IO3 as output signals. If it is low level sampling, first pull up SCLK, and then prepare data on IO0-IO3, and then pull down SCLK. Repeat pulling up SCLK, preparing data, and pulling down SCLK until the data transmission is completed. If it is high level sampling, first pull down SCLK, and then prepare data on IO0-IO3, and then pull up SCLK. Repeat pulling down SCLK, preparing data, and pulling up SCLK until the data transmission is completed.

[0075] For data reception, first set IO0-IO3 as input signals. If it is low level sampling, first pull up SCLK, and then pull down SCLK, and then take out the data of IO0-IO3. Repeat pulling up SCLK, pulling down SCLK, and taking out data until the data is taken out.

[0076] In the embodiment, any number of bytes can be received from or sent to the Flash during the data access operation. According to the operation type, any byte of data is sent to the CPU or any byte of data is received from the CPU until the from-device enable signal CS is low, and the QSPI timing is ended. When data is sent from the Flash, the data is sent in combination with the change of the GPIO5 (SCLK) signal. When data is received from the Flash, GPIO3-0 need to be set as input signals, and the data is taken out in combination with the change of the GPIO5 (SCLK) signal.

[0077] Step 1: The CPU host A sets the directions of GPIO0 (IO0)-GPIO3 (IO3) as input.

[0078] Step 2: The CPU host A pulls up GPIO4 (SCLK) and pulls down GPIO4 (SCLK), and collects the data of GPIO3 (IO3)-GPIO0 (IO0) to obtain the highest 4 bits as b'1000.

[0079] Step 3: The CPU host A pulls up GPIO4 (SCLK) and pulls down GPIO4 (SCLK), and collects the data of GPIO3 (IO3)-GPIO0 (IO0) to obtain the highest 4 bits as b'1010.

[0080] Step 4: The obtained data is preferably 0x8a.

[0081] The S23 specifically comprises:

[0082] The chip selection signal CS pin and the clock signal SCLK pin are pulled up.

[0083] In the embodiment, GPIO5 (CS) is pulled up, and the QSPI cycle is ended.

[0084] AsFigure 3 As shown, by the embodiment of the application, the QSPI function can be realized on the CPU without supporting the QSPI function, the structure is simple, the realization is easy, and the cost is low.

[0085] The application has the advantages that the method for realizing the QSPI function based on the GPIO pin simulation of the CPU only needs 6 GPIO pins to realize the QSPI function on the CPU without supporting the QSPI function, the structure is simple, the realization is easy, and the cost is low.

[0086] Compared with the SPI, the QSPI has 4 data lines and is bidirectional transmission, while the SPI has only 2 data lines, so that the transmission efficiency is greatly improved. The method is also compatible with the function of simulating the SPI communication through the GPIO.

[0087] In the description of the application, it should be understood that the terms "center", "thickness", "upper", "lower", "horizontal", "top", "bottom", "inner", "outer", "radial" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. Therefore, the features limited by "first", "second", "third" can explicitly or implicitly include one or more of the features.

Claims

1. A method for simulating QSPI functionality using CPU GPIO pins, characterized in that, Includes the following steps: S1. Simulate the QSPI pin using the CPU's GPIO pins, specifically: Four GPIO pins are configured to simulate the data transmission signals IO0~IO3 in the QSPI pins, one GPIO pin is configured to simulate the chip select signal CS in the QSPI pins, and one GPIO pin is configured to simulate the clock signal SCLK in the QSPI pins. S2. Communication with the slave device is achieved through the QSPI pins simulated by the CPU, specifically as follows: S21, Communication Transmission Preparation Phase; S22, Communication Transmission Phase, specifically: S221, Transmit Address / Command Sub-stage, specifically: The CPU sets the output signals via the transmission signal pins IO0~IO3, sets the first valid level of the transmitted address / command, sets the clock signal pin SCLK to a non-first valid level, and prepares the address / command to be sent via the transmission signal pins IO0~IO3; sets the clock signal SCLK to the first valid level, and sends the address / command to be transmitted to the slave device via the transmission signal pins IO0~IO3. After all addresses / commands are sent through the IO0~IO3 pins, the clock signal SCLK pin is set to a non-first active level to end the address / command transmission sub-stage. S222. After completing the address / command, enter the null instruction substage; S223. After the empty instruction sub-stage ends, the data transmission sub-stage begins, completing the communication transmission stage. In S223, the data transmission sub-stage is specifically divided into CPU data receiving mode and CPU data sending mode. The CPU data transmission mode is specifically as follows: The CPU sets the output signals via the transmission signal pins IO0~IO3, sets the second valid level of the transmitted data, sets the clock signal pin SCLK to a non-second valid level, and prepares the data to be sent via the transmission signal pins IO0~IO3; sets the clock signal SCLK to the second valid level, and sends the data to be transmitted to the slave device via the transmission signal pins IO0~IO3. After the data is sent, the communication transmission phase is complete. The specific CPU data receiving mode is as follows: The CPU sets the input signals through the transmission signal pins IO0~IO3, and sets the third valid level of the transmitted data. When the clock signal pin SCLK is at the third valid level, the data transmitted by the slave device is received through the transmission signal pins IO0~IO3. After the data transmission is completed, the communication transmission stage is finished. S23, Communication transmission termination stage.

2. The method for simulating QSPI function based on CPU GPIO pins according to claim 1, characterized in that, Specifically, S21 is: Pull the chip select signal CS pin low to make it active, and determine the sampling level of the clock signal SCLK pin based on the data transmitted in the communication.

3. The method for simulating QSPI function based on CPU GPIO pins according to claim 1, characterized in that, Specifically, S222 is: After the address / command is completed, the CPU sets the high and low values ​​of the clock signal SCLK pin 1 to 31 times to enter the no-instruction sub-stage.

4. The method for simulating QSPI function based on CPU GPIO pins according to claim 1, characterized in that, Specifically, S23 is: Pull the chip select signal CS pin and the clock signal SCLK pin high.

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