On-die Static Random Access Memory (SRAM) for caching logical-to-physical (L2P) tables

Abstract

The present disclosure describes methods and systems for reading data from a flash memory. A method may include receiving, by a flash memory controller, a read request for data stored in a plurality of flash memory dies. The read request includes a logical address of the data. Each flash memory die of the plurality of flash memory dies includes one or more flash memory arrays and one or more on-die static random access memory (SRAM) storage devices. The method further includes: identifying the on-die SRAM storage of the flash memory die that contains logical-to-physical (L2P) information; and searching the L2P information to obtain a physical address of the data corresponding to the logical address. The method further includes retrieving the data from the flash memory array of the flash memory die using the physical address.

Description

[0001] This application is a divisional application, and its original application is the international patent application PCT / CN2021 / 075939 which entered the Chinese national stage on March 8, 2021 and has an international filing date of February 8, 2021. The Chinese national application number of the original application is 202180000414.2, and the invention title is "Die Static Random Access Memory (SRAM) for Caching Logic-to-Physical (L2P) Tables". Technical Field

[0002] The present disclosure generally relates to the field of flash memory, and more particularly, to systems and methods for reducing latency in the operation of flash memory devices. Background Art

[0003] Memory cells have been scaled down to smaller sizes through improved process technologies, circuit designs, programming algorithms, and manufacturing processes. In many servers and mobile devices, NAND flash memory (a non-volatile storage technology) is widely used as the main non-volatile storage device due to its high storage density and relatively low access latency. Three-dimensional (3D) NAND flash memory has been developed to further increase storage density and reduce manufacturing costs. However, as smaller device sizes provide the benefit of significantly improved storage capacity, it has become increasingly challenging to effectively and timely read and write data in memory devices. Summary of the Invention

[0004] The present disclosure includes a method for reading data from a flash memory, including receiving, by a flash memory controller, a read request for data stored in a plurality of flash memory dies. The read request includes a logical address of the data. Each flash memory die of the plurality of flash memory dies includes one or more flash memory arrays and one or more die static random access memory (SRAM) storage devices. The method further includes: identifying the die SRAM storage of the flash memory die containing logic-to-physical (L2P) information; and searching the L2P information to obtain a physical address of the data corresponding to the logical address. The method further includes retrieving the data from the flash memory array of the flash memory die using the physical address.

[0005] The present disclosure also includes a method for reading data from a flash memory, including receiving, by a flash memory controller, a read request for data stored in a plurality of flash memory dies. The read request includes a logical address of the data, and the flash memory controller includes a controller memory. Each flash memory die of the plurality of flash memory dies includes one or more flash memory arrays and one or more on-die static random access memory (SRAM) memories. The method further includes searching for logical-to-physical (L2P) information in the controller memory. Responsive to the L2P information being in the controller memory: the method includes obtaining a physical address of the data using the L2P information and retrieving the data from the plurality of flash memory dies using the physical address. Responsive to the L2P information not being in the controller memory: the method includes identifying an on-die SRAM device of a flash memory die that contains the L2P information and searching for the L2P information to obtain a physical address corresponding to the logical address. The method further includes retrieving the data from the flash memory array of the flash memory die using the physical address.

[0006] The present disclosure also includes a flash memory system having a plurality of flash memory dies. Each flash memory die includes one or more NAND memory arrays and one or more on-die SRAM memories. The flash memory system further includes a flash memory controller, the flash memory controller including a controller memory and one or more processors. When executing instructions, the one or more processors are configured to receive a read request for data stored in the plurality of flash memory dies, wherein the read request includes a logical address of the data. The one or more processors are further configured to identify an on-die SRAM memory that contains logical-to-physical (L2P) information, the on-die SRAM device being formed on a flash memory die of the plurality of flash memory dies. The one or more processors are further configured to search for the L2P information to obtain a physical address of the data corresponding to the logical address. The flash memory controller is further configured to retrieve the data from the NAND memory array of the flash memory die using the physical address. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with the convention in the industry, various features are not drawn to scale. In fact, for clarity of illustration and discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figure 1 is a block diagram showing a flash memory system in accordance with some embodiments of the present disclosure.

[0009] Figure 2 is a schematic circuit diagram showing a flash memory array in accordance with some embodiments of the present disclosure.

[0010] Figure 3 is a flowchart showing the operation of a flash memory system according to some embodiments of the present disclosure. Detailed implementation

[0011] Although specific constructions and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other constructions and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure can also be used in a variety of other applications.

[0012] Note that references in this specification to "one embodiment", "an embodiment", "exemplary embodiments", "some embodiments", etc. indicate that the described embodiments include specific features, structures, or characteristics, but each embodiment may not necessarily include the specific features, structures, or characteristics. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described, will be within the knowledge of those skilled in the relevant art.

[0013] Generally, the terms can be understood at least in part from their use in the context. For example, at least in part depending on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can also be understood to convey a singular usage or a plural usage, at least in part depending on the context.

[0014] It should be readily understood that the meanings of "on", "above", and "over" in the present disclosure should be interpreted in the broadest possible way such that "on" not only means "directly on something", but also includes the meaning of "on something" with intermediate features or layers therebetween, and "above" or "over" not only means the meaning of "above" or "over" something, but can also include the meaning of "above" or "over" something without intermediate features or layers therebetween (i.e., directly on something).

[0015] In addition, spatial relative terms, such as "below", "beneath", "lower", "above", "upper", etc., may be used herein for convenience of description to describe the relationship of one element or feature to another (or multiple) element or feature as shown in the figures. Spatial relative terms are intended to cover different orientations in the use or operation of the device in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0016] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate includes a top surface and a bottom surface. The top surface of the substrate is where the semiconductor device is formed, and thus the semiconductor device is formed at the top side of the substrate. The bottom surface is opposite to the top surface, and thus the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include various semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0017] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entire upper structure or lower structure, or may have a scope that is less than the scope of the lower structure or upper structure. In addition, the layer may be a region of a uniform or non-uniform continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, the layer may be located between any pair of horizontal planes between the top surface and the bottom surface of the continuous structure or at the top surface and the bottom surface of the continuous structure. The layer may extend horizontally, vertically, and / or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and / or may have one or more layers on, above, and / or below it. The layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (wherein contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.

[0018] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process operation set during the design phase of a product or process, as well as a range of values above and / or below the expected value. The range of values may result from minor variations in the manufacturing process or tolerances. As used herein, the term "about" indicates a given amount of value that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may indicate a given amount of value that varies within, for example, 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0019] As used herein, the term "3D NAND memory device" (referred to herein as "memory device") refers to a semiconductor device having vertically oriented 3D NAND memory cell transistor strings (referred to herein as "memory strings", e.g., NAND strings or 3D NAND memory strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction with respect to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0020] A solid state drive (SSD) is a storage device capable of recording data. For example, an SSD device can use non-volatile memory components to store and retrieve data. A user or device interface allows other systems to access the storage capacity of the SSD device. To permanently store data, various types of non-volatile memory can be used, e.g., flash-based memory. 3D NAND memory devices are a type of non-volatile memory device developed to increase data storage capacity. Flash memory devices can be fabricated using several different types of integrated circuit technologies, such as NOR or NAND logic gates with floating gates. Depending on the application, flash memory devices can be arranged in arrays and configured to be accessed as blocks, pages, words, and / or bytes. Each page can contain 2 N bytes, where N is an integer, and a typical page size can be, for example, 2048 bytes (2 kb), 4096 bytes (4 kb), 8192 bytes (8 kb) or more per page. Pages can be arranged into blocks. For example, a block can contain 64, 128 or more pages. Read and write operations for NAND memory devices are performed on a per-page basis, while erase operations can be performed on a per-block basis.

[0021] Hard disks are linearly addressed by logical addresses (e.g., logical block addresses), while NAND devices address memory storage by physical addresses (e.g., page numbers). Thus, flash memory devices typically allocate a portion of the controller circuitry to maintain a record of the mapping of each logical block address to the current page number of the stored data. This recorded mapping can be managed by a flash translation layer (FTL), which can provide a logical-to-physical (L2P) table for mapping the two addresses. The FTL can be implemented using the allocated portion of the flash memory controller circuitry and control software. To retrieve a specific data segment, a host device can provide the logical address of the target data, and the flash memory controller can utilize the L2P mapping table to identify the physical page address of the target data in the non-volatile memory device and retrieve the stored data.

[0022] Several methods can be used to store and maintain the L2P mapping table. One such method is single-level direct L2P mapping. Under this mapping scheme, the mapping table includes entries for each page and an overview page for metadata at the end of each block containing logical block address information. The L2P mapping table can be stored in a memory device within the flash memory controller. For example, the L2P mapping table can be stored in a static random access memory (SRAM) device. Single-level direct L2P mapping can contain mapping information for the entire flash memory device. Thus, the single-level direct page mapping scheme requires a large amount of storage space (on the order of 1-2 MB per GB of user storage) to store the L2P mapping table, which can be challenging for high-capacity flash storage memory devices.

[0023] Another method for storing and maintaining the L2P mapping table is a multi-level mapping scheme. For example, a multi-level mapping scheme can group multiple adjacent logical blocks together and can include a page global directory for each group of blocks. The page global directory can be stored in a memory device (e.g., SRAM) within the flash memory controller for fast access. The mapping scheme also includes a page middle directory and a page table, which are stored and maintained at the memory cell level in pages located in the spare area of the NAND memory device. The page table contains the physical block number and physical page number of the data.

[0024] A flash translation layer (“FTL”) can be located in the flash memory control module to convert logical addresses to physical addresses. Under single-level direct L2P mapping, the FTL can read and scan the L2P mapping table stored within the flash memory controller. Under a multi-level mapping scheme, the FTL will read the page global directory stored in the flash memory controller and access the spare memory cells of the NAND memory device for the page middle directory and page table in order to retrieve the requested data address. The FTL can be a module stored in static random access memory (SRAM) or dynamic random access memory (DRAM) within the flash memory controller module. The access speed to SRAM within the flash memory and the access speed to the spare memory cells of the NAND memory device can be different. For example, the read latency of SRAM within the flash memory controller module can be on the order of a few microseconds, while the read latency from the cell level of the NAND memory device can be of a larger order of magnitude, e.g., dozens of microseconds.

[0025] As the storage capacity in memory devices (e.g., 3D NAND memories) increases, the size of the L2P table has become very large, and a large amount of storage space is required for access operations such as storing the L2P table and buffering data. In particular, in mobile devices that do not include DRAM memories, implementing a single-level direct L2P table in the SRAM memory of a flash memory controller may result in a larger device size and higher manufacturing costs. On the other hand, implementing a multi-level mapping scheme by storing components of the L2P table at the flash memory controller and at spare memory cells of the non-volatile memory device may result in long latency and a degradation of device performance.

[0026] To address the above drawbacks, the embodiments described herein are directed to systems and methods for reducing latency in a flash memory system without expanding the device footprint. More particularly, the present disclosure is directed to caching the L2P table in an SRAM memory that is on the same die as the NAND flash memory array, i.e., on-die SRAM. For example, the page middle directory and the page table can be stored in the on-die SRAM for quick access by the flash memory controller. The method can include implementing program code and / or algorithms for an indication flag that provides the location of the L2P table including the address information of the target data. For example, the indication flag can indicate a first state indicating that the target L2P table is stored in the on-die SRAM memory or a second state indicating that the L2P table is stored in the SRAM of the flash memory controller. Since a flash memory system can include more than one flash memory die, the indication flag can also indicate which flash memory die contains the on-die SRAM storing the target L2P table. Additionally, the method can further include exchanging the L2P table between various on-die SRAMs and the SRAM of the flash memory controller. The structures and components described in this application can be implemented in hardware, firmware, software, or any combination thereof. The methods and systems described in the present disclosure can reduce the read latency of a 3D NAND flash memory device by more than 90%.

[0027] Figure 1FIG. 0 shows a block diagram of a flash memory system 100 in accordance with some embodiments. The flash memory system 100 may include a flash memory controller 110 and an array of flash memory dies 160. The flash memory controller 110 communicates with a host controller 102 via an interface 104. The host controller 102 is operable to request the flash memory controller to perform read, program, and erase operations of the flash memory dies 160 by sending commands and / or data via the interface 104. The flash memory controller 110 may be configured to retrieve data from one or more flash memory dies 160 (e.g., an array of flash memory devices) and send the data to the host controller 102 via a data bus. The retrieved data may be transferred by the host controller 102 to a host computer or other system components not shown. The array of flash memory devices may include an array of one or more NAND flash memories, as introduced below as element 170.

[0028] The host controller 102 sends data to be stored at the flash memory dies 160 or retrieves data by commanding the flash memory controller 110 to read data from the flash memory dies 160. The host controller 102 may process I / O requests received from a host computer ( Figure 1 not shown), ensure data integrity and efficient storage, and manage the flash memory dies 160. The interface 106 may provide data and control communication between the flash memory controller 110 and the flash memory dies 160 via a data bus.

[0029] The flash memory controller 110 may include an encoder / decoder unit 120, a control logic unit 130, a controller memory 132, a flash translation layer (FTL) 140, and a page buffer 150. Other suitable components may be included in the flash memory controller 110 and are not shown or described herein for simplicity. In some embodiments, the FTL 140 may also include a storage area (e.g., SRAM) for storing L2P mapping information or any other suitable information.

[0030] The encoder / decoder unit 120 may provide encoding and decoding of data processed by the flash memory controller 110. The encoder / decoder unit 120 may also generate and store an error correction code (ECC) and metadata, as well as for memory management. The encoder / decoder unit 120 may be used to detect and correct errors in the stored data.

[0031] The control logic unit 130 can be any suitable integrated circuit (e.g., one or more processors) configured to receive instructions from the host controller 102 and perform read, program, and erase operations of the flash memory die 160 by transmitting commands and / or data to / from the flash memory die 160 via the interface 106 (as understood by a person of ordinary skill in the art (POSA)). For example, the control logic unit 130 receives requests for access to the flash media (e.g., read or write operations) from one or more external devices via the host controller 102. The control logic unit 130 can also be configured to communicate with and control other components of the flash memory controller 110. For example, the control logic unit 130 can command the FTL to scan the internal memory storage to obtain mapping information and send / receive address mapping information from the FTL. The control logic unit 130 can also communicate with the encoder / decoder unit 120, the page buffer 150, and other suitable components of the flash memory controller 110.

[0032] The controller storage 132 can be used to store commands for the operation of the control logic unit 130. In some embodiments, the controller storage 132 can be a storage medium for storing mapping information. For example, the controller storage 132 can include a single-level direct L2P mapping table for the sectors of the flash memory die 160. In some embodiments, the controller storage 132 can include page global directory information for the flash memory die 160. The page global directory information can be stored in a random access memory device (RAM) and used as a pseudo-cache to provide fast lookup of mapping data. The page global directory is well understood by a POSA and is not described in detail herein for simplicity. In some embodiments, the controller storage 132 can include software code, commands, computer logic, firmware, any suitable information. In some embodiments, the controller storage 132 can be an SRAM device.

[0033] The flash translation layer (FTL) 140 can be configured to provide an L2P mapping table for translating logical addresses into physical addresses. Requests to access the flash memory medium received by the control logic unit 130 can include one or more logical block addresses where user data is to be read or written. The FTL 140 can be configured to convert the logical block address of the desired data into a physical address by scanning various L2P tables. For example, the FTL 140 can generate L2P mapping information and send such information to a storage medium located in the flash memory controller 110, e.g., the controller memory 132. The FTL 140 can also send the mapping information to a storage medium located on the flash memory die 160, e.g., on-die SRAM or memory cells. The FTL 140 can also search the above storage medium when requested by the flash memory controller 110 to obtain L2P information.

[0034] The page buffer 150 can include one or more register circuits for storing data segments. For example, in a two-pass programming scheme, the page buffer 150 can store data such as lower page data, intermediate page data, and upper page data. Data transfer between the host controller 102 and the array of flash memory dies 160 can be temporarily stored in the page buffer 150. The structure and function of the page buffer 150 are well understood by POSA and are not described in detail here for simplicity.

[0035] The flash memory die 160 can be configured to store user data and includes circuit components for communicating with the flash memory controller 110 and for storing L2P mapping information. In some embodiments, each flash memory die 160 can include a data cache 162, on-die SRAM 164, and a NAND flash memory array 170. The flash memory die 160 can be a memory chip (package), a memory die, or any part of a memory die. In some embodiments, each flash memory die 160 can include one or more on-die SRAM 164 or one or more NAND flash memory arrays 170. For simplicity, additional on-die SRAM 164 and NAND flash memory arrays 170 are not shown Figure 1 here.

[0036] The data cache 162 can be configured to temporarily store data transferred between the flash memory controller 110 and the NAND flash memory array 170. For example, during a read operation for accessing stored user data from the NAND flash memory array 170, the data cache 162 can be configured to temporarily store the retrieved data before sending the retrieved data to the flash memory controller 110.

[0037] The SRAM 164 on the die can be configured to store L2P mapping information for fast access by the flash memory controller 110. For example, in a multi-level mapping scheme, the L2P mapping information (e.g., page middle directory and page table) can be stored in the SRAM 164 on the die and accessed by the FTL 140 of the flash memory controller 110 through the interface 160. Since reading data from an SRAM storage medium can be several orders of magnitude faster than reading data from NAND flash memory cells, storing such information in the SRAM 164 on the die can provide the benefit of particularly low data read latency compared to storing the L2P information in spare memory cells of the NAND flash memory array. In some embodiments, the SRAM 164 on the die can be any other suitable memory device having a speed faster than NAND flash memory cells. In some embodiments, a storage medium such as dynamic RAM (DRAM) can be implemented in the flash memory die 160 to perform a similar function as the SRAM 164 on the die.

[0038] The NAND flash memory array 170 can include one or more memory planes, and each memory plane can include a plurality of memory blocks. The same and concurrent operations can occur at each memory plane. A memory block, which can be megabyte (MB) sized, is the smallest size at which an erase operation is performed. Each memory block can include a plurality of memory cells, and each memory cell can be addressed through interconnections such as bit lines and word lines. The bit lines and word lines can be arranged vertically (e.g., in rows and columns respectively), thus forming an array of metal lines. For simplicity, the memory block is also referred to as the "memory array" or "array". The memory array is the core area in the memory die and performs the storage function.

[0039] Figure 2 is a schematic circuit diagram showing the arrangement of flash memory cells according to some embodiments of the present disclosure. The NAND flash memory array 170 can include deployments as Figure 2An array of flash memory cells 172 of the array arrangement shown. The NAND flash memory array 170 can be a 3D NAND flash memory array that includes a stacked layer of gate electrodes disposed over a substrate, wherein semiconductor channels pass through and intersect the word lines and enter the substrate. The bottom / lower gate electrode serves as the bottom / lower select gate. The top / upper gate electrode serves as the top / upper select gate. The word line / gate electrode between the top / upper select gate electrode and the bottom / lower gate electrode serves as the word line. The intersection of the word line and the semiconductor channel forms the memory cell. The top / upper select gate is connected to the word line for row selection, and the bottom / lower select gate is connected to the bit line for column selection. Examples of 3D NAND flash memory devices and methods of forming the same can be found in U.S. Patent No. 10,559,592, entitled "Memory Device and Forming Method Thereof", which is incorporated herein by reference in its entirety.

[0040] Each of the NAND flash memory cells 172 indicates one or more bit values stored therein. Specifically, each NAND flash memory cell 172 can include a transistor having a floating gate that stores charge. The NAND flash memory cells 172 are coupled in the form of a plurality of series strings 174, wherein the drains of the memory cells are all coupled to the sources of another NAND flash memory cell 172. The NAND flash memory array 170 can include word lines WL0-WLN. Each of the word lines WL0-WLN can be connected to the control gates of each of the NAND flash memory cells 172 in a row of the NAND flash memory array 170 and is used to bias the control gates of the NAND flash memory cells 172 in that row. The NAND flash memory array 170 also includes bit lines BL0-BLK. Each of the bit lines BL0-BLK is coupled to the series strings 174 and is coupled to the data cache 162. A sensing circuit (not shown, but obvious to one of ordinary skill in the art) can be controlled by the control logic unit 130 to detect the state of each NAND flash memory cell 172 by sensing the voltage or current on a specific one of the bit lines BL0-BLK.

[0041] Other suitable circuit components can be included in Figure 2 the schematic circuit diagram and are not shown for simplicity. For example, select gates, sensing circuits, address decoders, driver circuits, other support logic units / circuits, and any suitable circuit components can be included and are omitted herein for brevity.

[0042] Figure 3is a flowchart showing the operation of a flash memory system implementing on-die SRAM for reducing data read latency according to some embodiments of the present disclosure. It should be understood that method 300 is not exhaustive, and other operating steps may be performed before, after, or between any of the illustrated operating steps. In some embodiments, some of the operating steps of method 300 may be omitted, or other operating steps may be included, which are not described herein for simplicity. In some embodiments, the operating steps of method 300 may be performed in a different order and / or variation. Method 300 may be performed using the flash memory devices and circuits described in Figure 1 and Figure 2 .

[0043] According to some embodiments of the present disclosure, method 300 begins at operating step 310, where the host controller initiates a user data read request. Referring to Figure 1 , the host controller 102 may initiate a user data request command to the flash memory controller 110 through the interface 104 to request a specific user data segment stored in the flash memory array 170. In some embodiments, the request command may include one or more logical addresses of the requested user data.

[0044] According to some embodiments of the present disclosure, method 300 continues to operating step 320, where the flash memory controller scans and searches the L2P table in the medium storage (e.g., SRAM) of the flash memory controller. Referring to Figure 1 , the flash memory controller 110 may be configured to receive a user data request from the host controller and command the FTL 140 to search the controller storage 132 of the flash memory controller 110 to determine whether the controller storage 132 contains mapping information of the requested user data. In some embodiments, the controller storage 132 may include a single-level direct L2P mapping for user data selection. For example, to reduce read latency, the storage medium of the flash memory controller 110 may contain single-level direct L2P mapping information for user data frequently accessed by users. In some embodiments, the storage medium of the flash memory controller 110 may also contain sectors of L2P mapping information. For example, in a multi-level mapping scheme, the controller storage 132 may include a page global directory, and the FTL 140 may be configured to search the page global directory.

[0045] According to some embodiments of the present disclosure, method 300 continues to operating step 330, where the FTL is configured to determine whether the L2P data is stored in the controller medium storage. In some embodiments, the user data request initiated by the host controller may include logical address information of the requested data. Referring to Figure 1, FTL 140 can be configured to determine whether the L2P address information corresponding to the logical address information is stored in the controller media storage or in the flash memory die.

[0046] According to some embodiments of the present disclosure, if the FTL determines that the L2P address information is stored in the flash controller storage, method 300 proceeds to operation step 340, where the FTL reads the sector of the L2P information from the flash controller storage. Refer to Figure 1 , FTL 140 can be configured to search the contents of the controller storage 132 to identify the sector of the L2P mapping data corresponding to the logical address information received from the host controller 102. Method 300 proceeds to operation step 342, where the physical address is retrieved based on the read of the L2P data. In a single-level direct L2P mapping scheme, FTL 140 can look up the physical address in the L2P mapping table to obtain the corresponding physical address of the logical address received from the host controller 102.

[0047] Method 300 proceeds to operation step 380, where the control logic unit 130 of the flash memory controller 110 retrieves user data from the NAND flash memory array 170 based on the physical address of the user data. Then, method 300 proceeds to operation step 390, where the flash memory controller transfers the data to the host controller. For example, the flash memory controller 110 receives user data from the flash memory die 160 and temporarily stores the user data in the page buffer 150 before transferring the user data to the host controller 102 through the interface 104.

[0048] On the other hand, if the FTL determines at operation step 330 that the L2P address information is not stored in the flash controller memory, method 300 proceeds to operation step 350, where the indication flag is checked to determine where the L2P address information is stored. For example, a first state of the indication flag (e.g., state 0) may inform the flash memory controller 110 that the corresponding L2P address information is stored at a spare cell in one of the die of the flash memory die 160. The indication flag may be a bit string that provides information, e.g., identifying which die in the flash memory die the L2P address information is stored in. For example, the indication flag may be one or more bits of information stored in the controller memory 132. The indication flag may also include block information indicating whether the L2P mapping information is stored in the NAND flash memory array 170 or in the on-die SRAM 164. If the L2P address information is stored at a spare cell of the NAND flash memory array 170, method 300 proceeds to operation step 360, where the FTL 140 may be configured to retrieve the physical address from the L2P data stored at the spare cell of the NAND flash memory array 170. The indication flag may include information that guides the flash memory controller 110 to a specific die containing the L2P data.

[0049] Alternatively, a second state of the indication flag (e.g., state 1) may inform the flash memory controller 110 that the corresponding L2P address information is stored in the on-die SRAM. The indication flag may also be configured to include an identification of the on-die SRAM, e.g., the die number where the on-die SRAM is located. The indication flag may also include an identification of the sector of the on-die SRAM on which the relevant portion of the L2P mapping information is stored. According to some embodiments of the present disclosure, in such a case, method 300 proceeds to operation step 370, where the FTL may be configured to sweep the sector of the L2P mapping data from the on-die SRAM to the controller memory. Based on the information provided by the indication flag, the FTL may identify the sector of the on-die SRAM of a specific die of the flash memory die 160 and sweep the sector of the L2P mapping data from the on-die SRAM 164 to the controller memory 132. In some embodiments, sweeping the sector of the L2P mapping data includes transferring the sector of the L2P mapping data from the on-die SRAM 164 to the flash memory controller 110 and storing the sector of the L2P mapping data in the controller memory 132. According to some embodiments of the present disclosure, method 300 proceeds to operation 372, where the FTL updates the indication flag. Refer to Figure 1, the FTL 140 can update the indication flag to include information of sectors of the L2P mapping data currently stored in the controller memory 132. The stored information can be used for subsequent read requests. According to some embodiments of the present disclosure, method 300 proceeds to operation 374, where a physical address can be retrieved from the L2P data. The FTL 140 can be configured to scan and read the L2P data that has been swept onto the controller memory 132, and obtain the physical address corresponding to the logical address provided by the host controller 102. The indication flag can include one or more additional suitable states.

[0050] According to some embodiments of the present disclosure, then, method 300 proceeds to operation step 380, where data is read from the memory cell. Based on the physical address obtained by the FTL 140, the control logic unit 130 of the flash memory controller 110 retrieves user data from the NAND flash memory array 170 based on the physical address of the user data.

[0051] Then, method 300 proceeds to operation step 390, where the flash memory controller transfers the data to the host controller. For example, the flash memory controller 110 receives user data from the flash memory die and transfers the user data to the host controller 102 through the interface 104.

[0052] Various embodiments of the present disclosure are directed to systems and methods for reducing latency in a flash memory system without expanding the footprint of the device. For example, the flash memory die can include an SRAM memory on the same die as the NAND flash memory array. The method can include program code and / or algorithms implementing one or more indication flags for providing the location of an L2P table including address mapping information of target data. For example, the indication flag can indicate a first state indicating that the target L2P table is stored in the on-die SRAM memory of the die or a second state indicating that the L2P table is stored in the SRAM of the flash memory controller.

[0053] In some embodiments, a method for reading data from a flash memory includes receiving, by a flash memory controller, a read request for data stored in a plurality of flash memory dies. The read request includes a logical address of the data. Each of the plurality of flash memory dies includes one or more flash memory arrays and one or more on-die static random access memory (SRAM) storage devices. The method further includes: identifying the on-die SRAM memory of the flash memory die containing the logical-to-physical (L2P) information; and searching the L2P information to obtain the physical address of the data corresponding to the logical address. The method further includes retrieving the data from the flash memory array of the flash memory die using the physical address.

[0054] In some embodiments, a method for reading data from a flash memory includes receiving, by a flash memory controller, a read request for data stored in a plurality of flash memory dies. The read request includes a logical address of the data, and the flash memory controller includes a controller memory. Each flash memory die of the plurality of flash memory dies includes one or more flash memory arrays and one or more on-die static random access memory (SRAM) memories. The method further includes searching the controller memory for logical-to-physical (L2P) information. In response to the L2P information being in the controller memory: the method includes obtaining a physical address of the data using the L2P information and retrieving the data from the plurality of flash memory dies using the physical address. In response to the L2P information not being in the controller memory: the method includes identifying an on-die SRAM memory device of a flash memory die that contains the L2P information and searching the L2P information to obtain a physical address corresponding to the logical address. The method further includes retrieving the data from the flash memory array of the flash memory die using the physical address.

[0055] In some embodiments, a flash memory system includes a plurality of flash memory dies. Each flash memory die includes one or more NAND memory arrays and one or more on-die SRAM memories. The flash memory system further includes a flash memory controller that includes a controller memory and one or more processors. When executing instructions, the one or more processors are configured to receive a read request for data stored in the plurality of flash memory dies, where the read request includes a logical address of the data. The one or more processors are further configured to identify an on-die SRAM memory that contains logical-to-physical (L2P) information, the on-die SRAM memory being formed on the flash memory die of the plurality of flash memory dies. The one or more processors are further configured to search the L2P information to obtain a physical address of the data corresponding to the logical address. The flash memory controller is further configured to retrieve the data from the NAND memory array of the flash memory die using the physical address.

[0056] The foregoing description of the specific embodiments will so fully disclose the general nature of the present disclosure that others can, by applying the knowledge within the skill of the art, readily modify and / or adapt these specific embodiments for various applications without undue experimentation and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments. It should be understood that the language or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of this specification is to be interpreted by those skilled in the art in light of the teachings and guidance.

[0057] Embodiments of the present disclosure have been described above by means of functional building blocks of embodiments showing specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries can be defined as long as the specified functions and their relationships are appropriately performed.

[0058] The Summary of the Invention and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as envisioned by the inventor(s), and thus are not intended to limit the present disclosure and the appended claims in any way.

[0059] The breadth and scope of the present disclosure should not be limited by any of the above exemplary embodiments, but should be defined only in accordance with the appended claims and their equivalents.

Claims

1. A flash memory controller, comprising one or more processors, the one or more processors being configured to: Receive a request command for data stored in multiple flash memory dies, wherein, The request command includes the logical address of the data; Identify a die - on - SRAM storage device containing logical - to - physical (L2P) information, the die - on - SRAM storage device being formed on a flash memory die of the plurality of flash memory dies; Search the L2P information to obtain the physical address of the data corresponding to the logical address; And Retrieve the data from the NAND memory array of the flash memory die using the physical address.

2. The flash memory controller according to claim 1, wherein, The flash memory controller further includes a flash translation layer (FTL) configured to obtain the physical address of the data.

3. The flash memory controller according to claim 2, wherein, The flash memory controller further includes a controller memory configured to store an indication flag, the indication flag containing the location of the L2P information.

4. The flash memory controller according to claim 3, wherein, The location includes the address of the die - on - SRAM storage device.

5. The flash memory controller according to claim 1, wherein, Use a single - level direct L2P mapping or a multi - level mapping scheme to store and maintain the L2P information.

6. The flash memory controller according to claim 3, wherein the flash translation layer (FTL) is further configured to search the controller memory for the L2P information.

7. The flash memory controller according to claim 6, wherein the flash translation layer (FTL) is further configured to, in response to the L2P information not being in the controller memory, identify a flash memory die containing the L2P information.

8. The flash memory controller according to claim 7, wherein, Identifying a flash memory die containing the L2P information includes determining a sector of the L2P mapping table.

9. The flash memory controller according to claim 6, wherein the flash translation layer (FTL) is further configured to, in response to the L2P information not being in the controller memory, check the indication flag.

10. The flash memory controller according to claim 9, wherein the flash translation layer (FTL) is further configured to, based on the information obtained from the indication flag, determine a sector of the L2P mapping table.

11. The flash memory controller according to claim 10, wherein the flash translation layer (FTL) is further configured to sweep the sector of the L2P mapping table from the die - on - SRAM storage device to the controller memory.

12. The flash memory controller according to claim 10, wherein the flash translation layer (FTL) is further configured to update the indication flag with information related to the sector of the L2P mapping table.

13. The flash memory controller according to claim 11, wherein, Sweeping the sector of the L2P mapping table from the die - on - SRAM storage device to the controller memory includes: Transmitting the sector of the L2P mapping table from the die - on - SRAM storage device to the flash memory controller; and Storing the sector of the L2P mapping table in the controller memory.

14. The flash memory controller according to claim 1, wherein, The flash memory controller further includes a page buffer for temporarily storing the requested data.

15. The flash memory controller according to claim 1, wherein, The flash memory controller further includes an encoder / decoder unit capable of providing encoding and decoding of the processed data.

16. The flash memory controller according to claim 1, wherein, The request command includes a read request, a program request, and an erase request.

17. A NAND flash memory, comprising a flash memory die, wherein, The flash memory die includes: one or more NAND memory arrays; and one or more on-die SRAM storage devices; wherein, the NAND flash memory is configured to: cache logical-to-physical (L2P) information on the on-die SRAM storage device, and output corresponding L2P information in response to a request command for data stored in the NAND memory array.

18. The NAND flash memory according to claim 17, wherein, The flash memory die further includes a data cache for temporarily storing the data requested in the NAND memory array.

19. The NAND flash memory according to claim 17, wherein, A single-level direct L2P mapping or a multi-level mapping scheme is used to store and maintain the L2P information.

20. The NAND flash memory according to claim 17, wherein, The request command includes a read request, a program request, and an erase request.

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