A local feedback push-pull driving power mosfet circuit

Abstract

The application discloses a partial feedback push-pull type driving power MOSFET circuit, which comprises branch A, branch B and branch C; the branch A comprises a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1 and a second NMOS transistor MN2; the branch B comprises a third PMOS transistor MP3, a third NMOS transistor MN3, a first resistor R1 and a second resistor R2; and the branch C comprises a power MOS transistor M0. The partial feedback push-pull type driving power MOSFET circuit can effectively reduce di / dt through local feedback.

Description

Technical Field

[0001] The present invention relates to a power MOSFET driving integrated circuit, in particular to a local feedback push-pull driving power MOSFET circuit. Background Art

[0002] Power MOSFET driver circuits are widely used in integrated power chips. Currently, push-pull circuits are commonly used to drive power MOSFETs.

[0003] like Figure 1 As shown in the figure, when the drive signal is logic low, MP1 turns on and MN1 turns off. The voltage on VG1 quickly rises to the power supply voltage, turning M1 on. When the drive signal is logic high, MP1 turns off and M1 turns on, pulling the voltage on VG1 to ground and turning M1 off. However, in existing push-pull drive circuits, the di / dt of the power MOSFET device is very large during the turn-on and turn-off processes. Summary of the Invention

[0004] The object of the present invention is to overcome the deficiencies of the prior art and to provide a local feedback push-pull driving power MOSFET circuit, which can effectively reduce di / dt through local feedback.

[0005] The object of the present invention is achieved through the following technical solutions: a local feedback push-pull driving power MOSFET circuit, comprising branch A, branch B and branch C;

[0006] The branch A includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2. The source of the first PMOS transistor MP1 is connected to the power supply terminal, the drain of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, the source of the second NMOS transistor MN2 is connected to the drain of the first NMOS transistor MN1, and the source of the first NMOS transistor MN1 is grounded; the gates of the second PMOS transistor MP2 and the second NMOS transistor MN2 are connected, and the common end of the connections is connected to the drive input port; the gates of the first PMOS transistor MP1 and the first NMOS transistor MN1 are connected; the common end of the gates of the first PMOS transistor MP1 and the first NMOS transistor MN1 is connected to the common end of the drains of the second PMOS transistor MP2 and the second NMOS transistor MN2;

[0007] The branch B includes a third PMOS transistor MP3, a third NMOS transistor MN3, a first resistor R1, and a second resistor R2; the source of the third PMOS transistor MP3 is connected to the power supply terminal, the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3 via the first resistor R1 and the second resistor R2 in sequence, the source of the third NMOS transistor MN3 is connected to the source of the first NMOS transistor MN1, and the common end thereof is grounded; the gates of the third PMOS transistor MP3 and the third NMOS transistor MN3 are connected, and the common end of the connection is connected to the drive input port, and the common end of the first resistor R1 and the second resistor R2 is connected to the common end of the gates of the first PMOS transistor MP1 and the first NMOS transistor MN1;

[0008] The branch C includes a power MOS transistor M0 , a gate of the power MOS transistor M0 is connected to a common end of the first resistor R1 and the second resistor R2 , a source of the power MOS transistor M0 is grounded, and a drain is connected to the output port Drain.

[0009] The beneficial effect of the present invention is that the present invention can effectively reduce the di / dt of the M0 tube through local feedback, thereby preventing the M0 tube from being damaged by excessive voltage overshoot. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a schematic diagram of the principle of a traditional push-pull drive circuit;

[0011] Figure 2 It is a schematic diagram of the principle of the present invention;

[0012] Figure 3 Schematic diagram of the switching characteristics of the present invention;

[0013] Figure 4 This is a schematic diagram showing the principle of replacing the first PMOS transistor MP1 and the first NMOS transistor MN1 with transistors in the embodiment;

[0014] Figure 5 Schematic diagram of the principle when the second PMOS transistor MP2 and the second NMOS transistor MN2 are replaced by transistors in the embodiment;

[0015] Figure 6 This is a schematic diagram of the principle of adding two MOS tubes, MP11 and MN12, at both ends of MP1 and MN1;

[0016] Figure 7 This is a schematic diagram of the principle of adding multiple MOS tubes at both ends of MP1 and MN1;

[0017] Figure 8 For the general Figure 2 Schematic diagram of the principle of parallel connection of branch A;

[0018] Figure 9 Schematic diagram of the principle of setting multiple voltage partitions. DETAILED DESCRIPTION

[0019] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0020] like Figure 2 As shown, a local feedback push-pull driving power MOSFET circuit includes branch A, branch B and branch C;

[0021] The branch A includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2. The source of the first PMOS transistor MP1 is connected to the power supply terminal, the drain of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, the source of the second NMOS transistor MN2 is connected to the drain of the first NMOS transistor MN1, and the source of the first NMOS transistor MN1 is grounded; the gates of the second PMOS transistor MP2 and the second NMOS transistor MN2 are connected, and the common end of the connections is connected to the drive input port DRV; the gates of the first PMOS transistor MP1 and the first NMOS transistor MN1 are connected; the common end of the gates of the first PMOS transistor MP1 and the first NMOS transistor MN1 is connected to the common end of the drains of the second PMOS transistor MP2 and the second NMOS transistor MN2;

[0022] The branch B includes a third PMOS transistor MP3, a third NMOS transistor MN3, a first resistor R1, and a second resistor R2; the source of the third PMOS transistor MP3 is connected to the power supply terminal, the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3 via the first resistor R1 and the second resistor R2 in sequence, the source of the third NMOS transistor MN3 is connected to the source of the first NMOS transistor MN1, and the common end thereof is grounded; the gates of the third PMOS transistor MP3 and the third NMOS transistor MN3 are connected, and the common end of the connection is connected to the drive input port, and the common end of the first resistor R1 and the second resistor R2 is connected to the common end of the gates of the first PMOS transistor MP1 and the first NMOS transistor MN1;

[0023] The branch C includes a power MOS transistor M0 , a gate of the power MOS transistor M0 is connected to a common end of the first resistor R1 and the second resistor R2 , a source of the power MOS transistor M0 is grounded, and a drain is connected to the output port Drain.

[0024] Among them, A is a traditional push-pull circuit with two MOS tubes MP1 and MN1 added to control the conduction and shutdown of A; B is a push-pull circuit with resistors R1 and R2 added between the MOS tubes MP3 and MN3 to adjust the rate of rise of the VG1 voltage; C is a power MOSFET circuit.

[0025] like Figure 3 As shown, in the embodiment of the present application, T1 to T4 are in the on state, and T5 to T8 are in the off state. At T0, DRV is logic low, MP1, MP2, and MP3 are on, MN1, MN2, and MN3 are off, and the VG1 voltage rises rapidly. At T1, VG1 rises to the threshold voltage (Vth) of M0, and M0 is turned on. VG1 continues to rise, and the drain-source current of M0 begins to rise. At T2, it enters the Miller region, the VG1 voltage remains unchanged, and IDS remains unchanged. On the left side of T3, due to the feedback of the VG1 voltage, the voltage VDS across the source and drain of M0 slowly decreases, avoiding a sharp drop. At T3, M1 leaves the Miller region, VG1 slowly rises, and di / dt decreases. At T5, DRV is logic high, MP1, MP2, and MP3 are off, and MN1, MN2, and MN3 are on. VG1 drops rapidly, and enters the Miller region at T6. At time T7, the device leaves the Miller region, and the voltage drop of VG1 is fed back to MN1. This causes the voltage drop of VG1 to become smoother, the di / dt to decrease, and the voltage overshoot across the source and drain of M0 to decrease. At time T8, VG1 is less than the threshold voltage of MN1, M0 is cut off, and the drain-source current is zero.

[0026] Generally speaking, in the on-state, MP1, MP2, and MP3 are conducting. Because MP1 and MP2 are larger than MP3, under identical conditions, the conduction current of MP1 and MP2 is greater than that of MP3. Initially, the currents in branches A and B combine to rapidly increase the voltage of VG1. Feedback from VG1 to MP1 reduces the current in branch A, gradually reducing the rate of increase of the voltage on VG1. When VG1 exceeds the power supply voltage minus the threshold voltage of MP1, MP1 is disconnected. Branch B then continues to increase the voltage on VG1. The rate of increase can be adjusted by varying the ratio of R1 / R2. A larger ratio results in a slower rate of increase of the voltage on VG1 and a smaller di / dt. Similarly, in the off-state, MN1, MN2, and MN3 are conducting. The three transistors work together to pull down the voltage on VG1, which then feeds back to MN1, reducing the current in branch A and gradually reducing the rate of decrease of the voltage on VG1. When VG1 falls below the threshold voltage of MN1, MN1 disconnects. Continuing to pull down the VG1 voltage by branch B can effectively reduce di / dt.

[0027] In the embodiment of the present application, MP1 and MN1 may be replaced by transistors, and MP2 and MN2 may be replaced by transistors;

[0028] When the first PMOS transistor MP1 and the first NMOS transistor MN1 can be replaced by transistors, as shown in FIG. Figure 4 As shown, the source, drain, and gate of the MOS tube correspond to the emitter, collector, and base of the triode, respectively, and the base of the triode needs to be connected to a resistor and then connected to other devices corresponding to the position of the MOS tube.

[0029] When the second PMOS transistor MP2 and the second NMOS transistor MN2 are replaced by transistors, Figure 5 As described above, the source, drain and gate of the MOS tube correspond to the emitter, collector and base of the triode respectively, and the base of the triode needs to be connected to a resistor and then connected to other devices corresponding to the position of the MOS tube.

[0030] like Figure 6 As shown, in the embodiment of the present application, two MOS transistors, MP11 and MN12, are added at both ends of MP1 and MN1 and are connected in a diode manner. Specifically, the source of the first PMOS transistor MP1 is further connected to the PMOS transistor MP11, the drain of the PMOS transistor MP11 is connected to the source of the first PMOS transistor MP1, the source of the PMOS transistor MP11 is connected to the power supply terminal, and the gate and drain of the PMOS transistor MP11 are connected;

[0031] At this time, the drain of the first NMOS transistor is also connected to the NMOS transistor MN12, the drain of the NMOS transistor MN12 is connected to the source of the first NMOS transistor MN1, the source of the NMOS transistor MN12 is grounded, and the gate of the NMOS transistor MN12 is connected to the drain;

[0032] By adding MOS tubes, the cutoff voltage of MP1 and MN1 tubes can be reduced and increased by one diode conduction voltage respectively.

[0033] like Figure 7 As shown, there can be N PMOS tubes and NMOS tubes added. At this time, the cut-off voltage of MP1 and MN1 tubes decreases and increases by N diode conduction voltages respectively.

[0034] like Figure 8 As shown, Figure 2 The A structures in the circuit are connected in parallel, so that the overall current flowing through the entire A structure is larger.

[0035] like Figure 9 As shown, Figure 2 The A structure in the figure is connected in parallel, but the number of MOS tubes connected with diodes on each path increases successively. In this way, the rising rate of VG1 is different in different DRV voltage ranges.

[0036] The foregoing description shows and describes a preferred embodiment of the present invention. However, as previously stated, it should be understood that the present invention is not limited to the form disclosed herein and should not be construed as excluding other embodiments. Instead, the present invention is applicable to various other combinations, modifications, and environments and is capable of modification within the scope of the inventive concept described herein, through the teachings above, or through techniques or knowledge in the relevant art. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention are intended to be within the scope of the appended claims.

Claims

1. A local feedback push-pull driving power MOSFET circuit, characterized in that: Including branch A, branch B and branch C; The branch A includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2. The source of the first PMOS transistor MP1 is connected to the power supply terminal, the drain of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, the source of the second NMOS transistor MN2 is connected to the drain of the first NMOS transistor MN1, and the source of the first NMOS transistor MN1 is grounded; the gates of the second PMOS transistor MP2 and the second NMOS transistor MN2 are connected, and the common end of the connections is connected to the drive input port DRV; the gates of the first PMOS transistor MP1 and the first NMOS transistor MN1 are connected; the common end of the gates of the first PMOS transistor MP1 and the first NMOS transistor MN1 is connected to the common end of the drains of the second PMOS transistor MP2 and the second NMOS transistor MN2; The branch B includes a third PMOS transistor MP3, a third NMOS transistor MN3, a first resistor R1, and a second resistor R2; the source of the third PMOS transistor MP3 is connected to the power supply terminal, the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3 via the first resistor R1 and the second resistor R2 in sequence, the source of the third NMOS transistor MN3 is connected to the source of the first NMOS transistor MN1, and the common end thereof is grounded; the gates of the third PMOS transistor MP3 and the third NMOS transistor MN3 are connected, and the common end of the connection is connected to the drive input port, and the common end of the first resistor R1 and the second resistor R2 is connected to the common end of the gates of the first PMOS transistor MP1 and the first NMOS transistor MN1; The branch C includes a power MOS transistor M0 , a gate of the power MOS transistor M0 is connected to a common end of the first resistor R1 and the second resistor R2 , a source of the power MOS transistor M0 is grounded, and a drain is connected to the output port Drain.

2. The local feedback push-pull driving power MOSFET circuit according to claim 1, characterized in that: When the first PMOS transistor MP1 and the first NMOS transistor MN1 are replaced by a transistor, the source, drain, and gate of the MOS transistor correspond to the emitter, collector, and base of the transistor, respectively, and the base of the transistor needs to be connected to a resistor before being connected to other devices corresponding to the position of the MOS transistor.

3. The local feedback push-pull driving power MOSFET circuit according to claim 1, characterized in that: When the second PMOS transistor MP2 and the second NMOS transistor MN2 are replaced by a transistor, the source, drain, and gate of the MOS transistor correspond to the emitter, collector, and base of the transistor, respectively, and the base of the transistor needs to be connected to a resistor before being connected to other devices at the position corresponding to the MOS transistor.

4. The local feedback push-pull driving power MOSFET circuit according to claim 1, characterized in that: The source of the first PMOS transistor MP1 is further connected to the PMOS transistor MP11, the drain of the PMOS transistor MP11 is connected to the source of the first PMOS transistor MP1, the source of the PMOS transistor MP11 is connected to the power supply terminal, and the gate and drain of the PMOS transistor MP11 are connected; At this time, the drain of the first NMOS transistor is also connected to the NMOS transistor MN12, the drain of the NMOS transistor MN12 is connected to the source of the first NMOS transistor MN1, the source of the NMOS transistor MN12 is grounded, and the gate of the NMOS transistor MN12 is connected to the drain.

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