Wafers, wafer dicing methods, and chips

Abstract

This application provides a wafer, a method for dicing the wafer, and a chip. The wafer may include: multiple chips; each chip includes at least one core logic region; each core logic region is surrounded by a protection zone, and the protection zone of each core logic region is surrounded by a dicing zone; each core logic region includes an isolation unit for blocking communication signals between adjacent core logic regions; the dicing zone includes circuit units for connecting the core logic regions on both sides. Therefore, this application can avoid mechanical damage that may occur during wafer dicing by setting a protection zone around the core logic region. Furthermore, this application also provides isolation units within the core logic region to block communication signals between adjacent core logic regions before dicing, avoiding potential circuit damage when dicing multiple logic regions simultaneously.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a wafer, a method for dicing a wafer, and a chip. Background Technology

[0002] In the manufacturing process of chip products, integrated circuits are fabricated on wafers using various process technologies to form chips with specific functions. This allows a complete wafer to be cut into individual dies (i.e., chips) to facilitate the next stage of production.

[0003] Currently, a single tape-out can only produce one type of chip from a single mask. However, in some practical applications, it is often necessary to produce chips with the same function but different processing capabilities, such as chips for 8-core and 4-core processors. Using traditional manufacturing methods, two tape-outs are required to produce two different masks, which not only increases NRE (Non-recurring engineering) costs but also increases time costs. Summary of the Invention

[0004] This application aims to provide a wafer, a method for dicing a wafer, and a chip, so that chips with different structures can be obtained after dicing by fabricating a mask in only one fabrication process before dicing, thereby expanding the variety of chips and improving the applicability of the wafer.

[0005] To achieve the above objectives, this application provides a wafer comprising: a plurality of chips; each chip comprising at least one core logic region; a protection zone surrounding each core logic region, and a dicing zone surrounding the protection zone of each core logic region; each core logic region comprising an isolation unit for blocking communication signals between adjacent core logic regions; and the dicing zone comprising a circuit unit for connecting two core logic regions.

[0006] Furthermore, the wafer also includes a common power grid for providing power signals; each core logic region also includes a field-effect transistor for isolating power signals.

[0007] Furthermore, the wafer also includes multiple power supply grids that provide different power signals; wherein each core logic region includes one power supply grid.

[0008] Furthermore, the cutting area between the protection zones surrounding each core logic zone also includes an electrostatic discharge unit for protecting the circuits in each core logic zone.

[0009] Furthermore, the chip includes multiple core logic regions; wherein each core logic region is provided with a self-test logic unit for detecting whether communication between adjacent core logic regions is smooth.

[0010] Furthermore, the chip includes a loopback logic unit for detecting whether a test chain in at least one core logic region forms a closed loop.

[0011] Furthermore, the core logic area also includes: a clock-gated logic unit and a power-gated logic unit for controlling communication signals between adjacent core logic areas, a cross-clock domain synchronization unit for eliminating metastability caused by different clocks, and a decoupling capacitor unit for ensuring the stability of the power supply signal provided by the power supply grid.

[0012] Furthermore, at least two core logic regions have different dimensions in the vertical direction; and / or, the at least two core logic regions have different dimensions in the horizontal direction.

[0013] This application also provides a method for cutting the wafer provided in this application, the method comprising: cutting along a cutting region between protected areas surrounding a core logic region and / or between protected areas surrounding multiple core logic regions in the wafer to obtain multiple chips.

[0014] This application also provides a chip obtained by dicing the wafer described above, wherein the method for dicing the wafer is the method described above provided in this application.

[0015] The beneficial effects of the technical solutions provided in some embodiments of this application include at least the following:

[0016] In the above embodiments of this application, the wafer may include: multiple chips; each chip includes at least one core logic region; each core logic region is surrounded by a protection zone, and the protection zone of each core logic region is surrounded by a dicing zone; each core logic region includes an isolation unit for blocking communication signals between adjacent core logic regions; the dicing zone includes a circuit unit for connecting the core logic regions on both sides. Thus, this application can avoid mechanical damage that may occur during wafer dicing by setting a protection zone around the core logic regions. Furthermore, this application also sets isolation units within the core logic regions to block communication signals between adjacent core logic regions before dicing, avoiding potential circuit damage when dicing multiple logic regions simultaneously. In this way, this application can diced the wafer to obtain the desired chip by performing only one fabrication process and creating only one mask before dicing. In addition, this application can also, as needed, perform a complete dicing of multiple core logic regions during the wafer dicing process, so that a single chip can include multiple core logic regions. Therefore, based on the wafer structure in the embodiments of this application, different dicing methods can be used to obtain multiple chips, which not only expands the types and applicability of chips, but also avoids the additional NRE costs caused by multiple wafer fabrication. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the wafer structure provided in an embodiment of this application;

[0019] Figure 2 This is a schematic diagram of the structure of a chip in a wafer provided in an embodiment of this application;

[0020] Figure 3 This is a schematic diagram of another chip structure in a wafer provided in an embodiment of this application;

[0021] Figure 4 This is a schematic diagram of the structure of a chip in a wafer provided in an embodiment of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms "comprising" and "provided with," and any variations thereof, in the specification, claims, and foregoing drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," "third," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a specific order or hierarchy. The term "multiple" in this application refers to two or more (including two).

[0024] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0025] The wafer, the method of dicing the wafer, and the chip according to this application will be described in detail below with reference to the accompanying drawings.

[0026] Reference Figure 1 The image shows a top view of a wafer with a grid-like structure.

[0027] In some embodiments, the wafer of this application may include multiple chips, each chip including at least one core logic region. Each core logic region is surrounded by a protection zone, and the protection zone of each core logic region is surrounded by a dicing zone.

[0028] Possibly, each core logic region may include an isolation unit; the segmentation region may include a circuit unit; wherein, the isolation unit may be interconnected with the circuit unit.

[0029] Understandable Figure 1 The wafer shown may include one or more chips A, which may include multiple core logic regions.

[0030] See Figure 2 In a specific example, Figure 2The core 2 in chip A shown may specifically include: a first core logic region 21, a second core logic region 22, a first inner segmentation region 23 (segmentation region) disposed between the first core logic region 21 and the second core logic region 22, a first inner protection zone 24 disposed between the first core logic region 21 and the first inner segmentation region 23, and a second inner protection zone 25 disposed between the second core logic region 22 and the first inner segmentation region 23 (i.e., the first core logic region 21 is connected to the first inner segmentation region 23 through the first inner protection zone 24, and the second core logic region 22 is connected to the first inner segmentation region 23 through the second inner protection zone 25). Further, Figure 2 An outer protection zone 3 can be set around the kernel 2 shown, and an outer cutting zone 1 can be set around the outer protection zone 3 of the first core logic zone 21 and the second core logic zone 22.

[0031] It is understood that, in this embodiment of the application, the wafer can be cut along the outer cutting area 1 of the outer protection zone 3 to obtain chip A. In this way, based on the setting of the outer protection zone 3, when cutting the outer cutting area 1, the outer protection zone 3 can prevent mechanical damage to the inner core area 2 during the cutting process.

[0032] Furthermore, each core logic area may include an isolation unit for blocking communication signals between adjacent core logic areas, and the segmentation area may include a circuit unit for connecting the core logic areas on both sides.

[0033] See Figure 2 The first inner slicing area 23 shown can be equipped with circuit units, and the first core logic area 21 and the second core logic area 22 can be equipped with isolation units. Further, the isolation units in the first core logic area 21 and the second core logic area 22 can be equipped with control switches and controlled to be connected to the circuit units. Specifically, when the control switch is closed, the isolation unit is electrically connected to the circuit unit, and at this time, the isolation unit acts as a connection and conduction mechanism. When the first inner slicing area 23 is not sliced, it can be used not only to test chip A, but also to realize the communication function between the first core logic area 21 and the second core logic area 22. When the control switch is open, the electrical connection between the isolation unit and the circuit unit is broken, and at this time, the isolation unit is used to block the signals output by the circuit unit to the first core logic area 21 and the second core logic area 22.

[0034] In the above embodiments of this application, the wafer may include: multiple chips; each chip includes at least one core logic region; each core logic region is surrounded by a protection zone, and the protection zone of each core logic region is surrounded by a dicing zone; each core logic region includes an isolation unit for blocking communication signals between adjacent core logic regions; the dicing zone includes a circuit unit for connecting the core logic regions on both sides. Thus, this application can avoid mechanical damage that may occur during wafer dicing by setting a protection zone around the core logic regions. Furthermore, this application also sets isolation units within the core logic regions to block communication signals between adjacent core logic regions before dicing, avoiding potential circuit damage when dicing multiple logic regions simultaneously. In this way, this application can diced the wafer to obtain the desired chip by performing only one fabrication process and creating only one mask before dicing. In addition, this application can also, as needed, perform a complete dicing of multiple core logic regions during the wafer dicing process, so that a single chip can include multiple core logic regions. Therefore, based on the wafer structure in the embodiments of this application, different dicing methods can be used to obtain multiple chips, which not only expands the types and applicability of chips, but also avoids the additional NRE costs caused by multiple wafer fabrication.

[0035] In some implementations, the wafer may also include the same power grid for providing power signals; each core logic region may also include field-effect transistors for isolating power signals.

[0036] For example, in Figure 2 The chip A shown can be configured with a power supply grid to provide power signals to the circuit units in the first core logic region 21, the second core logic region 22, and the first inner slicing region 23. Furthermore, field-effect transistors (MOSFETs) can be installed in the first core logic region 21 and the second core logic region 22. The first inner slicing region 23 can be controlled to connect to the first core logic region 21 and the second core logic region 22 via MOSFETs and connected to the same power supply grid. Therefore, based on the MOSFET configuration, the first inner slicing region 23 can be electrically connected to the same power supply grid for functional testing of the chip. Simultaneously, the power signals between the first inner slicing region 23 and the power supply grid can be isolated by the MOSFETs to prevent them from affecting the power signals between the first core logic region 21 and the second core logic region 22 and the power supply grid.

[0037] In some implementations, the wafer may also include multiple power grids that provide different power signals; specifically, each core logic region may include one power grid.

[0038] For example, in Figure 2In the chip A shown, the first core logic region 21, the second core logic region 22, and the first inner slicing region 23 can use different power supply grids. In this case, the power signal between the first inner slicing region 23 and its corresponding power supply grid does not affect the power signals between the first core logic region 21 and the second core logic region 22 and their corresponding power supply grids.

[0039] In some implementations, the cutting area between the protection zones surrounding each core logic region in this application embodiment may further include an electrostatic discharge unit for protecting the circuitry in each core logic region.

[0040] For example, an electrostatic discharge unit can also be provided in the first inner dicing region 23. Specifically, the electrostatic discharge unit can be used to prevent the circuits in the first core logic region 21 and the second core logic region 22 from being damaged by electrostatic discharge generated by the first inner dicing region 23 when the wafer is diced.

[0041] In some implementations, each core logic area in this application embodiment is provided with a self-test logic unit for detecting whether communication between adjacent core logic areas is smooth.

[0042] For example, in Figure 2 The first core logic region 21 shown can be equipped with a self-test logic unit (BIST logic circuit). Specifically, the BIST logic circuit can be used to detect the various circuit connections in the first inner cut region 23, the components in the circuits, and whether the communication between the first core logic region 21 and the second core logic region 22 is smooth when the first inner cut region 23 is not cut. Therefore, the embodiments of this application can greatly reduce the dependence of various circuits in the first core logic region 21 and the second core logic region 22, as well as the components in the various circuits, on automatic test equipment (ATE) during the testing process of chip A.

[0043] In some implementations, each chip in this application embodiment may include a loopback logic unit for detecting whether a test chain located in at least one core logic region forms a closed loop.

[0044] For example, in Figure 3The multiple logic regions of the core in the chip A shown can be arranged side by side along the vertical axis L. Specifically, the core 2 of chip A can include 3 core logic regions, 2 partitioned regions, and 4 protected regions. The 3 core logic regions are a first core logic region 31, a second core logic region 32, and a third core logic region 39. The 2 partitioned regions are a first inner partitioned region 33 between the first core logic region 31 and the second core logic region 32, and a second inner partitioned region 36 between the second core logic region 32 and the third core logic region 35. The 4 protected regions are a first inner protected region 34 between the first core logic region 31 and the first inner partitioned region 33, a second inner protected region 35 between the second core logic region 32 and the first inner partitioned region 33, a third inner protected region 37 between the second core logic region 32 and the second inner partitioned region 36, and a fourth inner protected region 38 between the third core logic region 39 and the second inner partitioned region 36. Furthermore, self-test logic units can be respectively set in the first core logic region 31, the second core logic region 32, and the third core logic region 39, and a loopback logic unit for detecting whether the test chain in each core logic region forms a closed loop can be set in at least one of the aforementioned core logic regions. For example, after the first inner dicing region 33 is diced, the loopback logic unit can make the test chain of the individual die (chiplet) formed after dicing form a closed loop, thereby ensuring that the individual die can successfully complete the test.

[0045] Possibly, in the embodiments of this application, the size of the first core logic area 31 in the vertical direction L is smaller than the size of the second core logic area 32 in the vertical direction L; and / or the size of the first core logic area 31 in the horizontal direction W is smaller than the size of the second core logic area 32 in the horizontal direction W, that is, the first core logic area 31 and the second core logic area 32 may be the same or different in area.

[0046] Possibly, refer to Figure 4In this embodiment of the application, the multiple logic regions of the core in chip A can be arranged side by side in the vertical direction L and the horizontal direction W. Specifically, the core 2 of chip A can include 3 core logic regions, 2 segmentation regions, and 4 protection regions. Among them, the first core logic region 41 and the second core logic region 42 can be arranged side by side in the vertical direction L, and the third core logic region 49 can be located on one side of the first core logic region 41 and the second core logic region 42 in the horizontal direction W. Further, a first inner segmentation region 43 can be provided between the first core logic region 41 and the second core logic region 42, and a second inner segmentation region 46 can be provided between the third core logic region 49 and the first core logic region 41 and the second core logic region 42. Furthermore, a first inner protection zone 44 can be set between the first core logic area 41 and the first inner cutting area 43, a second inner protection zone 45 can be set between the second core logic area 42 and the first inner cutting area 43, a third inner protection zone 47 can be set between the first core logic area 41, the second core logic area 42 and the second inner cutting area 46, and a fourth inner protection zone 48 can be set between the second inner cutting area 46 and the third core logic area 49.

[0047] In some implementations, the core logic area may further include: clock-gated logic units and power-gated logic units for controlling communication signals between adjacent core logic areas, cross-clock domain synchronization units for eliminating metastability caused by different clocks, and decoupling capacitor units for ensuring the stability of power signals provided by the power grid.

[0048] For example, in Figure 4 The first core logic region 41 of the chip A shown can also be equipped with clock gating logic units and power gating logic units, which can be controlled to be turned on or off respectively. When the first inner slicing region 43 is not sliced, the first core logic region 41 and the second logic region 42 can communicate across the first inner slicing region 43, and the clock gating logic units and power gating logic units can be directly turned on. When the first inner slicing region 43 is sliced, the first core logic region 41 and the second logic region 42 do not need to communicate across the first inner slicing region 43, and the clock gating logic units and power gating logic units can be directly turned off to save power consumption. In addition, in order to eliminate the metastability caused by different clock domains, a clock domain crossing (CDC) unit can also be set in the first inner slicing region 43; in order to ensure the stability of the power supply voltage, a decoupling capacitor (DECAP) unit can also be set in the first inner slicing region 43.

[0049] It is understandable that the second inner segmentation area 46 can have the same internal structure as the first inner segmentation area 43. The second core logic area 42 can have the same or different internal structure as the first core logic area 41. Similarly, the third core logic area 49 can have the same or different internal structure as the first core logic area 41.

[0050] This application also provides a method for dicing the wafer described above. The method includes dicing along a dicing region between protected zones surrounding a core logic region and / or between protected zones surrounding multiple core logic regions in the wafer to obtain multiple chips.

[0051] For example, when dicing a wafer, it can be done along... Figure 4 The outer cutting region 1 shown is cut to obtain chip A; it can also be cut along the first inner cutting region 43 and / or the second inner cutting region 46 to obtain multiple small grains (small chips).

[0052] Specifically, during the dicing process, the outer dicing area 1 can be diced to separate each inner core area 2 from its corresponding outer dicing area 1. At this point, depending on requirements, the first core logic area 41, the second core logic area 42, the third core logic area 49, the first inner dicing area 43, and the second inner dicing area 46 can be used directly as a single die. Alternatively, depending on requirements, the first inner dicing area 43 and / or the second inner dicing area 46 can be selectively diced. In this case, the first core logic area 41, the second core logic area 42, and the third core logic area 49 can be used individually or in combination of two to form different dies. This allows for further increases in the dicing methods of the wafer and the chip A located within it, based on the structure of chip A, thereby obtaining more different types of chips and further expanding the wafer's applicability.

[0053] This application also provides a chip obtained by dicing the wafer described above, wherein the method for dicing the wafer is the method described above.

[0054] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A wafer, characterized in that, The wafer includes: Multiple chips; Each chip includes at least one core logic area; Each core logic area is surrounded by a protection zone, and each core logic area is surrounded by a cutting zone. Each core logic region includes an isolation unit for blocking communication signals between adjacent core logic regions; the segmentation region includes a circuit unit for connecting the core logic regions on both sides. The isolation unit is equipped with a control switch, which is controlled to be connected to the circuit unit. When the control switch is closed, the isolation unit is connected to the circuit unit to connect and conduct different core logic areas through the isolation unit. When the control switch is open, the isolation unit is disconnected from the circuit unit to block the signals output by the circuit unit to the two core logic areas. When the wafer is diced, the communication signals between adjacent core logic regions are blocked by the isolation unit to generate the chip containing a single core logic region or a combination of core logic regions.

2. The wafer according to claim 1, characterized in that, The wafer also includes the same power grid for providing power signals; Each core logic region also includes field-effect transistors for isolating power signals.

3. The wafer according to claim 1, characterized in that, The wafer also includes multiple power grids that provide different power signals; wherein each core logic region includes one power grid.

4. The wafer according to claim 2 or 3, characterized in that, The cutting area between the protection zones surrounding each core logic region also includes an electrostatic discharge unit for protecting the circuitry within each core logic region.

5. The wafer according to claim 1, characterized in that, The chip includes multiple core logic regions; each core logic region is equipped with a self-test logic unit for detecting whether communication between adjacent core logic regions is smooth.

6. The wafer according to claim 5, characterized in that, The chip includes a loopback logic unit for detecting whether a test chain in at least one core logic region forms a closed loop.

7. The wafer according to claim 1, characterized in that, The core logic area also includes: a clock-gated logic unit and a power-gated logic unit for controlling communication signals between adjacent core logic areas, a cross-clock domain synchronization unit for eliminating metastability caused by different clocks, and a decoupling capacitor unit for ensuring the stability of the power signal provided by the power grid.

8. The wafer according to claim 1, characterized in that, At least two core logic regions have different dimensions in the vertical direction; and / or, the at least two core logic regions have different dimensions in the horizontal direction.

9. A method for dicing a wafer according to any one of claims 1 to 8, characterized in that, The method includes cutting along a cutting area between protected areas surrounding one core logic region and / or between protected areas surrounding multiple core logic regions in the wafer to obtain multiple chips.

10. A chip obtained by dicing a wafer according to any one of claims 1 to 8, characterized in that, The method for dicing the wafer is the method described in claim 9.

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