Continuous approximation register analog-to-digital converter and signal conversion method thereof

Abstract

A continuous approximation register analog-to-digital converter includes sampling circuitry, comparator circuitry, and controller circuitry. The sampling circuitry generates first and second signals from a sampled signal. The comparator circuitry compares the first and second signals to generate a plurality of first decision signals. The controller circuitry generates a plurality of digital codes from the first decision signals and controls the comparator circuitry to repeatedly compare to generate a plurality of second decision signals, thereby generating a digital output from the digital codes, a statistical noise value, and the second decision signals. The controller circuitry also controls the sampling circuitry and the comparator circuitry during an initialization phase, wherein the comparator circuitry repeatedly compares from the sampled signal having an initial level to generate a plurality of third decision signals, and the controller circuitry performs a statistical operation from the third decision signals to obtain the statistical noise value.

Description

TECHNICAL FIELD

[0001] The present application relates to an analog-to-digital converter, and more particularly, to a successive approximation register (SAR) analog-to-digital converter (ADC) with a function of estimating actual noise and performing a statistical operation and a signal conversion method thereof. BACKGROUND

[0002] The resolution of an analog-to-digital converter (ADC) is usually limited by the noise of the actual environment. In the prior art, the noise data of some circuits (e.g., comparators) in the ADC can be predicted by prior simulation, and a pre-design calculation can be performed according to the noise data to improve the resolution of the ADC. However, the noise of the actual environment can also include intrinsic noise (e.g., thermal noise and / or flicker noise, etc.) of other circuits and electromagnetic interference in the actual environment, etc. Therefore, the noise data predicted by prior simulation is not sufficient to reflect the actual noise data, so that the actual improvement of the resolution of the ADC is not obvious. SUMMARY

[0003] In some embodiments of the present application, a successive approximation register (SAR) analog-to-digital converter (ADC) includes sampling circuitry, a comparator circuit, and controller circuitry. The sampling circuitry is configured to generate a first signal and a second signal according to a sampling signal. The comparator circuit is configured to compare the first signal and the second signal to generate a plurality of decision signals. The controller circuitry is configured to generate a plurality of first digital codes according to the decision signals, and control the comparator circuit to generate the decision signals corresponding to a plurality of output comparison results according to the first digital codes, a statistical noise value, and the decision signals corresponding to the output comparison results. The controller circuitry is also configured to control the sampling circuitry and the comparator circuit in an initial stage, wherein the comparator circuit generates the decision signals corresponding to a plurality of estimated comparison results according to the sampling signal having an initial level, and the controller circuitry performs a statistical operation according to the decision signals corresponding to the estimated comparison results to obtain the statistical noise value.

[0004] In some embodiments, a signal conversion method includes the following operations: generating, by a successive approximation register (SAR) analog-to-digital converter (ADC) in an initial stage, a plurality of decision signals corresponding to a plurality of estimated comparison results according to a sampling signal having an initial level, and performing a statistical operation according to the decision signals corresponding to the estimated comparison results to obtain a statistical noise value; generating, by the SAR ADC, a plurality of first digital codes according to an input signal, and generating the decision signals corresponding to a plurality of output comparison results; and generating a digital output according to the first digital codes, the statistical noise value, and the decision signals corresponding to the output comparison results.

[0005] The present application is herein described in conjunction with the preferably embodiments thereof, with each of the embodiments discussed and illustrated to instill a full understanding of lower power analog-to-digital converters. These embodiments are presented by way of example only, and therefore, should not be considered to limit the scope of the application to these particular embodiments. In addition, although the application is described herein as being particularly useful in the field of lower power analog-to-digital converters, the application is also amenable to other fields where lower power analog-to-digital converters are useful. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 A schematic diagram of a continuous approximation register analog-to-digital converter according to some embodiments of the application;

[0007] Figure 2A A flowchart of operations for generating statistical noise values according to some embodiments of the application;

[0008] Figure 2B A schematic diagram of a continuous approximation register analog-to-digital converter according to some embodiments of the application; Figure 1 performing an operation in Figure 2A

[0009] Figure 2C performing another operation in Figure 1 Figure 2A

[0010] Figure 2D performing a plurality of operations in Figure 1 Figure 2A

[0011] Figure 3 A flowchart of operations for generating a digital output in Figure 1

[0012] Figure 4 A flowchart of a signal conversion method according to some embodiments of the application. DETAILED DESCRIPTION

[0013] All words used herein are to be interpreted in their normal and customary manner. The above words are defined in accordance with their definitions in commonly used dictionaries and the usage of any of the words discussed herein in the context of the present disclosure is merely exemplary and should not be limiting as to the scope and meaning of the present application. Similarly, the present application is not limited to the various embodiments shown and described herein.

[0014] ​​​​​​As used in the specification, the terms "coupled" and "connected" refer to any logical, electrical, and / or physical connection, direct or indirect, between two or more elements. As used in the specification, the term "circuitry" can refer to an independently completed electrical circuit or to a combination of electrical circuits, either of which can include passive element components, active element components, or combinations thereof.

[0015] As used in the specification, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used in the specification, the terms "first," "second," "third," etc. are used only to describe different elements, and do not imply a particular order or importance of the elements. Thus, a first element can also be termed a second element without departing from the scope of the application. For the sake of brevity, like elements in the various figures will be denoted by the same reference number.

[0016] Figure 1 A schematic diagram of a successive approximation register (SAR) analog-to-digital converter 100 (hereinafter referred to as SAR analog-to-digital converter 100) according to some embodiments of the present application is shown. The SAR analog-to-digital converter 100 includes a sampling circuitry 110, a comparator circuit 120, and a controller circuitry 130.

[0017] The sampling circuitry 110 is configured to generate a signal S1 and a signal S2 according to a sampling signal SS. In some embodiments, the sampling circuitry 110 includes a switch circuit 112 and a digital-to-analog converter circuit 114. The switch circuit 112 includes a plurality of switches T1-T3. The switch T1 is coupled between an input terminal IT1 of the SAR analog-to-digital converter 100 and a first input terminal of the comparator circuit 120. The switch T2 is coupled between an input terminal IT2 of the SAR analog-to-digital converter 100 and a second input terminal of the comparator circuit 120. The switch T3 is coupled between the input terminal IT1 and the input terminal IT2. The input terminal IT1 and the input terminal IT2 are configured to receive an input signal VIN.

[0018] When the switch IT1 and the switch IT2 are turned on and the switch IT3 is not turned on, the input signal VIN is output as the sampling signal SS via the switch IT1 and the switch IT2. In this condition, the SAR analog-to-digital converter 100 can convert the input signal VIN to a corresponding digital output DO. Alternatively, when the switch IT1, the switch IT2, and the switch IT3 are all turned on, the input terminal IT1 is coupled to the input terminal IT2. In this condition, the input terminal IT1 and the input terminal IT2 are shorted, and the switch circuit 112 can output the sampling signal SS having an initial level.

[0019] In this embodiment, the digital-to-analog converter circuit 114 can be a capacitive digital-to-analog converter circuit. For example, the digital-to-analog converter circuit 114 includes a switched capacitor array 114A and a switched capacitor array 114B. The switched capacitor array 114A is coupled to the switch T1 and the first input terminal of the comparator circuit 120, and is used to generate a signal S1 according to the sampling signal SS and the control of the controller circuit system 130. For example, the switched capacitor array 114A includes multiple capacitors and multiple switches. The capacitance values ​​of the multiple capacitors are C (denoted as 2). 0 C), C, 2 1 C, 2 2 C、…、2 B-2 C and 2 B-1 C, where 2 0 2 1 …、2 B-2 and 2 B-1 This represents the weights corresponding to these capacitors, and has the minimum weight (i.e., 2). 0 One capacitor is fixedly coupled to ground. In some embodiments, the value B in the capacitance value can be a positive integer. In some embodiments, the value B can be used to indicate the resolution of the SAR analog-to-digital converter 100. Based on the control of the controller circuit system 130, multiple switches selectively transmit either the ground voltage or the reference voltage VREF to the corresponding one of the remaining capacitors. The multiple capacitors can store the sampled signal SS and generate a signal S1 based on the switching of the multiple switches.

[0020] The switched capacitor array 114B is coupled to the switch T2 and the second input terminal of the comparator circuit 120, and is used to generate the signal S2 according to the sampled signal SS and the control of the controller circuit system 130. The configuration of the switched capacitor array 114B is similar to that of the switched capacitor array 114A, so it will not be described again here.

[0021] Comparator circuit 120 compares signals S1 and S2 to generate a decision signal SD. Controller circuit system 130 executes a binary search algorithm based on the decision signal SD to generate a digital output DO. Specifically, during analog-to-digital conversion, controller circuit system 130 determines a digital code (e.g., digital code d) for the digital output DO based on the decision signal SD. B-1 The controller circuit system 130 then switches the digital-to-analog converter circuit 114 accordingly. In response to the switching of the digital-to-analog converter circuit 114, the comparator circuit 120 compares the updated signal S1 with the signal S2 again to generate the next decision signal SD. The controller circuit system 130 determines the next digital code (e.g., digital code d) for the digital output DO based on this decision signal SD. B-2), and switches the digital-to-analog converter circuit 114. In this way, it is understood that during the analog-to-digital conversion, the comparator circuit 120 can sequentially compare the signal S1 with the signal S2 to generate a plurality of decision signals SD corresponding to a plurality of output comparison results (which are used to generate a plurality of first digital codes (e.g., the digital codes d B-1 , d B-2 , …, d1, d0) in the digital output DO.

[0022] In some embodiments, the controller circuitry 130 is further configured to generate the complete digital output DO according to the first digital codes, a statistical noise value (e.g., the statistical noise value σ noise ) and the decision signals SD corresponding to the output comparison results. In some embodiments, the controller circuitry 130 can control the sampling circuitry 110 and the comparator circuit 120 during an initial stage (e.g., a predetermined period after the SAR analog-to-digital converter 100 is powered on) in which the comparator circuit 120 generates the decision signals SD corresponding to a plurality of estimated comparison results (which are used to estimate the statistical noise value) according to the sampling signal SS having an initial level, and the controller circuitry 130 performs a statistical operation according to the decision signals SD to obtain the aforementioned statistical noise value. The operation thereof will be described in detail below with reference to Figures 2A to 3 .

[0023] In some embodiments, the controller circuitry 130 can be implemented by a digital signal processor circuit, a microcontroller circuit and / or a digital logic circuit, which can be configured to perform the operations in Figure 2A and Figure 3 . In some embodiments, the controller circuitry 130 further includes a memory circuit (not shown in the figure) configured to store data of the statistical noise value. In some embodiments, the controller circuitry 130 can include a first circuit portion configured to perform the analog-to-digital conversion, and a second circuit portion configured to perform the aforementioned statistical operation and generate the complete digital output DO. In some embodiments, the controller circuitry 130 can output a plurality of control signals (not shown in Figure 1 ) to control the switching of the switch circuit 112, and output another control signal (not shown in Figure 1 ) to control the timing of the comparator circuit 120.

[0024] For example, the controller circuit system 130 can output a first control signal to control the comparator circuit 120 to perform a comparison or reset, and the comparator circuit 120 can output a second control signal to notify the controller circuit system 130 that the comparison or reset has been completed. When the first control signal switches from a first logic value to a second logic value, the comparator circuit 120 can begin the comparison. When the comparator circuit 120 completes the comparison to generate a corresponding decision signal SD, the comparator circuit 120 can output a second control signal with a second logic value to notify the controller circuit system 130 that the comparison operation has been completed. The controller circuit system 130 can store the current decision signal SD accordingly and switch the first control signal from the second logic value back to the first logic value. In response to the first control signal with the first logic value, the comparator circuit 120 can be reset to restore the internal nodes in the comparator circuit 120 to a preset level. When the comparator circuit 120 completes the reset, the comparator circuit 120 can switch the second control signal from the second logic value back to the first logic value to notify the controller circuit system 130 that the reset operation has been completed. In this way, the controller circuit system 130 can switch the first control signal from a first logic value to a second logic value to begin the next comparison. Through the above repeated operation, the comparator circuit 120 can perform the comparison several times to generate multiple decision signals SD. The above-described arrangement between the comparator circuit 120 and the controller circuit system 130 is merely an example, and the present invention is not limited thereto.

[0025] Figure 2A The flowchart illustrates several operations for generating statistical noise values ​​according to some embodiments of the present invention. In some embodiments, the controller circuit system 130 may perform... Figure 2A Multiple operations are performed to determine the statistical noise value.

[0026] In operation S210, during the initial phase, the control sampling circuit system couples the first input terminal to the second input terminal to generate a sampling signal with an initial level.

[0027] Figure 2B As shown in some embodiments of the present invention Figure 1 The SAR analog-to-digital converter 100 performs Figure 2A A schematic diagram of operation S210 in the diagram. Figure 2BAs shown, in the initial stage, switches T1, T2, and T3 are all turned on. Under this condition, the first input terminal IT1 and the second input terminal IT2 are short-circuited. Therefore, the switching circuit 112 can output a sampling signal SS with an initial level (e.g., but not limited to zero) to the digital-to-analog converter circuit 114. In other words, the digital-to-analog converter circuit 114 can store the sampling signal SS with the initial level. In some embodiments, the sampling circuit system 110 can generate the sampling signal SS with the initial level using other configuration methods. For example, in the initial stage, the switching circuit 112 can couple input terminals IT1 and IT2 to a signal source for providing a preset level (e.g., ground voltage or reference voltage VREF). Various configuration methods for generating the initial level are all within the scope of this invention.

[0028] Continue to refer to Figure 2A In operation S220, during the initial stage, a component in the digital-to-analog converter circuit is switched (in... Figure 1 In the example, a capacitor receives a reference voltage to generate a first signal (e.g., signal S1) and a second signal (e.g., signal S2) based on a sampled signal having an initial level.

[0029] Figure 2C As shown in some embodiments of the present invention Figure 1 The SAR analog-to-digital converter 100 performs Figure 2A A schematic diagram of operation S220 is shown. Figure 2C As shown, after the sampled signal SS is stored, switches T1, T2, and T3 are not turned on. Further, the controller circuit system 130 switches the element with the minimum weight (e.g., 20) in the switched capacitor array 114A (in this example, a switchable capacitor) to receive the reference voltage VREF to generate signals S1 and S2. By operating S220, the level of signal S1 (i.e., the level at the first input of comparator circuit 120) is shifted by VREF / 2B. The above-described capacitor switching configuration is merely an example, and the invention is not limited thereto. In other embodiments, the controller circuit system 130 may switch one or more capacitors in the switched capacitor array 114A or switched capacitor array 114B to generate the corresponding signals S1 and S2.

[0030] Continue to refer to Figure 2A In operation S230, the comparator circuit is controlled to repeatedly compare the first signal and the second signal to generate multiple decision signals corresponding to multiple estimation comparison results. In operation S240, statistical operations are performed based on the multiple decision signals corresponding to the multiple estimation comparison results to obtain a statistical noise value.

[0031] Figure 2D As illustrated in some embodiments of the present inventionFigure 1 The SAR ADC 100 performs Figure 2A An illustration of the operations S230 and S240 is shown in FIG. 2B. As shown, based on the control of the controller circuitry 130, the comparator circuit 120 repeatedly compares the signal S1 with the signal S2 n1 times to generate n1 decision signals SD (which correspond to n1 estimated comparison results, which are used to estimate the statistical noise value). Figure 2D

[0032] In general analog-to-digital conversion, after generating the plurality of digital codes d B-1 , d B-2 , …, d1, d0, a residue voltage can be generated on the digital-to-analog converter circuit 114 due to residual charge. The residue voltage is equivalent to the quantization error of the SAR ADC 100 to the sampling signal SS to be converted. In addition, in practical applications, the comparison result of the comparator circuit 120 can be inaccurate due to various noises. To improve this problem, the controller circuitry 130 can estimate the statistical noise value through the operation S240, and then estimate the residue voltage. In some embodiments, if the input of the comparator circuit 120 is the sum of the residue voltage and the statistical noise value, a statistical operation can be used to determine the probability of the comparator circuit 120 outputting a decision signal SD with a logic value of 1. In some embodiments, the aforementioned statistical operation can include (but is not limited to) maximum likelihood estimation.

[0033] For example, referring to the related art document B. Verbruggen, J. Tsouhlarakis, T. Yamamoto, M. Iriguchi, E. Martens and J. Craninckx, “A 60dB SNDR 35MS / s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation,” in IEEE Journal of Solid-State Circuits, vol. 50, no. 9, pp. 2002-2011, Sept. 2015, Equation (1) of this document estimates the probability of the comparator circuit 120 outputting a decision signal SD with a logic value of 1 in a single comparison based on the maximum likelihood estimation method. Based on Equation (1) of the aforementioned document, it can be further derived that the probability of n1 decision signals SD with a logic value of 1 corresponding to n1 estimated comparison results conforms to the following Equation (2), where V res is the residue voltage, σ noise ​To calculate the statistical noise value, k1 is the number of decision signals SD having a preset logic value (e.g., logic value 1) among n1 decision signals, and erf() is an error function:

[0034]

[0035] If the value k1 is equal to the statistical noise value σ noise , the residual voltage V res can be calculated based on equation (2): -1 where erf() is an inverse error function:

[0036]

[0037] As mentioned above, in the initial stage, the level of the first input of the comparator circuit 120 is shifted by VREF / 2B (i.e., operation S220), so the residual voltage V res of equation (2) is equivalent to VREF / 2 B . Substituting VREF / 2 B into equation (3) gives:

[0038]

[0039] Therefore, in the initial stage, the controller circuit system 130 can perform a statistical operation (i.e., equation (4)) according to the value n1 and the value of VREF / 2 B to determine the statistical noise value σ noise , and store the statistical noise value σ noise . In this way, the controller circuit system 130 can estimate the residual voltage V noise using the statistical noise value σ res to generate a complete digital output DO. It should be understood that the statistical noise value σ noise above can include various noise data associated with the sampling circuit system 110 and the comparator circuit 120. In some embodiments, the aforementioned various noise conforms to a Gaussian distribution.

[0040] In the aforementioned reference, the statistical noise value σ noise is determined by simulation in advance. However, in this reference, the statistical noise value σ noise only covers the noise data of the comparator circuit, and the noise data obtained by simulation cannot fully reflect the real noise. For example, if the operating conditions such as process, voltage, temperature, etc. of the actual application vary, the statistical noise value σ noise will change. In other words, the statistical noise value σ noise of this reference is not sufficient to reflect the real noise data. In addition, the aforementioned reference needs to set multiple comparator circuits to generate sufficient statistical data.

[0041] In some embodiments of the present application, the statistical noise value σ noise is determined in an initial stage (e.g., a period after power-up) of the SAR ADC 100. In other words, the SAR ADC 100 can calculate the statistical noise value σ noise in an actual environment through a training process (i.e., operations performed in the initial stage). In this way, more accurate noise data can be obtained. In addition, in some embodiments of the present application, a sufficient amount of statistical data can be generated using only a single comparator circuit 120. In this way, circuit area and hardware cost can be saved.

[0042] Figure 3 is a flowchart of operations for generating the digital output DO according to some embodiments of the present application. In some embodiments, the controller circuitry 130 can perform the operations in Figure 1 to determine the digital output DO. Figure 3

[0043] In operation S310, a first signal and a second signal are generated according to a sampling signal. In operation S320, the first signal and the second signal are compared to generate a plurality of decision signals. In operation S330, a plurality of first digital codes (e.g., digital codes d B-1 , d B-2 , …, d1, d0) are generated according to the decision signals.

[0044] For example, the switches T1 and T2 are turned on, and the switch T3 is turned off. Under this condition, the switch circuit 112 can output the input signal VIN as the sampling signal SS. In response to the sampling signal SS, the switch capacitor array 114A and the switch capacitor array 114B generate different signals S1 and S2. The comparator circuit 120 can compare the signals S1 and S2 to generate a decision signal SD. In response to the decision signal SD, the controller circuitry 130 generates a digital code d B-1 and switches at least one of the switch capacitor array 114A and / or the switch capacitor array 114B. In this way, the switch capacitor array 114A and the switch capacitor array 114B can update the signals S1 and S2, and the comparator circuit 120 can again compare the signals S1 and S2 to generate a new decision signal SD. In response to the decision signal SD, the controller circuitry 130 generates a digital code d B-2 and switches at least one of the switch capacitor array 114A and / or the switch capacitor array 114B. In this way, the switch capacitor array 114A and the switch capacitor array 114B can update the signals S1 and S2, and the comparator circuit 120 can again compare the signals S1 and S2 to generate a new decision signal SD. In response to the decision signal SD, the controller circuitry 130 generates a digital code d B-1 , d B-2 , …, d1, d0) are generated according to the decision signals.​

[0045] In operation S340, the controller circuit is controlled to repeatedly compare the first signal and the second signal to generate a plurality of decision signals corresponding to a plurality of output comparison results. In operation S350, a second digital code is determined according to the plurality of decision signals corresponding to the plurality of output comparison results and the statistical noise value.

[0046] For example, after generating the plurality of digital codes d B-1 , d B-2 , …, d1, d0, a residual voltage V res may be left on the digital-to-analog converter circuit 114. In other words, after generating the plurality of digital codes d B-1 , d B-2 , …, d1, d0, the signal S1 and the signal S2 outputted by the digital-to-analog converter circuit 114 can be used to reflect the residual voltage V res . The controller circuitry 130 can control the comparator circuit 120 to repeatedly compare the signal S1 and the signal S2 to generate n2 decision signals SD corresponding to n2 output comparison results. Referring to the aforementioned equation (3), the controller circuitry 130 can perform a statistical operation (i.e., maximum likelihood estimation) using a value k2 to obtain the residual voltage V res , for example, as the following equation (5), where the value k2 is the number of signals among the n2 decision signals SD having a preset logic value (e.g., logic value 1):

[0047]

[0048] Further, the controller circuitry 130 can convert the residual voltage V res to a second digital code D res using the following equation (6), where the second digital code D res may be a signal having a plurality of bits:

[0049]

[0050] In operation S360, the first digital codes and the second digital code are combined to generate a digital output. For example, the controller circuitry 130 can combine the plurality of digital codes d B-1 , d B-2 , …, d1, d0 (denoted as d B-1 d B-2 …d1d0) and sum the combined digital codes and the second digital code D res to generate a digital output DO, which can be represented as the following equation (7):

[0051] DO = d B-1 d B-2 …d1d0 + D res … (7).

[0052] By the above operations, the resolution of the SAR ADC 100 can be effectively improved. For example, in one embodiment, if the SAR ADC 100 does not use the above statistical operation or other correction mechanisms, the signal-to-noise ratio of the digital output DO is about 51.7 decibels (dB). By the above operations, the signal-to-noise ratio of the digital output DO can be improved to about 55.3 dB.

[0053] The above description of the SAR ADC 100 is merely an example, and the present application is not limited thereto. In other embodiments, the controller circuitry 130 can perform a non-binary search algorithm to perform the analog-to-digital conversion. In some embodiments, the controller circuit 130 can use digital signal processing, look-up tables, or other suitable means to perform the statistical operation. In some embodiments, the digital-to-analog converter circuit 114 can be other types of digital-to-analog converter circuits. For example, the digital-to-analog converter circuit 114 can be a resistor string digital-to-analog converter circuit, a current-mode digital-to-analog converter, or the like.

[0054] Figure 4 A flowchart of a signal conversion method 400 according to some embodiments of the present application is shown. In operation S410, at an initial stage, a successive approximation register analog-to-digital converter generates decision signals corresponding to a plurality of estimated comparison results based on a sample signal having an initial level, and performs a statistical operation based on the decision signals corresponding to the estimated comparison results to obtain a statistical noise value. In operation S420, the successive approximation register analog-to-digital converter generates a plurality of first digital codes based on an input signal, and generates decision signals corresponding to a plurality of output comparison results. In operation S430, a digital output is generated based on the first digital codes, the statistical noise value, and the decision signals corresponding to the output comparison results.

[0055] The above operations can be described with reference to the above embodiments, and thus will not be described again. The above operations of the signal conversion method 400 are merely examples, and the order of the operations in the examples is not limiting. The operations of the signal conversion method 400 can be appropriately added, replaced, omitted, or performed in different orders (e.g., simultaneously or partially simultaneously) without departing from the operation manner and scope of the embodiments of the present application.

[0056] In summary, the SAR ADC and the signal conversion method of some embodiments of the present application can use data that determines the actual noise during the power-up of the device, and can perform a statistical operation using the data without excessive hardware cost to effectively improve the resolution of the SAR ADC.

[0057] Although the embodiments of the present application have been described above, these embodiments are not intended to limit the present application, and a person having ordinary knowledge in the art can make various changes to the technical features of the present application based on the disclosure or implied disclosure of the present application, and all such changes can fall within the scope of the patent protection sought for the present application. In other words, the scope of the protection of the present application should be defined by the appended claims rather than the above description.

[0058] BRIEF DESCRIPTION OF DRAWINGS

[0059] 100: analog-to-digital converter

[0060] 110: sampling circuitry

[0061] 112: switch circuit

[0062] 114: digital-to-analog converter circuit

[0063] 114A, 114B: switched capacitor array

[0064] 120: comparator circuit

[0065] 130: controller circuitry

[0066] 2 0 C, 2 1 C, 2 2 C, 2 B-2 C, 2 B-1 C: capacitance

[0067] 400: signal conversion method

[0068] DO: digital output

[0069] IT1, IT2: input terminal

[0070] S1, S2: signal

[0071] S210, S220, S230, S240: operation

[0072] S310, S320, S330, S340, S350, S360: operation

[0073] S410, S420, S430: operation

[0074] SD: decision signal

[0075] SS: sampling signal

[0076] T1, T2, T3: switch

[0077] VIN: input signal

[0078] VREF: reference voltage

Claims

1. A successive approximation register type analog-to-digital converter, comprising: A sampling circuit system for generating a first signal and a second signal based on a sampled signal; A comparator circuit is used to compare the first signal with the second signal to generate multiple decision signals; as well as A controller circuit system is configured to generate a plurality of first digital codes based on the plurality of decision signals, and to control the comparator circuit to generate the plurality of decision signals corresponding to a plurality of output comparison results, so as to generate a digital output based on the plurality of first digital codes, a statistical noise value, and the plurality of decision signals corresponding to the plurality of output comparison results. The controller circuit system is further configured to control the sampling circuit system and the comparator circuit in an initial stage, wherein the comparator circuit generates the plurality of decision signals corresponding to the plurality of estimated comparison results based on the sampling signal having an initial level, and the controller circuit system performs a statistical operation based on the plurality of decision signals corresponding to the plurality of estimated comparison results to obtain the statistical noise value.

2. The sequential approximation register type analog-to-digital converter according to claim 1, characterized in that, The sampling circuit system is configured to receive an input signal from a first input terminal and a second input terminal to generate the sampling signal, and the sampling circuit system is further configured to couple the first input terminal to the second input terminal in the initial stage to generate the sampling signal having the initial level.

3. The sequential approximation register type analog-to-digital converter according to claim 1, characterized in that, The sampling circuit system includes a digital-to-analog converter circuit, and the controller circuit system is configured to switch a component in the digital-to-analog converter circuit to receive a reference voltage during the initial phase, to generate the first signal and the second signal based on the sampling signal having the initial level, and to control the comparator circuit to repeatedly compare the first signal and the second signal to generate the plurality of decision signals corresponding to the plurality of estimation comparison results.

4. The sequential approximation register type analog-to-digital converter according to claim 3, characterized in that, The component is the component with the lowest weight in the digital-to-analog converter circuit.

5. The sequential approximation register type analog-to-digital converter according to claim 1, characterized in that, The statistical operation is a maximum likelihood estimate.

6. The sequential approximation register type analog-to-digital converter according to claim 1, characterized in that, The controller circuit system is used to perform the statistical operation based on a numerical value to determine the statistical noise value, wherein the numerical value is the number of signals with a preset logic value among the plurality of decision signals corresponding to the plurality of estimation comparison results.

7. The sequential approximation register type analog-to-digital converter according to claim 1, characterized in that, The controller circuit system is used to control the comparator circuit to repeatedly compare the first signal with the second signal after generating the plurality of first digital codes, so as to generate the plurality of decision signals corresponding to the plurality of output comparison results.

8. The sequential approximation register type analog-to-digital converter according to claim 1, characterized in that, The controller circuit system is used to determine a second digital code based on a numerical value and the statistical noise value, and to combine the plurality of first digital codes and the second digital code to generate the digital output, wherein the numerical value is the number of signals with a preset logic value among the plurality of decision signals corresponding to the plurality of output comparison results.

9. The successive approximation register type analog-to-digital converter according to claim 8, characterized in that, The controller circuit system is used to perform a statistical operation based on the numerical value and the statistical noise value to determine the second digital code.

10. A signal conversion method, comprising: In an initial stage, a successive approximation register analog-to-digital converter generates multiple decision signals corresponding to multiple estimation comparison results based on a sampled signal having an initial level, and performs a statistical operation based on the multiple decision signals corresponding to the multiple estimation comparison results to obtain a statistical noise value. The sequential approximation register analog-to-digital converter generates a plurality of first digital codes based on an input signal and generates a plurality of decision signals corresponding to a plurality of output comparison results. as well as A digital output is generated based on the plurality of first digital codes, the statistical noise value, and the plurality of decision signals corresponding to the plurality of output comparison results.

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