Capacitor structure and method of making the same

Abstract

A capacitor structure and a method of fabricating the same are disclosed. The capacitor structure includes an insulating layer and a capacitor cell. The capacitor cell is disposed on the insulating layer and includes a first electrode, a second electrode, a first dielectric layer, and a patterned conductive layer. The second electrode is disposed above the first electrode in a vertical direction. The first dielectric layer is disposed between the first electrode and the second electrode in the vertical direction. The patterned conductive layer is disposed between the first electrode and the second electrode, the patterned conductive layer is electrically connected to the first electrode, and the first dielectric layer surrounds the patterned conductive layer in a horizontal direction.

Description

TECHNICAL FIELD

[0001] The present invention relates to a capacitor structure and a method of fabricating the same, and more particularly to a capacitor structure with a patterned conductive layer disposed between two electrodes and a method of fabricating the same. BACKGROUND

[0002] In modern society, micro-processing systems composed of integrated circuits (ICs) have been widely used in various aspects of life. Many electronic devices, such as personal computers, mobile phones, and home appliances, all have applications of integrated circuits. With the increasing advancement of technology and the continuous development of emerging electronic products, integrated circuits are also developing towards diversification, miniaturization, and precision.

[0003] In current electronic products, various semiconductor technologies are used to form circuit elements on a silicon substrate, such as metal oxide semiconductor transistors (MOS transistors), capacitors, or resistors. Various circuit elements can be electrically connected to each other to form a complex circuit system. Generally, a capacitor structure can be composed of an upper electrode, a dielectric layer, and a lower electrode. The conventional capacitor structure is disposed in the inter-metal dielectric layer (IMD layer) above the silicon substrate and has a metal-insulator-metal (MIM) structure. However, as the functionality and performance requirements of electronic products continue to increase, the complexity and integration of integrated circuits also increase accordingly. Therefore, how to integrate the fabrication method or / and structural design of the capacitor structure and other elements (such as transistors) to meet product requirements has always been the research direction of relevant professionals. SUMMARY

[0004] The present invention provides a capacitor structure and a method of fabricating the same. A dielectric layer and a patterned conductive layer are disposed between two electrodes of a capacitor unit, and the dielectric layer surrounds the patterned conductive layer. Thus, the related fabrication process of the capacitor unit is simplified, and the fabrication process integration between the capacitor unit and other semiconductor elements is improved.

[0005] An embodiment of the present application provides a capacitor structure, comprising an insulating layer and a capacitor unit, wherein the capacitor unit is disposed on the insulating layer. The capacitor unit comprises a first electrode, a second electrode, a first dielectric layer and a patterned conductive layer. The second electrode is disposed above the first electrode in a vertical direction. The first dielectric layer is disposed between the first electrode and the second electrode in the vertical direction. The patterned conductive layer is disposed between the first electrode and the second electrode. The patterned conductive layer is electrically connected to the first electrode, and the first dielectric layer surrounds the patterned conductive layer in a horizontal direction.

[0006] An embodiment of the present application provides a method for manufacturing a capacitor structure, comprising the following steps. A capacitor unit is formed on an insulating layer. The capacitor unit comprises a first electrode, a second electrode, a first dielectric layer and a patterned conductive layer. The second electrode is disposed above the first electrode in a vertical direction. The first dielectric layer is disposed between the first electrode and the second electrode in the vertical direction. The patterned conductive layer is disposed between the first electrode and the second electrode. The patterned conductive layer is electrically connected to the first electrode, and the first dielectric layer surrounds the patterned conductive layer in a horizontal direction. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 FIG. 1 is a schematic diagram of a capacitor structure according to an embodiment of the present application;

[0008] Figures 2 to 7 FIG. 2 is a schematic diagram of a method for manufacturing a capacitor structure according to an embodiment of the present application;

[0009] Figure 3 FIG. 3 is a schematic diagram of a subsequent state of the method for manufacturing a capacitor structure according to the embodiment of the present application; Figure 2 FIG. 4 is a schematic diagram of a subsequent state of the method for manufacturing a capacitor structure according to the embodiment of the present application;

[0010] Figure 4 FIG. 5 is a schematic diagram of a subsequent state of the method for manufacturing a capacitor structure according to the embodiment of the present application; Figure 3 FIG. 6 is a schematic diagram of a subsequent state of the method for manufacturing a capacitor structure according to the embodiment of the present application;

[0011] Figure 5 FIG. 7 is a schematic diagram of a subsequent state of the method for manufacturing a capacitor structure according to the embodiment of the present application; Figure 4 FIG. 8 is a schematic diagram of a subsequent state of the method for manufacturing a capacitor structure according to the embodiment of the present application;

[0012] Figure 6 FIG. 9 is a schematic diagram of a subsequent state of the method for manufacturing a capacitor structure according to the embodiment of the present application; Figure 5 FIG. 10 is a schematic diagram of a subsequent state of the method for manufacturing a capacitor structure according to the embodiment of the present application;

[0013] Figure 7 FIG. 11 is a schematic diagram of a subsequent state of the method for manufacturing a capacitor structure according to the embodiment of the present application; Figure 6 FIG. 12 is a schematic diagram of a subsequent state of the method for manufacturing a capacitor structure according to the embodiment of the present application;

[0014] Figure 8 FIG. 13 is a schematic diagram of a method for manufacturing a capacitor structure according to another embodiment of the present application;

[0015] Figure 9 FIG. 14 is a schematic diagram of a capacitor structure according to a second embodiment of the present application;

[0016] Figure 10 Schematic view of a capacitor structure according to a third embodiment of the application;

[0017] Figure 11 Schematic view of a capacitor structure according to a fourth embodiment of the application.

[0018] Explanation of main element symbols

[0019] 10 substrate

[0020] 20 III-V compound layer

[0021] 21 III-V compound layer

[0022] 22 insulating layer

[0023] 32 first conductive layer

[0024] 34 second conductive layer

[0025] 34P patterned conductive layer

[0026] 36 third conductive layer

[0027] 40 dielectric material

[0028] 40A first portion

[0029] 40B second portion

[0030] 41 underlayer

[0031] 42 dielectric material

[0032] 43 dielectric material

[0033] 44 dielectric material

[0034] 45 dielectric material

[0035] 46 dielectric material

[0036] 80 patterned mask layer

[0037] 91 patterning process

[0038] 92 etching process

[0039] 93 processing

[0040] 101 capacitor structure

[0041] 102 capacitor structure

[0042] 103 capacitor structure

[0043] 104 capacitor structure

[0044] BE first electrode

[0045] BS bottom surface

[0046] CP capacitor cell

[0047] CR chloride residue

[0048] CS1 connection structure

[0049] CS2 connection structure

[0050] CS3 connection structure

[0051] CS4 connection structure

[0052] CT1 contact structure

[0053] CT2 contact structure

[0054] CT3 contact structure

[0055] CT4 contact structure

[0056] CT5 contact structure

[0057] D1 first direction

[0058] D2 second direction

[0059] DL1 first dielectric layer

[0060] DL2 second dielectric layer

[0061] G gap

[0062] GE gate structure

[0063] GT transistor cell

[0064] OP1 opening

[0065] OP2 opening

[0066] OP3 opening

[0067] SD source / drain structure

[0068] ST stack structure

[0069] TE second electrode

[0070] TS top surface

[0071] W1 width

[0072] W2 width DETAILED DESCRIPTION

[0073] The following detailed description of the application discloses sufficient information to enable those skilled in the art to practice the application. The embodiments set forth in the following description are illustrative and not restrictive in nature. Various modifications and changes can be made thereto without departing from the spirit and scope of the application, which is set forth in the appended claims.

[0074] Before further description of the embodiments, the following terms are first defined for use throughout the specification.

[0075] The terms "on," "over," and "above" are to be interpreted in the broadest context to mean not only "directly on" something but also to include the meaning of being on something with other intervening features or layers therebetween, and not only "over" or "above" something but also to include the meaning of being "over" or "above" something with no other intervening features or layers therebetween (i.e., directly on something).

[0076] The use of ordinal terms such as "first," "second," etc., in the specification and claims to modify an element of the application does not in itself connote any priority or order of one element to another, or to the process disclosed, but rather the use of such terms is merely intended to identify various elements as they are described with respect to the requirements of the written description and for the reader's convenience. Unless otherwise indicated, the use of relational terms, if any, such as "coupled," "attached," "connected," "interfaced," and / or the like are used solely to describe one element's relationship to another element(s) as a non-limiting identification of a physical or logical position relationship or connection between two or more elements and / or does not convey any other type of relationship, such as an electrical or magnetic relationship.

[0077] The term "etching" is used herein generally to describe a fabrication process to pattern a material such that at least a portion of the material is left after the etching is complete. When a material is "etched," at least a portion of the material can be left after the etching is complete. In contrast, when a material is "removed," substantially all of the material can be removed during the process. However, in some embodiments, "removed" can be considered a broad term that includes etching.

[0078] The terms "forming" or "depositing" are used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any workable layer forming technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0079] Reference is made to Figure 1 . Figure 1 A schematic diagram of a capacitor structure 101 is shown as a first embodiment of the application. As shown in FIG. 1, the capacitor structure 101 includes a substrate 102, a first electrode 104, a dielectric layer 106, and a second electrode 108. The substrate 102 can be any suitable substrate, such as a semiconductor substrate, a glass substrate, a ceramic substrate, etc. The first electrode 104 can be any suitable electrode, such as a metal electrode, a conductive oxide electrode, etc. The dielectric layer 106 can be any suitable dielectric layer, such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, etc. The second electrode 108 can be any suitable electrode, such as a metal electrode, a conductive oxide electrode, etc. Figure 1As shown, the capacitor structure 101 includes an insulating layer 22 and a capacitor cell CP. The capacitor cell CP is disposed on the insulating layer 22, and the capacitor cell CP includes a first electrode BE, a second electrode TE, a first dielectric layer DL1, and a patterned conductive layer 34P. The second electrode TE is disposed on the first electrode BE in a vertical direction (e.g., a first direction D1 as shown in Figure 1 FIG. 1), the first dielectric layer DL1 is disposed between the first electrode BE and the second electrode TE in the first direction D1, and the patterned conductive layer 34P is disposed between the first electrode BE and the second electrode TE. The patterned conductive layer 34P is electrically connected to the first electrode BE, and the first dielectric layer DL1 surrounds the patterned conductive layer 34P in a horizontal direction (e.g., a second direction D2 as shown in Figure 1 FIG. 2 or other direction orthogonal to the first direction D1). By disposing the patterned conductive layer 34P, a gap between the first electrode BE and the second electrode TE can be created by removing portions of the patterned conductive layer 34P, and the first dielectric layer DL1 can be disposed in the gap to form the capacitor cell CP. Thus, the fabrication process of the capacitor cell CP can be integrated with the fabrication process of the dielectric layer in other elements (e.g., transistors, etc.), and thus the design flexibility in the related structure or / and fabrication process integration can be improved.

[0080] In some embodiments, the first direction D1 described above can be considered as a thickness direction of the insulating layer 22, and the insulating layer 22 can have a top surface TS and a bottom surface BS opposite to each other in the first direction D1, and the capacitor cell CP can be disposed on one side of the top surface TS, but not limited thereto. The horizontal direction (e.g., the second direction D2 as shown in Figure 1 FIG. 2 and other direction orthogonal to the first direction D1) substantially orthogonal to the first direction D1 can be substantially parallel to the top surface TS or / and the bottom surface BS of the insulating layer 22, but not limited thereto. In addition, in this document, the distance in the first direction D1 between a relatively higher position or / and component in a vertical direction (e.g., the first direction D1) and the bottom surface BS of the insulating layer 22 can be greater than the distance in the first direction D1 between a relatively lower position or / and component in the vertical direction (e.g., the first direction D1) and the bottom surface BS of the insulating layer 22, the lower part or bottom of a component can be closer to the bottom surface BS of the insulating layer 22 in the first direction D1 than the upper part or top of the component, another component above a certain component can be considered as relatively farther away from the bottom surface BS of the insulating layer 22 in the first direction D1, and another component below a certain component can be considered as relatively closer to the bottom surface BS of the insulating layer 22 in the first direction D1, but not limited thereto.

[0081] In some embodiments, the patterned conductive layer 34P can be physically and electrically directly connected with the first electrode BE, and the patterned conductive layer 34P can be physically and electrically separated from the second electrode TE, and the first dielectric layer DL1 can directly contact the first electrode BE, the second electrode TE, and the patterned conductive layer 34P, but the application is not limited thereto. In some embodiments, the first electrode BE and the second electrode TE can overlap in the first direction D1, and the area of the region where the first electrode BE and the second electrode TE overlap in the first direction D1 can be substantially equal to the projected area of the second electrode TE in the first direction D1, but the application is not limited thereto. In addition, in some embodiments, the center point of the projected area of the first electrode BE in the first direction D1 can overlap the patterned conductive layer 34P in the first direction D1, and the first dielectric layer DL1 disposed between the first electrode BE and the second electrode TE can be located on two opposite sides of the patterned conductive layer 34P in the horizontal direction (for example, the second direction D2), but the application is not limited thereto.

[0082] In some embodiments, the materials of the first electrode BE and the second electrode TE can respectively include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or other suitable conductive materials. In addition, in order to remove part of the patterned conductive layer 34P to generate a gap between the first electrode BE and the second electrode TE, and to form the first dielectric layer DL1 in the gap to form the capacitor unit CP, the patterned conductive layer 34P, the first electrode BE, and the second electrode TE need to have a required etching selectivity in a specific etching manufacturing process, so the material composition of the patterned conductive layer 34P can be different from the material composition of the first electrode BE and the material composition of the second electrode TE. For example, the patterned conductive layer 34P can include aluminum, an aluminum-containing compound, or other materials that can form a required etching selectivity with the material of the first electrode BE and the material of the second electrode TE, and when the material of the patterned conductive layer 34P is aluminum, the materials of the first electrode BE and the second electrode TE can be titanium or titanium nitride, but the application is not limited thereto.

[0083] In some embodiments, the capacitor structure 101 can further include a second dielectric layer DL2 disposed on the insulating layer 22 and covering the capacitor cell CP, and the material composition of the second dielectric layer DL2 can be the same as that of the first dielectric layer DL1. In some embodiments, the second dielectric layer DL2 can cover the capacitor cell CP in the vertical direction and in the horizontal direction, and the second dielectric layer DL2 can be directly connected with the first dielectric layer DL1. For example, the first dielectric layer DL1 can be a first portion 40A of a dielectric material 40, the second dielectric layer DL2 can be a second portion 40B of the dielectric material 40, and the second portion 40B can be directly connected with the first portion 40A, and the dielectric material 40 can include a silicon oxide layer, such as a TEOS silicon oxide layer obtained by using TEOS as a precursor, or other dielectric materials with good gap-filling capability or / and high dielectric constant (high-k), thereby improving the capacitance value of the capacitor cell CP, but not limited thereto.

[0084] In some embodiments, the capacitor structure 101 can further include an opening OP1 and a contact structure CT1. The opening OP1 can be disposed on the patterned conductive layer 34P in the first direction D1 and extend through the second dielectric layer DL2 on the second electrode TE, the second electrode TE, and a portion of the first dielectric layer DL1, and a bottom of the opening OP1 can be connected to the patterned conductive layer 34P. In addition, the contact structure CT1 can be partially disposed in the opening OP1, and the contact structure CT1 can be electrically connected to the first electrode BE through the patterned conductive layer 34P. In some embodiments, the capacitor structure 101 can further include a liner layer 41, a dielectric material 42, and a contact structure CT2. The liner layer 41 can be disposed on the second dielectric layer DL2 and partially disposed in the opening OP1, and the dielectric material 42 can be disposed on the liner layer 41 and partially disposed in the opening OP1, so that a portion of the liner layer 41 and a portion of the dielectric material 42 can be disposed on the patterned conductive layer 34P in the first direction D1. In addition, an opening OP2 can extend through the dielectric material 42 and the liner layer 41 on the patterned conductive layer 34P in the first direction D1, and another opening OP3 can extend through the dielectric material 42, the liner layer 41, and the second dielectric layer DL2 on the second electrode TE in the first direction D1. The contact structure CT1 and the contact structure CT2 can be disposed in the openings OP2 and OP3, respectively, and the contact structure CT1 and the contact structure CT2 can be in contact with the patterned conductive layer 34P and the second electrode TE, respectively, to form electrical connections, and the opening OP2 can be partially located in the opening OP1. In some embodiments, a portion of the liner layer 41 or / and a portion of the dielectric material 42 can be located between the contact structure CT1 and the second electrode TE in a horizontal direction (e.g., the second direction D2) to electrically isolate the contact structure CT1 and the second electrode TE.

[0085] In some embodiments, the insulating layer 22 can include silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating materials. The liner layer 41 can include nitride (e.g., silicon nitride) or other suitable insulating materials. The dielectric material 42 can include silicon oxide, low dielectric constant (low-k) dielectric material, or other suitable dielectric materials. The low-k dielectric material described above can be used to reduce the electrical influence between the contact structure CT1 and the contact structure CT2, so the material composition of the dielectric material 42 can be different from that of the dielectric material 40, and the dielectric constant of the dielectric material 42 can be lower than that of the dielectric material 40, but the disclosure is not limited thereto. In addition, the contact structure CT1 and the contact structure CT2 can include a barrier layer (not shown) and a low-resistance material layer (not shown), the barrier layer can include titanium nitride, tantalum nitride, or other suitable conductive barrier materials, and the low-resistance material layer can include a relatively low-resistance material such as copper, aluminum, tungsten, or the like, but the disclosure is not limited thereto.

[0086] In some embodiments, the capacitor structure 101 can further include a III-V compound layer 20, and the insulating layer 22 can be disposed on the III-V compound layer 20 in the first direction Dl. In some embodiments, part of the III-V compound layer 20 can be used to form part of a III-V compound transistor structure (e.g., a gallium nitride transistor), and the III-V compound layer 20 can include multiple III-V compound layers (e.g., a gallium nitride semiconductor layer, an aluminum gallium nitride layer, etc.) disposed in the first direction Dl, but the application is not limited in this regard. In some embodiments, the first dielectric layer DLl in the capacitor cell CP and the second dielectric layer DL2 covering the capacitor cell CP can be integrated with the fabrication process of the dielectric layer in the III-V compound transistor structure or on the III-V compound transistor structure, thereby achieving the effect of simplifying the fabrication process, but the application is not limited in this regard. In some embodiments, the structure or / and the fabrication process of the capacitor cell CP described above can also be integrated with the structure or / and the fabrication process of other types of active (active) elements or / and passive (passive) elements as needed.

[0087] Please refer to Figures 2 to 7 and Figure 1 . Figures 2 to 7 The schematic diagram of the method for fabricating the capacitor structure of an embodiment of the application is shown, wherein Figure 3 is shown, Figure 2 is shown, Figure 4 is shown, Figure 3 is shown, Figure 5 is shown, Figure 4 is shown, Figure 6 is shown, Figure 5 is shown, Figure 7 is shown, Figure 6 is shown, and Figure 1 can be regarded as showing the schematic diagram of the situation after Figure 7 , but the application is not limited in this regard. As Figure 1 shown, the method for fabricating the capacitor structure 101 of the embodiment can include the following steps. Forming a capacitor cell CP on the insulating layer 22, and the capacitor cell CP includes a first electrode BE, a second electrode TE, a first dielectric layer DLl, and a patterned conductive layer 34P. The second electrode TE is disposed above the first electrode BE in the vertical direction (e.g., the first direction Dl), the first dielectric layer DLl is disposed between the first electrode BE and the second electrode TE in the first direction Dl, and the patterned conductive layer 34P is disposed between the first electrode BE and the second electrode TE. The patterned conductive layer 34P is electrically connected to the first electrode BE, and the first dielectric layer DLl surrounds the patterned conductive layer 34P in the horizontal direction (e.g., the second direction D2).

[0088] Further note that the method of fabricating the capacitor structure 101 of the present embodiment can include, but is not limited to, the following steps. First, as shown in Figures 2 to 3 the stack structure ST can include a first electrode BE, a patterned conductive layer 34P, and a second electrode TE stacked on the insulating layer 22 in sequence. In some embodiments, the method of forming the stack structure ST can include, but is not limited to, the following steps. A first conductive layer 32 is formed on the insulating layer 22, a second conductive layer 34 is formed on the first conductive layer 32, and a third conductive layer 36 is formed on the second conductive layer 34. Then, a patterning process 91 is performed on the third conductive layer 36, the second conductive layer 34, and the first conductive layer 32, at least a portion of the third conductive layer 36 can be patterned by the patterning process 91 to become the second electrode TE, at least a portion of the second conductive layer 34 can be patterned by the patterning process 91 to become the patterned conductive layer 34P, and at least a portion of the first conductive layer 32 can be patterned by the patterning process 91 to become the first electrode BE. In some embodiments, a patterned mask layer 80 can be formed on the third conductive layer 36, and the patterning process 91 can be performed using the patterned mask layer 80 as an etching mask, and the patterning process 91 can include one or more etching steps to etch the third conductive layer 36, the second conductive layer 34, and the first conductive layer 32, respectively, but the present embodiment is not limited thereto. In some embodiments, since the first electrode BE, the patterned conductive layer 34P, and the second electrode TE in the stack structure ST can be formed by etching using the patterned mask layer 80, the first electrode BE, the patterned conductive layer 34P, and the second electrode TE in the stack structure ST can overlap with each other in the first direction D1 and have substantially the same projected area, but the present embodiment is not limited thereto. In addition, the patterned mask layer 80 can be removed after the stack structure ST is formed.

[0089] Then, as shown in Figures 2 to 4As shown, a portion of the patterned conductive layer 34P is removed by an etching fabrication process 92 to form a gap G between the first electrode BE and the second electrode TE. In some embodiments, the etching fabrication process 92 can include reacting a chloride residue CR on the stack structure ST with water (e.g., deionized water, DI water) to remove a portion of the patterned conductive layer 34P to form the gap G. For example, when the material of the patterned conductive layer 34P is aluminum or an aluminum-containing compound, the chloride residue CR can include aluminum chloride (e.g., AICI3), and the reaction of aluminum chloride with water can form hydrochloric acid (HC1), which can react with the aluminum of the patterned conductive layer 34P to form aluminum chloride, so that the etching effect on the patterned conductive layer 34P can be caused by using this reaction mechanism, but not limited thereto. In some embodiments, other etching methods having a suitable etching selectivity between the patterned conductive layer 34P and the first electrode BE and the second electrode TE can also be used to form the gap G according to design requirements. In addition, in some embodiments, the patterning fabrication process 91 can include a dry etching step, the above-mentioned chloride residue CR can be generated by the patterning fabrication process 91, and the gas used in the patterning fabrication process 91 (e.g., the reaction gas used in the above-mentioned dry etching step) can include a chlorine-containing gas, but not limited thereto. It is worth noting that after the gap G is formed, the remaining patterned conductive layer 34P still needs to directly contact the first electrode BE and the second electrode TE, thereby achieving the effect of supporting the second electrode TE.

[0090] As Figures 4 to 6As shown, a first dielectric layer DL1 can be formed in the void G. In some embodiments, the method of forming the first dielectric layer DL1 may include forming a dielectric material 40 on the insulating layer 22. A portion of the dielectric material 40 (e.g., a first portion 40A) may be formed in the void G, while another portion of the dielectric material 40 (e.g., a second portion 40B) may be formed on the stacked structure ST. The first dielectric layer DL1 may include the dielectric material 40 formed in the void G (e.g., the first portion 40A of the dielectric material 40), while the second portion 40B of the dielectric material 40 may be considered as a second dielectric layer DL2, but is not limited thereto. After the dielectric material 40 is formed, an opening OP1 may be formed on the patterned conductive layer 34P. The opening OP1 may penetrate the dielectric material 40 and the second electrode TE on the stacked structure ST in the first direction D1, and a portion of the patterned conductive layer 34P may be removed by the step of forming the opening OP1 to separate the patterned conductive layer 34P from the second electrode TE. In other words, after the dielectric material 40 is formed and before the opening OP1 is formed, the patterned conductive layer 34P can be directly connected to the second electrode TE, and after the opening OP1 is formed, the patterned conductive layer 34P can be separated from the second electrode TE, thereby forming the capacitor unit CP. In some embodiments, in order to ensure that the patterned conductive layer 34P is partially removed to avoid electrical connection between the patterned conductive layer 34P and the second electrode TE, the bottom width of the opening OP1 (e.g., Figure 6 The width W1 shown may be greater than or equal to the width W2 of the patterned conductive layer 34P, but is not limited thereto. It is worth noting that the method for fabricating the capacitor unit CP in this embodiment may include, but is not limited to, the method described above. Figures 2 to 6 The manufacturing steps are described above, and other suitable manufacturing methods can be used to form the capacitor unit CP as needed based on the design. Furthermore, through the above... Figures 2 to 6 When forming the capacitor cell CP in the manufacturing process, the capacitance value of the capacitor cell CP can be adjusted by changing the thickness of the second conductive layer 34. Therefore, it is not necessary to change the corresponding layout pattern in order to meet the requirements of different products, thereby reducing the related design and / or manufacturing costs.

[0091] like Figure 7 As shown, after the opening OP1 and the capacitor unit CP are formed, a liner 41 and a dielectric material 42 can be formed. The liner 41 can be conformally formed on the second dielectric layer DL2 and in the opening OP1, while the dielectric material 42 can be formed on the liner 41 and fill the opening OP1. Figure 7 and Figure 1As shown, after the dielectric material 42 is formed, the opening OP2, the opening OP3, the contact structure CT1 and the contact structure CT2 can be formed. In some embodiments, the liner 41 can serve as an etch stop layer when forming the opening OP2, thereby improving the depth control condition for the opening OP2, but not limited thereto. In some embodiments, the dielectric material 42 can also be formed directly after the opening OP1 is formed without forming the liner 41.

[0092] Different embodiments of the present application will be described below, and for simplicity of explanation, the following description mainly focuses on the different parts of each embodiment and does not repeat the same parts. In addition, the same elements in different embodiments of the present application are labeled with the same reference numerals for easy cross-referencing between different embodiments.

[0093] Please refer to Figure 8 and Figures 2 to 4 . Figure 8 The schematic diagram of the method for fabricating the capacitor structure of another embodiment of the present application is shown. As Figure 8 may be considered as a schematic diagram showing the condition after Figure 2 and Figure 3 , but not limited thereto. As Figure 2 and Figure 8 shown, in some embodiments, a treatment 93 can be performed after the patterning fabrication process 91 (i.e. after the formation of the stack structure ST) to form chloride residues CR on the stack structure ST, for example, the chloride residues CR can be formed on the sidewalls of the patterned conductive layer 34P, but not limited thereto. In some embodiments, the treatment 93 can include a plasma treatment or other suitable method that can be used to form the chloride residues CR on the stack structure ST, and the treatment 93 can be performed consecutively in the same fabrication chamber as the patterning fabrication process 91, but not limited thereto. Then, as Figure 8 , Figure 3 and Figure 4 shown, the patterned mask layer 80 can be removed after the treatment 93, and then the etching fabrication process 92 can be performed to remove a portion of the patterned conductive layer 34P to form the gap G. In other words, the treatment 93 can be performed after the patterning fabrication process 91 shown in Figure 2 and before the etching fabrication process 92 shown in Figure 4 , and the chloride residues CR can be generated by the treatment 93.

[0094] Please refer to Figure 9 . Figure 9 The schematic diagram of the capacitor structure 102 of the second embodiment of the present application is shown. As Figure 9As shown, in some embodiments, the capacitor structure 102 can further include a substrate 10, a III-V compound layer 21, a source / drain structure SD, a gate structure GE, a dielectric material 45, and a dielectric material 46. In some embodiments, the III-V compound layer 20 can be disposed on the substrate 10, the III-V compound layer 21 can be disposed on the III-V compound layer 20, the gate structure GE can be disposed on the III-V compound layer 21, the insulating layer 22 and the dielectric material 40 can be partially disposed on the sidewall of the III-V compound layer 21 and the sidewall of the gate structure GE, and the dielectric material 42 can be partially disposed on the gate structure GE. In addition, the source / drain structure SD can penetrate through the dielectric material 42, the dielectric material 40, and the insulating layer 22, thereby contacting the III-V compound layer 20, the dielectric material 45 can be disposed on the dielectric material 42, and the dielectric material 46 can be disposed on the dielectric material 45. In some embodiments, the substrate 10 can include a silicon substrate, a silicon carbide (SiC) substrate, a gallium nitride substrate, a sapphire substrate, or a substrate formed of other suitable materials, the III-V compound layer 21 can include a p-type doped III-V compound such as a p-type doped gallium nitride, the gate structure GE and the source / drain structure SD can include a metallic conductive material or other suitable conductive material, respectively, and the dielectric material 45 and the dielectric material 46 can include a single layer or multiple layers of dielectric material, but the scope of the application is not limited in this respect. In some embodiments, the gate structure GE, the source / drain structure SD, the III-V compound layer 21, and the III-V compound layer 20 can be considered as a part of a transistor unit GT, and the dielectric material 40 can be partially disposed in the capacitor unit CP and partially disposed in the transistor unit GT, thereby achieving a structure or / and a fabrication process that integrates the transistor unit GT and the capacitor unit CP, but the scope of the application is not limited in this respect. In some embodiments, the capacitor unit CP can be formed after the step of forming the III-V compound layer 21 and before the step of forming the gate structure GE, but the scope of the application is not limited in this respect.

[0095] In some embodiments, the capacitor structure 102 can further include a contact structure CT3, a contact structure CT4, a contact structure CT5, a connection structure CS1, a connection structure CS2, a connection structure CS3, and a connection structure CS4. The contact structure CT3 and the contact structure CT5 can respectively form electrical connections with corresponding source / drain structures SD through the dielectric material 45 and the dielectric material 46 over the source / drain structures SD, and the contact structure CT4 can form an electrical connection with the gate structure GE through the dielectric material 42, the dielectric material 45, and the dielectric material 46 over the gate structure GE. In addition, the contact structure CT1 can form an electrical connection with the patterned conductive layer 34P through the dielectric material 40, the dielectric material 42, the dielectric material 45, and the dielectric material 46 over the patterned conductive layer 34P, and the contact structure CT2 can form an electrical connection with the second electrode TE through the dielectric material 40, the dielectric material 42, the dielectric material 45, and the dielectric material 46 over the second electrode TE. In addition, each of the above-mentioned connection structures can be disposed over the dielectric material 46, the connection structure CS1, the connection structure CS3, and the connection structure CS4 can respectively form electrical connections with the contact structure CT1, the contact structure CT3, and the contact structure CT4, and the connection structure CS2 can form electrical connections with the contact structure CT2 and the contact structure CT5, such that one of the source / drain structures SD in the transistor unit GT can be electrically connected with the second electrode TE in the capacitor unit CP through the contact structure CT5, the connection structure CS2, and the contact structure CT2, but the application is not limited to this. In some embodiments, the contact structure CT3, the contact structure CT4, and the contact structure CT5 can have similar material compositions as the contact structure CT1, and each of the above-mentioned connection structures can include a metallic conductive material or other suitable conductive material.

[0096] Referring to FIG. 1, a schematic view of a capacitor structure 102 according to a first embodiment of the application is shown. As shown in FIG. 1, the capacitor structure 102 can include a substrate 10, a gate structure GE, a patterned conductive layer 34P, a second electrode TE, a dielectric material 40, a dielectric material 42, a dielectric material 45, a dielectric material 46, a contact structure CT1, a contact structure CT2, a contact structure CT3, a contact structure CT4, a contact structure CT5, a connection structure CS1, a connection structure CS2, a connection structure CS3, and a connection structure CS4. Figure 10 . Figure 10 A schematic view of a capacitor structure 103 according to a third embodiment of the application is shown. As shown in FIG. 3, the capacitor structure 103 can include a substrate 10, a gate structure GE, a patterned conductive layer 34P, a second electrode TE, a dielectric material 40, a dielectric material 42, a dielectric material 45, a dielectric material 46, a contact structure CT1, a contact structure CT2, a contact structure CT3, a contact structure CT4, a contact structure CT5, a connection structure CS1, a connection structure CS2, a connection structure CS3, and a connection structure CS4. Figure 10As shown, in some embodiments, the capacitor structure 103 may further include dielectric material 43 and dielectric material 44, which may be disposed between dielectric material 42 and dielectric material 45, and dielectric material 43 may be disposed between dielectric material 42 and dielectric material 44. In some embodiments, the capacitor cell CP may be disposed on dielectric material 42, and a portion of dielectric material 43 may be used to form the first dielectric layer DL1 in the capacitor cell CP. In some embodiments, the fabrication process of the first electrode BE, the patterned conductive layer 34P and / or the second electrode TE in the capacitor cell CP may be integrated with the fabrication process of the source / drain structure SD, thereby achieving the effect of simplified fabrication process, but is not limited thereto. In some embodiments, the first electrode BE, the patterned conductive layer 34P and / or the second electrode TE in the capacitor cell CP may be formed on dielectric material 42 after the step of forming the source / drain structure SD. In addition, in some embodiments, dielectric material 43 may include a silicon oxide layer, such as a TEOS silicon oxide layer, a high-k dielectric material or other suitable dielectric material, while dielectric material 44 may include an oxide dielectric material, a low-k dielectric material or other suitable dielectric material. Therefore, the dielectric constant of dielectric material 43 may be higher than that of dielectric material 44, but is not limited thereto.

[0097] Please see Figure 11 . Figure 11 The illustration shows a schematic diagram of the capacitor structure 104 according to a fourth embodiment of the present invention. Figure 11 As shown, in some embodiments, the capacitor cell CP may be disposed on the dielectric material 45, and the dielectric material 46 may include multiple dielectric layers, and a portion of one dielectric layer in the dielectric material 46 (e.g., the bottommost dielectric layer) may be used to form the first dielectric layer DL1 in the capacitor cell CP. In some embodiments, an interconnect structure (not shown) may be provided on the dielectric material 45, and the fabrication process of the first electrode BE, the patterned conductive layer 34P and / or the second electrode TE in the capacitor cell CP may be integrated with the fabrication process of the interconnect structure, thereby achieving the effect of simplifying the fabrication process and / or reducing the area occupied by the capacitor cell CP. The fabrication process of the capacitor cell CP may be considered as integrated into the back end of line (BEOL) fabrication process, but is not limited thereto. Furthermore, the above Figure 9 and Figure 10 The capacitor unit CP in the capacitor structure can be considered as integrated into the front end of line (FEOL), but is not limited to this.

[0098] In summary, in the capacitor structure and the manufacturing method thereof, the dielectric layer and the patterned conductive layer can be arranged between the first electrode and the second electrode of the capacitor unit, and the dielectric layer surrounds the patterned conductive layer, thereby simplifying the related manufacturing process of the capacitor unit and improving the manufacturing process integration between the capacitor unit and other semiconductor elements.

[0099] The above merely provides the preferred embodiments of the present application, and all equivalent changes and modifications made according to the claims of the present application should fall within the scope of the present application.

Claims

1. A capacitor structure, comprising: an insulating layer; and a capacitor cell disposed on the insulating layer, wherein the capacitor cell comprises: a first electrode; a second electrode disposed above the first electrode in a vertical direction; a first dielectric layer disposed between the first electrode and the second electrode in the vertical direction; a patterned conductive layer disposed between the first electrode and the second electrode, wherein the patterned conductive layer is electrically connected to the first electrode, and the first dielectric layer surrounds the patterned conductive layer in a horizontal direction; and an opening disposed above the patterned conductive layer in the vertical direction and penetrating the second electrode, wherein the opening is directly connected to the second electrode and the patterned conductive layer.

2. The capacitor structure of claim 1, wherein a material composition of the patterned conductive layer is different from a material composition of the first electrode and a material composition of the second electrode.

3. The capacitor structure of claim 1, wherein the patterned conductive layer comprises aluminum.

4. The capacitor structure of claim 1, wherein the patterned conductive layer is directly connected to the first electrode, and the patterned conductive layer is separated from the second electrode.

5. The capacitor structure of claim 1, further comprising: a contact structure partially disposed in the opening, and the contact structure is electrically connected to the first electrode through the patterned conductive layer.

6. The capacitor structure of claim 1, further comprising: a second dielectric layer disposed on the insulating layer and covering the capacitor cell, wherein a material composition of the second dielectric layer is the same as a material composition of the first dielectric layer.

7. The capacitor structure of claim 6, wherein the first dielectric layer is a first portion of a dielectric material, the second dielectric layer is a second portion of the dielectric material, and the second portion is directly connected to the first portion.

8. The capacitor structure of claim 1, wherein the horizontal direction is orthogonal to the vertical direction.

9. The capacitor structure of claim 1, further comprising: a III-V compound layer, wherein the insulating layer is disposed on the III-V compound layer.

10. A method of fabricating a capacitor structure, comprising: forming a capacitor cell on an insulating layer, wherein the capacitor cell comprises: a first electrode; a second electrode disposed above the first electrode in a vertical direction; a dielectric layer disposed between the first electrode and the second electrode in the vertical direction; a patterned conductive layer disposed between the first electrode and the second electrode, wherein the patterned conductive layer is electrically connected to the first electrode, and the dielectric layer surrounds the patterned conductive layer in a horizontal direction; and forming an opening, wherein the opening is disposed above the patterned conductive layer in the vertical direction and penetrates the second electrode, and the opening is directly connected to the second electrode and the patterned conductive layer.

11. The method of fabricating a capacitor structure of claim 10, wherein the method of forming the capacitor cell comprises: forming a stack structure on the insulating layer, wherein the stack structure comprises the first electrode, the patterned conductive layer, and the second electrode; removing a portion of the patterned conductive layer with an etching fabrication process to form a gap between the first electrode and the second electrode; and forming the dielectric layer in the gap.

12. The method of claim 11, wherein the method of forming the stack structure comprises: forming a first conductive layer on the insulating layer; forming a second conductive layer on the first conductive layer; forming a third conductive layer on the second conductive layer; and performing a patterning fabrication process on the third conductive layer, the second conductive layer, and the first conductive layer, wherein the third conductive layer is patterned by the patterning fabrication process to become the second electrode, the second conductive layer is patterned by the patterning fabrication process to become the patterned conductive layer, and the first conductive layer is patterned by the patterning fabrication process to become the first electrode.

13. The method of claim 12, wherein the etching fabrication process comprises reacting water with chloride residues on the stack structure to remove the portion of the patterned conductive layer.

14. The method of claim 13, wherein the chloride residues are generated by the patterning fabrication process, and a gas used in the patterning fabrication process comprises a chlorine-containing gas.

15. The method of claim 13, further comprising: performing a treatment after the patterning fabrication process and before the etching fabrication process, wherein the chloride residues are generated by the treatment.

16. The method of claim 11, wherein the method of forming the dielectric layer comprises: forming a dielectric material on the insulating layer, wherein a portion of the dielectric material is formed in the gap, another portion of the dielectric material is formed on the stack structure, and the dielectric layer comprises the dielectric material formed in the gap.

17. The method of claim 16, wherein the opening is formed on the patterned conductive layer after the dielectric material is formed, and the opening penetrates the dielectric material on the stack structure in the vertical direction.

18. The method of claim 17, wherein the patterned conductive layer directly connects the second electrode after the dielectric material is formed and before the opening is formed, and a portion of the patterned conductive layer is removed by the step of forming the opening to separate the patterned conductive layer from the second electrode.

19. The method of claim 10, wherein the patterned conductive layer comprises aluminum.

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