First-stage amplifier circuit, comparator, readout circuit and image sensor

Abstract

The present invention provides a first-stage amplifier circuit, which is applied to a comparator, and includes a first-stage amplifier unit and a clamp unit. The first-stage amplifier unit is used to compare a pixel signal and a ramp signal, and output a driving voltage; the clamp unit is connected to the first-stage amplifier unit, and is used to limit the rise of the driving voltage when the driving voltage reaches a target voltage, thereby preventing the driving voltage from rising to the power supply voltage, thereby ensuring that the second-stage input tube of the comparator always maintains a conducting state, thereby reducing the flip delay of the comparator. The present invention also provides a comparator, a readout circuit, and an image sensor.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and in particular to a first-stage amplifier circuit, a comparator, a readout circuit and an image sensor. Background Art

[0002] CMOS image sensor (CIS) has been widely used in imaging fields such as video, surveillance, industrial manufacturing, automobiles, and home appliances. The mainstream readout circuit structure of CIS is a readout circuit based on analog-to-digital converter (SS-ADC). The function of SS-ADC is to compare the signal to be quantized with a ramp reference signal. The comparison result is finally quantized through a counter to obtain an N-bit binary digital quantity. One of the most core circuits in SS-ADC is the comparator. The function of the comparator is to judge the size of the ramp signal voltage and the signal voltage to be quantized, and output a "1" or "0" signal as the basis for subsequent counter quantization. The CIS comparator has two stages. The first stage is the first-stage amplifier circuit, which provides a certain gain to quickly distinguish the difference in input signals. The second stage is the first-stage amplifier circuit, which also provides a certain gain and makes the output reach a larger swing. The SS-ADC comparison judgment has two stages. The first stage converts the reset potential data, and the second stage converts the integral signal potential data. During the operation of SS-ADC, the ramp signal will be raised first so that it can intersect with the pixel output signal for comparison and judgment. However, when the ramp signal is higher than the pixel output signal, the output potential of the first-stage amplifier circuit of the comparator will be pulled close to the power supply voltage, which will cause the second-stage input tube of the comparator to be cut off and no current will flow through it. At this time, the IR drop of the power supply line will decrease until the ramp signal is lower than the pixel output signal, that is, when the first stage of the comparator is flipped, the second-stage input tube will enter the on state, which will increase the flip delay of the comparator.

[0003] Therefore, it is necessary to provide a novel first-stage amplifier circuit, comparator, readout circuit and image sensor to solve the above problems existing in the prior art. Summary of the invention

[0004] The object of the present invention is to provide a first-stage amplifier circuit, a comparator, a readout circuit and an image sensor to reduce the flip delay of the comparator.

[0005] To achieve the above object, the first-stage amplifier circuit of the present invention is applied to a comparator and includes:

[0006] a first-stage amplification unit, used for comparing the pixel signal and the ramp signal, and outputting a driving voltage; and

[0007] The clamping unit is connected to the first-stage amplifying unit and is used for limiting the rise of the driving voltage when the driving voltage reaches the target voltage.

[0008] The beneficial effect of the first-stage amplifier circuit is that the clamping unit is connected to the first-stage amplifier unit and is used to limit the rise of the driving voltage when the driving voltage reaches the target voltage, thereby preventing the driving voltage from rising to the power supply voltage, thereby ensuring that the second-stage input tube of the comparator always maintains a conductive state, thereby reducing the flip delay of the comparator.

[0009] Optionally, the first-stage amplifying unit includes a current mirror circuit, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first capacitor and a second capacitor. The drain of the first NMOS tube is connected to the first output end of the current mirror circuit, and the drain of the second NMOS tube is connected to the second output end of the current mirror circuit. As the output end of the first-stage amplifying unit, the source of the first NMOS tube and the source of the second NMOS tube are both connected to the drain of the third NMOS tube, and the source of the third NMOS tube is grounded. The gate of the first NMOS tube is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the ramp signal. The gate of the second NMOS tube is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the pixel signal. The gate of the third NMOS tube is connected to the first control signal.

[0010] Optionally, the clamping unit includes a first PMOS tube, a source of the first PMOS tube is connected to a drain of the second NMOS tube, a drain of the first PMOS tube is connected to a drain of the third NMOS tube, and a gate of the first PMOS tube is connected to a drain of the first NMOS tube.

[0011] Optionally, the clamping unit includes a first PMOS tube and a fourth NMOS tube, the source of the first PMOS tube is connected to the drain of the second NMOS tube, the gate of the first PMOS tube is connected to the drain of the first NMOS tube, the drain of the first PMOS tube is connected to the drain of the fourth NMOS tube, the source of the fourth NMOS tube is connected to the drain of the third NMOS tube, and the gate of the fourth NMOS tube is connected to the second control signal.

[0012] Optionally, the first-stage amplifier circuit also includes a reset unit, which includes a second PMOS tube and a third PMOS tube, the source of the second PMOS tube is connected to the drain of the first NMOS tube, the drain of the second PMOS tube is connected to the gate of the first NMOS tube, the source of the third PMOS tube is connected to the drain of the second NMOS tube, the drain of the third PMOS tube is connected to the gate of the second NMOS tube, and the gate of the second PMOS tube and the gate of the third PMOS tube are both connected to a third control signal.

[0013] Optionally, the current mirror circuit includes a fourth PMOS tube and a fifth PMOS tube, the source of the fourth PMOS tube and the source of the fifth PMOS tube are both connected to the power supply voltage, the drain of the fourth PMOS tube is connected to the gate of the fourth PMOS tube, the gate of the fifth PMOS tube, and the drain of the first NMOS tube, and the drain of the fifth PMOS tube is connected to the drain of the second NMOS tube.

[0014] The present invention also provides a comparator, comprising:

[0015] The first stage amplifying circuit; and

[0016] The second-stage amplifier circuit includes a sixth PMOS tube, a fifth NMOS tube, a sixth NMOS tube and a third capacitor, wherein the source of the sixth PMOS tube is connected to a power supply voltage, the gate of the sixth PMOS tube is connected to the first-stage amplifier circuit, the drain of the sixth PMOS tube is connected to the drain of the fifth NMOS tube and the drain of the sixth NMOS tube, the source of the fifth NMOS tube and the gate of the sixth NMOS tube are both connected to one end of the third capacitor, the other end of the third capacitor is grounded, the gate of the fifth NMOS tube is connected to a fourth control signal, and the source of the sixth NMOS tube is grounded.

[0017] The beneficial effect of the comparator is that the first-stage method circuit is applied to avoid the driving voltage rising to the power supply voltage, thereby ensuring that the sixth PMOS tube in the second-stage amplifier circuit of the comparator always maintains the on state, thereby reducing the flip delay of the comparator.

[0018] The present invention also provides a readout circuit, comprising at least one readout unit, wherein the readout unit comprises the comparator and a counter, wherein the counter is connected to the output end of the comparator and is used to count the output signal of the comparator to output a digital signal.

[0019] The beneficial effect of the readout circuit is that: the comparator is applied, the flip delay of the comparator is small, and the accuracy of the digital signal output by the readout circuit is ensured.

[0020] The present invention also provides an image sensor, comprising:

[0021] A pixel array unit, used for outputting pixel signals after light sensing;

[0022] A decoding driving unit, connected to the pixel array unit, and used to drive the pixel array unit;

[0023] A ramp generating unit, used for generating a ramp signal;

[0024] The readout circuit is connected to the ramp generating unit and the pixel array unit;

[0025] An output signal processing unit, connected to the readout circuit, to convert the digital signal into an image and output it;

[0026] A timing control unit is connected to the decoding driving unit, the ramp generating unit, the readout circuit and the output signal processing unit, and is used to send a clock signal to the decoding driving unit, the ramp generating unit, the readout circuit and the output signal processing unit.

[0027] The beneficial effect of the image sensor is that: by applying the readout circuit, the accuracy of the digital signal output by the readout circuit is high, thereby ensuring the quality of the image output by the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of the structure of an image sensor in some embodiments of the present invention;

[0029] Figure 2 is a circuit diagram of a pixel unit in some embodiments of the present invention;

[0030] Figure 3 is a timing diagram of a pixel unit in some embodiments of the present invention;

[0031] Figure 4 is a circuit diagram of a comparator in the prior art;

[0032] Figure 5 A schematic diagram of a comparator circuit in some embodiments of the present invention;

[0033] Figure 6 It is a timing diagram of an image sensor in the prior art;

[0034] Figure 7 To adopt Figure 4 An image of a dark scene captured by an image sensor of the comparator shown;

[0035] Figure 8 To adopt Figure 5An image of a dark scene captured by the image sensor of the comparator shown. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0037] In view of the problems existing in the prior art, an embodiment of the present invention provides an image sensor. Figure 1 The image sensor 100 includes a pixel array unit 101, a readout circuit 102, a decoding driving unit 103, a ramp generating unit 104, an output signal processing unit 105 and a timing control unit 106.

[0038] Reference Figure 1 The pixel array unit 101 is used to output pixel signals after light exposure; the decoding driving unit 103 is connected to the pixel array unit 101 to drive the pixel array unit 101; the ramp generating unit 104 is used to generate a ramp signal; the readout circuit 102 is connected to the ramp generating unit 104 and the pixel array unit 101; the output signal processing unit 105 is connected to the readout circuit 102 to convert the digital signal into an image and output it; the timing control unit 106 is connected to the decoding driving unit 103, the ramp generating unit 104, the readout circuit 102 and the output signal processing unit 105 to send a clock signal to the decoding driving unit 103, the ramp generating unit 104, the readout circuit 102 and the output signal processing unit 105. The pixel array unit 101 includes at least one pixel unit 1011. The decoding driving unit 103 , the ramp generating unit 104 , the output signal processing unit 105 and the timing control unit 106 are all well-known technologies in the art and will not be described in detail herein.

[0039] Figure 2 FIG. 1 is a circuit diagram of a pixel unit in some embodiments of the present invention. Figure 2The pixel unit 1011 includes a seventh NMOS tube 10111, an eighth NMOS tube 10112, a ninth NMOS tube 10113, a tenth NMOS tube 10114 and a photodiode 10115, the drain of the seventh NMOS tube 10111 is connected to the power supply voltage VDD, the source of the seventh NMOS tube 10111 is connected to the gate of the eighth NMOS tube 10112 and the drain of the ninth NMOS tube 10113, the gate of the seventh NMOS tube 10111 is used to receive the fifth control signal RX, the source of the ninth NMOS tube 10113 is connected to the photodiode 10115, and the gate of the seventh NMOS tube 10111 is used to receive the fifth control signal RX. The cathode of the photodiode 10115 is connected, the gate of the ninth NMOS tube 10113 is used to receive the sixth control signal TX, the anode of the photodiode 10115 is grounded, the drain of the eighth NMOS tube 10112 is connected to the power supply voltage VDD, the source of the eighth NMOS tube 10112 is connected to the drain of the tenth NMOS tube 10114, the gate of the tenth NMOS tube 10114 is used to receive the seventh control signal SEL, and the source of the tenth NMOS tube 10114 is connected to the readout circuit 102 to send the pixel signal to the readout circuit 102.

[0040] Reference Figure 2 The drain of the ninth NMOS tube 10113 is connected to one end of the first connection line 10116, the gate of the ninth NMOS tube 10112 is connected to the other end of the first connection line 10116, the source of the seventh NMOS tube 10111 is connected to one end of the second connection line 10117, the other end of the second connection line 10117 is connected to the first connection line 10116, and the connection point between the second connection line 10117 and the first connection line 10116 is the floating diffusion area 10118.

[0041] Figure 3 FIG. 1 is a timing diagram of a pixel unit in some embodiments of the present invention. Figure 2 and Figure 3 , Rst represents the reset phase of the pixel unit 1011, Exp represents the exposure phase of the pixel unit 1011, Read represents the signal reading phase of the pixel unit 1011, SEL represents the seventh control signal applied to the gate of the tenth NMOS tube 10114, RX represents the fifth control signal applied to the gate of the seventh NMOS tube 10111, and TX represents the sixth control signal applied to the gate of the ninth NMOS tube 10113.

[0042] Reference Figure 2 and Figure 3When the pixel unit 1011 is in the reset stage, the seventh control signal SEL maintains a low level, the fifth control signal RX maintains a high level, and the sixth control signal TX changes from a high level to a low level. The fifth control signal RX and the sixth control signal TX are both high level, the seventh NMOS tube 10111 and the ninth NMOS tube 10113 are both turned on, and the potential of the floating diffusion area 10118 is pulled up to the power supply voltage VDD to complete the reset.

[0043] Reference Figure 2 and Figure 3 , after the fifth control signal RX and the sixth control signal TX are both changed from high level to low level, the pixel unit 1011 enters the exposure stage from the reset stage, the seventh control signal SEL maintains a low level, the fifth control signal RX maintains a low level, and the sixth control signal TX maintains a low level. The fifth control signal RX and the sixth control signal TX are both low level, the seventh NMOS tube 10111 and the ninth NMOS tube 10113 are both turned off, and the photodiode 10115 senses light and generates photoelectrons proportional to the light intensity.

[0044] Reference Figure 2 and Figure 3 , after the seventh control signal SEL changes from a low level to a high level, the tenth NMOS tube 10114 is turned on, and the pixel unit 1011 enters the signal reading stage from the exposure stage. The fifth control signal RX first changes from a low level to a high level to reset the floating diffusion area 10118. At this time, the eighth NMOS tube 10112 is controlled by the potential of the floating diffusion area 10118, and the source of the tenth NMOS tube 10114 outputs a first reset potential, and then the fifth control signal RX changes from a high level to a low level; the sixth control signal TX changes from a low level to a high level, and the photoelectrons in the photodiode 10115 are transferred to the floating diffusion area 10118. At this time, the eighth NMOS tube 10112 is controlled by the potential of the floating diffusion area 10118, and the source of the tenth NMOS tube 10114 outputs a second reset potential, and then the sixth control signal TX changes from a high level to a low level.

[0045] In some embodiments, the readout circuit includes at least one readout unit, and the readout unit includes a comparator and a counter. The counter is connected to the output end of the comparator and is used to count the output signal of the comparator to output a digital signal.

[0046] Figure 4 Schematic diagram of a comparator circuit in the prior art. Figure 5FIG. 1 is a schematic diagram of a comparator circuit in some embodiments of the present invention. Figure 4 and Figure 5 , Figure 5 and Figure 4 The difference is that a clamping unit is added.

[0047] Reference Figure 4 and Figure 5 The comparator includes a first-stage amplifier circuit 10211 and a second-stage amplifier circuit 10212. The first-stage amplifier circuit includes a first-stage amplifier unit. The first-stage amplifier unit is used to compare the pixel signal and the ramp signal and output a driving voltage.

[0048] Reference Figure 4 and Figure 5 The first-stage amplifying unit includes a current mirror circuit, a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a first capacitor C1 and a second capacitor C2. The drain of the first NMOS tube M1 is connected to the first output end of the current mirror circuit, and the drain of the second NMOS tube M2 is connected to the second output end of the current mirror circuit as the output end of the first-stage amplifying unit. The source of the first NMOS tube M1 and the source of the second NMOS tube M2 are both connected to the drain of the third NMOS tube M3. The source of the third NMOS tube M3 is grounded. The gate of the first NMOS tube M1 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the ramp signal RAMP. The gate of the second NMOS tube M2 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to the pixel signal PIX_OUT. The gate of the third NMOS tube M3 is connected to the first control signal VBN_CM.

[0049] Reference Figure 4 and Figure 5 The current mirror circuit includes a fourth PMOS tube M4 and a fifth PMOS tube M5, the source of the fourth PMOS tube M4 and the source of the fifth PMOS tube M5 are both connected to the power supply voltage VDD, the drain of the fourth PMOS tube M4 is connected to the gate of the fourth PMOS tube M4, the gate of the fifth PMOS tube M5, and the drain of the first NMOS tube M1, and the drain of the fifth PMOS tube M5 is connected to the drain of the second NMOS tube M2.

[0050] Reference Figure 5The first-stage amplifier circuit also includes a clamping unit, which includes a first PMOS tube MQ2 and a fourth NMOS tube MQ1. The source of the first PMOS tube MQ2 is connected to the drain of the second NMOS tube M2, the gate of the first PMOS tube MQ2 is connected to the drain of the first NMOS tube M1, and the connection point is a node A. The drain of the first PMOS tube MQ2 is connected to the drain of the fourth NMOS tube MQ1, the source of the fourth NMOS tube MQ1 is connected to the drain of the third NMOS tube M3, and the gate of the fourth NMOS tube MQ1 is connected to the second control signal ENC.

[0051] In some embodiments, the clamping unit includes a first PMOS tube, the source of the first PMOS tube is connected to the drain of the second NMOS tube, the drain of the first PMOS tube is connected to the drain of the third NMOS tube, and the gate of the first PMOS tube is connected to the drain of the first NMOS tube.

[0052] Reference Figure 4 and Figure 5 The first-stage amplifier circuit also includes a reset unit, which includes a second PMOS tube MS1 and a third PMOS tube MS2. The source of the second PMOS tube MS1 is connected to the drain of the first NMOS tube M1, the drain of the second PMOS tube MS1 is connected to the gate of the first NMOS tube M1, the source of the third PMOS tube MS2 is connected to the drain of the second NMOS tube M2, the drain of the third PMOS tube MS2 is connected to the gate of the second NMOS tube M2, and the gate of the second PMOS tube MS1 and the gate of the third PMOS tube MS2 are both connected to the third control signal RSTN_CM.

[0053] Reference Figure 4 and Figure 5 The second-stage amplifier circuit 10212 includes a sixth PMOS tube M6, a fifth NMOS tube MS3, a sixth NMOS tube M7 and a third capacitor C3. The source of the sixth PMOS tube M6 is connected to the power supply voltage VDD, the gate of the sixth PMOS tube M6 is connected to the first-stage amplifier circuit 10211, the drain of the sixth PMOS tube M6 is connected to the drain of the fifth NMOS tube MS3 and the drain of the sixth NMOS tube M7, the source of the fifth NMOS tube MS3 and the gate of the sixth NMOS tube M7 are both connected to one end of the third capacitor C3, the other end of the third capacitor C3 is grounded, the gate of the fifth NMOS tube MS3 is connected to the fourth control signal RST_CM, and the source of the sixth NMOS tube M7 is grounded GND.

[0054] Reference Figure 4 and Figure 5 The third NMOS tube M3 is a current source tube, which provides a bias current for the first-stage amplification unit. The first capacitor C1 and the second capacitor C2 are both DC-isolating capacitors. The third control signal RSTN_CM and the fourth control signal RST_CM are mutually inverted signals. CM_OUT is the output signal of the comparator.

[0055] Figure 6 FIG. 1 is a timing diagram of an image sensor in the prior art. The image sensor in the present invention adopts Figure 6 Same timing diagram. Figure 2 , Figure 5 and Figure 6 , RX represents the fifth control signal applied to the gate of the seventh NMOS tube 10111, TX represents the sixth control signal applied to the gate of the ninth NMOS tube 10113, SEL represents the seventh control signal applied to the gate of the tenth NMOS tube 10114, RST_CM represents the fourth control signal applied to the gate of the fifth NMOS tube MS3, RAMP represents the ramp signal, PIX_OUT represents the pixel signal, CM_OUT represents the output signal of the comparator, CNT represents the count value of the counter, VR represents the first ramp stage, VS represents the second ramp stage, t1 represents the first counting time of the counter, and t2 represents the second counting time of the counter.

[0056] Reference Figure 4 , Figure 5 and Figure 6 When the ramp signal RAMP is higher than the pixel signal PIX_OUT, the driving voltage CM1_OUT output by the first-stage amplification unit is high, when the third control signal RSTN_CM is low, the fourth control signal RST_CM is high, the second PMOS tube MS1, the third PMOS tube MS2 and the fifth NMOS tube MS3 are turned on, and the comparator is reset.

[0057] Reference Figure 2 , Figure 4 and Figure 6, both the first ramp stage VR and the second ramp stage VS change from a high potential to a low potential, that is, the ramp signal RAMP is first higher than the pixel signal PIX_OUT, and then the ramp signal RAMP is lower than the pixel signal PIX_OUT. Before the first ramp stage VR and the second ramp stage VS start, the potential of the ramp signal RAMP will be raised first so as to cross with the pixel signal PIX_OUT later as the basis for the judgment of the comparator. However, when the ramp signal RAMP is higher than the pixel signal PIX_OUT, since the gain of the first-stage amplification unit is relatively large, the jump amplitude of the driving voltage CM1_OUT output by the first-stage amplification unit is relatively large, and it will be pulled up to close to the power supply voltage VDD, which will cause the sixth PMOS tube M6 to be turned off, so that no current flows through the second-stage amplification circuit 10212, thereby causing the IR of the power supply voltage VDD to be drop decreases until the ramp signal RAMP is lower than the pixel signal PIX_OUT, that is, after the comparator completes the flipping in the first ramp stage VR, the sixth PMOS tube M6 will be turned on, and the judgment process of the second-stage amplifier circuit 10212 will be prolonged, thereby increasing the flipping delay of the comparator. Similarly, the second ramp stage VS has the same problem as the first ramp stage VR.

[0058] In some embodiments, in the image sensor, if the pixel array unit includes n columns of pixel units, n readout units are required, and the n readout units include n comparators, where n is a natural number greater than 1. Figure 4 In the comparator shown, in the first ramp stage, the potentials of the pixel signals output by the pixel units in each column are relatively close, so the flip delays of the comparators in each column in the first ramp stage are almost the same; in the second ramp stage, the pixel signals output by the pixel units in each column may be greatly different, for example Figure 6As shown in the large signal and small signal, when the pixel signal is a large signal, that is, the pixel signal changes greatly, and when the pixel signal is a small signal, that is, the pixel signal changes less, the comparator receiving the pixel signal of the small signal will flip first relative to the comparator receiving the pixel signal of the large signal, and the second-stage amplifier circuit of the comparator flipped first will be restored to conduction first, thereby increasing the IR drop of the signal line of the power supply voltage VDD. For example, the i-th comparator receives a pixel signal of a small signal, and the n-th comparator receives a pixel signal of a large signal. The i-th comparator will increase the current on the signal line of the power supply voltage VDD, thereby increasing the IR drop of the entire signal line of the power supply voltage VDD. The power supply voltage of the n-th comparator at this time will be smaller than the normal power supply voltage, so that the gate-source voltage of the sixth PMOS tube in the n-th comparator becomes smaller, and the flipping of the second-stage amplifier circuit of the n-th comparator will be delayed, thereby making the second counting time of the counter connected to the n-th comparator larger, and finally making the digital signal converted by the n-th column pixel signal larger, i is a natural number greater than 0 and less than n.

[0059] Figure 7 To adopt Figure 4 The dark scene image is captured by the image sensor of the comparator shown in FIG. Figure 4 When the comparator shown in FIG. 1 is shooting a dark scene, if there is a circular pattern darker than the dark scene in the uniform dark scene, the pixel output in the same row as the circular pattern will be larger than the pixel output value of the surrounding image. At this time, the gain will be very large, so that the image will show abnormal banded noise in the same row as the graphic pattern, such as Figure 7 shown.

[0060] Reference Figure 5 When the second control signal ENC is high, the fourth NMOS tube MQ1 is turned on and the clamping unit is valid; when the second control signal ENC is low, the fourth NMOS tube MQ1 is turned off and the clamping unit is invalid.

[0061] Reference Figure 5, the potential of the power supply voltage VDD is Vdd, the gate-source voltage of the fourth PMOS tube M4 is VGS4, then the potential of the node A is Vdd-VGS4, after the potential of the ramp signal is raised before the start of the first ramp stage, and after the potential of the ramp signal is raised before the start of the second ramp stage, the driving voltage CM1_OUT output by the first-stage amplifier circuit is pulled up to a high potential, when the potential of the driving voltage CM1_OUT reaches Vdd-VGS4+Vth1, the first PMOS tube MQ2 will be turned on, so that the branch where the first PMOS tube MQ2 and the fourth NMOS tube MQ1 are located generates current, thereby limiting the rise of the driving voltage CM1_OUT. Wherein, VGS4 is the gate-source voltage of the fourth PMOS tube M4, Vth1 is the threshold voltage of the first PMOS tube MQ2, the threshold voltage of the fourth PMOS tube M4 is Vth4, the drain-source voltage of the fourth PMOS tube M4 is VDS4, Vth4 is approximately equal to Vth1, and Vdd-VGS4+Vth1 can be converted to Vdd-VDS4. By controlling the bias current Ib provided by the third NMOS tube M3 and the size of the fourth PMOS tube M4, VDS4 can be made greater than or equal to the threshold voltage Vth6 of the sixth PMOS tube M6. Therefore, when the potential of the driving voltage CM1_OUT reaches the highest, the gate-source voltage VGS6 of the sixth PMOS tube M6 is greater than or equal to the threshold voltage Vth6 of the sixth PMOS tube M6, thereby ensuring that the sixth PMOS tube M6 is always in a conducting state, thereby avoiding IR drop of the power supply voltage VDD signal line.

[0062] Figure 8 To adopt Figure 5 The dark scene image is captured by the image sensor of the comparator shown in FIG. Figure 5 The comparator shown in FIG. 1 eliminates abnormal band noise when a dark scene is captured and a circular pattern darker than the dark scene exists in the uniform dark scene, such as Figure 8 shown.

[0063] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A first-stage amplifier circuit, applied to a comparator, characterized in that: include: The first-stage amplification unit is used to compare the pixel signal and the ramp signal and output a driving voltage; the first-stage amplification unit includes a current mirror circuit, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first capacitor and a second capacitor, the drain of the first NMOS tube is connected to the first output end of the current mirror circuit, the drain of the second NMOS tube is connected to the second output end of the current mirror circuit, as the output end of the first-stage amplification unit, the source of the first NMOS tube and the source of the second NMOS tube are both connected to the drain of the third NMOS tube, the source of the third NMOS tube is grounded, the gate of the first NMOS tube is connected to one end of the first capacitor, the other end of the first capacitor is connected to the ramp signal, the gate of the second NMOS tube is connected to one end of the second capacitor, the other end of the second capacitor is connected to the pixel signal, and the gate of the third NMOS tube is connected to the first control signal; as well as A clamping unit is connected to the first-stage amplifying unit and is used to limit the rise of the driving voltage when the driving voltage reaches the target voltage; the clamping unit includes a first PMOS tube and a fourth NMOS tube, the source of the first PMOS tube is connected to the drain of the second NMOS tube, the gate of the first PMOS tube is connected to the drain of the first NMOS tube, the drain of the first PMOS tube is connected to the drain of the fourth NMOS tube, the source of the fourth NMOS tube is connected to the drain of the third NMOS tube, and the gate of the fourth NMOS tube is connected to the second control signal.

2. The first-stage amplifier circuit according to claim 1, characterized in that: It also includes a reset unit, which includes a second PMOS tube and a third PMOS tube, the source of the second PMOS tube is connected to the drain of the first NMOS tube, the drain of the second PMOS tube is connected to the gate of the first NMOS tube, the source of the third PMOS tube is connected to the drain of the second NMOS tube, the drain of the third PMOS tube is connected to the gate of the second NMOS tube, and the gate of the second PMOS tube and the gate of the third PMOS tube are both connected to a third control signal.

3. The first-stage amplifier circuit according to claim 1, characterized in that: The current mirror circuit includes a fourth PMOS tube and a fifth PMOS tube, the source of the fourth PMOS tube and the source of the fifth PMOS tube are both connected to the power supply voltage, the drain of the fourth PMOS tube is connected to the gate of the fourth PMOS tube, the gate of the fifth PMOS tube, and the drain of the first NMOS tube, and the drain of the fifth PMOS tube is connected to the drain of the second NMOS tube.

4. A comparator, characterized in that: include: The first-stage amplifier circuit according to any one of claims 1 to 3; as well as The second-stage amplifier circuit includes a sixth PMOS tube, a fifth NMOS tube, a sixth NMOS tube and a third capacitor, wherein the source of the sixth PMOS tube is connected to a power supply voltage, the gate of the sixth PMOS tube is connected to the first-stage amplifier circuit, the drain of the sixth PMOS tube is connected to the drain of the fifth NMOS tube and the drain of the sixth NMOS tube, the source of the fifth NMOS tube and the gate of the sixth NMOS tube are both connected to one end of the third capacitor, the other end of the third capacitor is grounded, the gate of the fifth NMOS tube is connected to a fourth control signal, and the source of the sixth NMOS tube is grounded.

5. A readout circuit, characterized in that: The device comprises at least one readout unit, wherein the readout unit comprises the comparator and the counter as claimed in claim 4, wherein the counter is connected to the output end of the comparator and is used to count the output signal of the comparator to output a digital signal.

6. An image sensor, characterized in that: include: A pixel array unit, used for outputting pixel signals after light sensing; A decoding driving unit, connected to the pixel array unit, and used to drive the pixel array unit; A ramp generating unit, used for generating a ramp signal; The readout circuit as claimed in claim 5, connected to the ramp generating unit and the pixel array unit; An output signal processing unit, connected to the readout circuit, to convert the digital signal into an image and output it; A timing control unit is connected to the decoding driving unit, the ramp generating unit, the readout circuit and the output signal processing unit, and is used to send a clock signal to the decoding driving unit, the ramp generating unit, the readout circuit and the output signal processing unit.

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