Printed Circuit Board and Method for Manufacturing Printed Circuit Board

Abstract

The present disclosure provides a printed circuit board and a method of manufacturing a printed circuit board. The printed circuit board includes: a first insulating layer; a first metal layer disposed on one surface of the first insulating layer; a second metal layer disposed on the other surface of the first insulating layer opposite to the one surface; a via hole penetrating the first insulating layer to connect the first metal layer and the second metal layer to each other; and a heterogeneous metal region disposed in at least one of a region adjacent to the via hole and the first insulating layer and a region adjacent to the via hole and the first metal layer, and the heterogeneous metal region includes a material different from that of the via hole, wherein the heterogeneous metal region contains at least one of nickel (Ni), silicon (Si), and titanium (Ti).

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2021-0077836 filed in the Korean Intellectual Property Office on June 16, 2021, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board and a method for manufacturing the printed circuit board. Background Art

[0003] In order to follow the recent trend toward weight reduction and size reduction of mobile devices, there has also been a growing demand to make printed circuit boards to be mounted on mobile devices lighter, thinner, shorter, and smaller.

[0004] Therefore, in order to form micro vias that connect layers to each other in a printed circuit board, a technology for effectively processing the micro via holes is required. In addition, a wiring material filling the micro via holes is required to have excellent electrical and mechanical properties. Summary of the invention

[0005] An aspect of the present disclosure may provide a printed circuit board including a microcircuit and / or a microvia.

[0006] Another aspect of the present disclosure may provide a printed circuit board in which a via hole of a microcircuit having excellent electrical and mechanical properties is formed.

[0007] According to one aspect of the present disclosure, a printed circuit board may include: a first insulating layer; a first metal layer, disposed on one surface of the first insulating layer; a second metal layer, disposed on another surface of the first insulating layer opposite to the one surface; a via, penetrating the first insulating layer to connect the first metal layer and the second metal layer to each other; and a heterogeneous metal region, disposed in at least one of a region where the via is adjacent to the first insulating layer and a region where the via is adjacent to the first metal layer, and the heterogeneous metal region includes a material different from that of the via, wherein the heterogeneous metal region contains at least one of nickel (Ni), silicon (Si) and titanium (Ti).

[0008] According to another aspect of the present disclosure, a method for manufacturing a printed circuit board includes: preparing a first insulating layer, the first insulating layer is disposed on a second insulating layer, and a first metal layer is disposed on one surface of the first insulating layer; forming a via hole penetrating the first insulating layer to expose at least a portion of the first metal layer; forming a via hole by filling the via hole; and forming a second metal layer connected to the via hole and disposed on another surface of the first insulating layer, the other surface being opposite to the one surface, wherein the via hole forming step includes performing a sandblasting process using an abrasive containing at least one of nickel (Ni), silicon (Si) and titanium (Ti). BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a diagram schematically showing an example of an electronic device system;

[0011] Figure 2 is a diagram schematically illustrating an exemplary embodiment of an electronic device;

[0012] Figure 3 is a diagram schematically illustrating an exemplary embodiment of a printed circuit board according to the present disclosure; and

[0013] Figures 4 to 7 is a diagram schematically illustrating a process for manufacturing a printed circuit board according to the present disclosure. DETAILED DESCRIPTION

[0014] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0015] Electronic Devices

[0016] Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0017] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010 therein. The mainboard 1010 may be physically and / or electrically connected to a chip-related component 1020, a network-related component 1030, and other components 1040. These components may be connected to other electronic components to be described below via various signal lines 1090.

[0018] The chip-related components 1020 may include: a memory chip, such as a volatile memory (e.g., a dynamic random access memory (DRAM)), a non-volatile memory (e.g., a read-only memory (ROM)), or a flash memory; an application processor chip, such as a central processing unit (e.g., a central processing unit (CPU)), a graphics processor (e.g., a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller; and a logic chip, such as an analog-to-digital converter or an application-specific integrated circuit (ASIC). The chip-related components 1020 are not limited thereto, but may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may have a package form including the above-mentioned chips or electronic components.

[0019] The network-related components 1030 may include components that are compatible with or communicate according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), EV-DO (evolution-data only, an evolution of cdma2000 1x), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for Global Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, 3G protocols, 4G protocols, 5G protocols, and any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, but may also include components compatible with or communicating according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020.

[0020] Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components 1040 are not limited thereto, but also include passive components in the form of chip components for various other purposes, etc. In addition, other components 1040 may be combined with each other together with chip-related components 1020 and / or network-related components 1030.

[0021] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the mainboard 1010. Examples of other electronic components may include a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. The other electronic components are not limited thereto, but may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), etc. The electronic device 1000 may also include other electronic components for various purposes, etc., depending on the type of the electronic device 1000.

[0022] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a display, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto, but may be any other electronic device that processes data.

[0023] Figure 2 is a perspective view schematically illustrating an exemplary embodiment of an electronic device.

[0024] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that may or may not be physically and / or electrically connected to the mainboard 1110 may also be housed in the smart phone 1100. A portion of the electronic component 1120 may be the above-mentioned chip-related component, such as an antenna module 1121, but is not limited thereto. The antenna module 1121 may be in a form in which an electronic component is surface-mounted on a printed circuit board, but is not limited thereto. In addition, the electronic device is not necessarily limited to the smart phone 1100, but may be any other electronic device as described above.

[0025] Printed Circuit Board

[0026] Figure 3 is a diagram schematically illustrating an exemplary embodiment of a printed circuit board according to the present disclosure.

[0027] Reference Figure 3According to the present disclosure, a printed circuit board may include: a first insulating layer 100; a first metal layer 300, which is disposed on one surface of the first insulating layer 100, specifically, the first metal layer 300 may be embedded in one surface of the first insulating layer 100; a second metal layer 400, which is disposed on another surface of the first insulating layer 100 opposite to the one surface; and a via 500, which penetrates the first insulating layer 100 to connect the first metal layer 300 and the second metal layer 400 to each other.

[0028] In this case, the printed circuit board according to the present disclosure may further include a heterogeneous metal area 510 disposed in at least one of an area where the via 500 is adjacent to the first insulating layer 100 and an area where the via 500 is adjacent to the first metal layer 300, and the heterogeneous metal area 510 includes a material different from that of the via 500. For example, the heterogeneous metal area 510 may connect the first metal layer 300 and the via 500 to each other.

[0029] In this case, the heterogeneous metal region 510 may include at least one of nickel (Ni), silicon (Si), and titanium (Ti). By providing the heterogeneous metal region 510 including the above-mentioned material (particularly a conductive metal having high conductivity) between the via 500 and the first metal layer 300, the conductivity can be improved, and the mechanical strength can also be improved.

[0030] The heterogeneous metal region 510 may include at least one particle. More specifically, the heterogeneous metal region 510 may include a conductive material in the form of particles, the conductive material including at least one of nickel (Ni), silicon (Si), and titanium (Ti), but is not limited thereto.

[0031] The heterogeneous metal region 510 may be a layer formed in a plating process for filling the via hole 500H after forming the via hole 500H (described below). More specifically, as will be described below, the via hole 500H may be formed by a sandblasting method (or referred to as a sandblasting process) using the abrasive 10, and after the via hole 500H is formed, the abrasive 10 remaining in the via hole 500H may be combined with the plating layer for forming the via hole 500, thereby forming the heterogeneous metal region 510. In this case, the abrasive 10 remaining in the via hole 500H may include at least one of nickel (Ni), silicon (Si), and titanium (Ti), and the heterogeneous metal region 510 formed by combining the abrasive 10 remaining in the via hole 500H with the plating layer for forming the via hole 500 may include a material different from that of the via hole 500. In addition, the plating layer for forming the via hole 500 by filling the via hole 500H may include an electroless plating layer and an electrolytic plating layer. The heterogeneous metal region 510 may be in contact with an electroless plated layer, or may be in contact with both an electroless plated layer and an electrolytic plated layer, but is not limited thereto.

[0032] Since the heterogeneous metal region 510 including the above material (particularly, a conductive metal having high conductivity) may connect the via 500 and the first metal layer 300 to each other, conductivity may be improved, and mechanical strength may also be improved.

[0033] The heterogeneous metal region 510 may be formed only in a region where the via hole 500 is adjacent to each of the first insulating layer 100 and the first metal layer 300. More specifically, as Figure 6 As shown in , the via hole 500H may have a first region 500A adjacent to the first metal layer 300 and a second region 500B adjacent to the first insulating layer 100, in which case the heterogeneous metal region 510 may be disposed in at least a portion of the first region 500A and in at least a portion of the second region 500B. This is because when the via hole 500H is formed, the abrasive 10 used in the sandblasting process may remain only in the region of the via hole 500H adjacent to each of the first insulating layer 100 and the first metal layer 300. Alternatively, the heterogeneous metal region 510 may be disposed only in the first region 500A of the via hole 500 adjacent to the first metal layer 300, but is not limited thereto.

[0034] In this case, the abrasive 10 used in the sandblasting process may include at least one of nickel (Ni), silicon (Si) and titanium (Ti), and the abrasive 10 may have a particle size of 0.001 μm to 50 μm, and may be distributed in an irregular particle size. The particle size of the abrasive 10 may be measured by known techniques. For example, the particle size may be measured by a scanning electron microscope (SEM).

[0035] Since copper (Cu) introduced in the plating process of forming the via hole 500 and at least one of nickel (Ni), silicon (Si) and titanium (Ti) remaining after the sandblasting process of forming the via hole 500H can form a heterogeneous metal area 510, conductivity can be improved and mechanical strength can also be improved, but the effect is not limited to this.

[0036] For example, the heterogeneous metal region 510 may contain 3wt% to 7wt% of nickel (Ni), silicon (Si), and titanium (Ti) based on the total weight of copper (Cu), nickel (Ni), silicon (Si), and titanium (Ti) in the heterogeneous metal region 510. In this case, when the content of nickel (Ni), silicon (Si), and titanium (Ti) contained in the heterogeneous metal region 510 is less than 3wt%, the mechanical strength of the heterogeneous metal region according to the present disclosure cannot be improved as expected compared to the via plating layer containing only Cu. On the other hand, when the content of nickel (Ni), silicon (Si), and titanium (Ti) contained in the heterogeneous metal region 510 is greater than 7wt%, the thermal conductivity and electrical conductivity of the heterogeneous metal region 510 may be much lower than the thermal conductivity and electrical conductivity of the via plating layer containing only Cu. Considering the mechanical strength and conductivity of the circuit pattern and the via 500, etc., the content of nickel (Ni), silicon (Si), and titanium (Ti) contained in the heterogeneous metal region 510 is preferably maintained in the range of 3wt% to 7wt%, but is not limited thereto. The content of at least one of nickel (Ni), silicon (Si), and titanium (Ti) in the heterogeneous metal region 510 is 3 wt % to 7 wt % based on the total weight of the heterogeneous metal region 510. For example, the content of at least one of nickel (Ni), silicon (Si), and titanium (Ti) in the heterogeneous metal region 510 is 3 wt % to 7 wt % based on the total weight of at least one of nickel (Ni), silicon (Si), and titanium (Ti) in the heterogeneous metal region 510 and copper.

[0037] A method of measuring the weights of nickel (Ni), silicon (Si), and titanium (Ti) in the heterogeneous metal region 510 or the content ratio therebetween will be described below.

[0038] A portion of the conductive material included in the heterogeneous metal region 510 may be extracted from a region where the via 500 is adjacent to each of the first metal layer 300 and the first insulating layer 100. In this case, if necessary, the board may be cut at any point of the board to expose a portion of the via 500 or a portion of the heterogeneous metal region 510, but is not limited thereto. In addition, the conductive material may be extracted multiple times from the heterogeneous metal region 510. In addition, the conductive material may be extracted only from the first region 500A where the via 500 is adjacent to the first metal layer 300, or the conductive material may be extracted only from the second region 500B where the via 500 is adjacent to the first insulating layer 100, but is not limited thereto.

[0039] Here, the area of ​​the via 500 adjacent to each of the first metal layer 300 and the first insulating layer 100 may include the following area: from a portion of the via 500 that is completely in contact with each of the first metal layer 300 and the first insulating layer 100 to a portion of the via 500 that is spaced apart from each of the first metal layer 300 and the first insulating layer 100 by a predetermined distance (excluding a portion of the via 500 that is spaced apart from each of the first metal layer 300 and the first insulating layer 100 by more than a predetermined distance). The predetermined distance is not limited, but may refer to the length or shortest distance of a region of the via 500 that includes at least one of nickel (Ni), silicon (Si), and titanium (Ti).

[0040] After that, the relative mass fractions of copper (Cu), nickel (Ni), silicon (Si) and titanium (Ti) in the extracted conductive sample can be observed by energy dispersive X-ray spectroscopy or inductively coupled plasma mass spectrometry. Based on this, the content ratio between nickel (Ni), silicon (Si) and titanium (Ti) can be obtained.

[0041] In addition, when the conductive material is extracted multiple times, multiple measured values ​​of the total weight of the conductive material can be obtained. In addition, multiple values ​​of the sum of the respective weights of nickel (Ni), silicon (Si), and titanium (Ti) can be obtained. In this case, each of the nickel (Ni) content, silicon (Si) content, and titanium (Ti) content of the heterogeneous metal region 510 can be an average value of the measured values ​​of the corresponding samples of the conductive material extracted multiple times. More specifically, in the case of extracting the conductive material multiple times, the weight ratio or content ratio between nickel (Ni), silicon (Si), and titanium (Ti) can be measured for each of the multiple samples of the extracted conductive material, and the arithmetic mean of the measured values ​​can be the weight ratio or content ratio between the nickel (Ni), silicon (Si), and titanium (Ti) contained in the heterogeneous metal region 510.

[0042] In addition, the printed circuit board according to the present disclosure may further include a second insulating layer 200 disposed on one surface of the first insulating layer 100 and at least partially contacting the first metal layer 300. That is, the printed circuit board according to the present disclosure may include the first insulating layer 100 stacked on the upper surface of the second insulating layer 200 and the first metal layer 300 contacting the second insulating layer 200 and embedded in the first insulating layer 100. In this case, the first metal layer 300 may be embedded in one surface of the first insulating layer 100 and protrude from one surface of the second insulating layer 200. The second metal layer 400 may be formed to protrude from the other surface of the first insulating layer 100 opposite to the one surface of the first insulating layer 100.

[0043] The first insulating layer 100 and the second insulating layer 200 may include the same material or may include different materials. In addition, the first insulating layer 100 and the second insulating layer 200 may include at least one of the following materials: a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide resin), and a resin in which a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler in a core material such as glass fiber (glass cloth or glass fabric) (e.g., prepreg, Ajinomoto built-up film (ABF), FR-4, or bismaleimide triazine (BT)).

[0044] The second insulating layer 200 may be an insulating layer on which a carrier metal foil (such as a copper foil) is attached. In this case, the carrier metal foil may include a copper clad laminate (CCL). Based on the purpose of use, the type of copper clad laminate may include a glass / epoxy copper clad laminate, a heat-resistant resin copper clad laminate, a paper / phenolic resin copper clad laminate, a high-frequency copper clad laminate, a flexible copper clad laminate, a composite copper clad laminate, etc. In this case, taking the metal foil as a copper foil as an example, the copper foil may include copper (Cu), and the portion of the copper foil other than the portion on which the first metal layer 300 is formed may be removed in the process of forming the first metal layer 300.

[0045] The first insulating layer 100 may be an insulating layer on which a carrier metal foil (such as a copper foil) is attached. Taking the metal foil as a copper foil as an example, similar to the carrier copper foil on the second insulating layer 200, the portion of the carrier copper foil on the first insulating layer 100 other than the portion where the second metal layer 400 is formed may be removed in the process of forming the second metal layer 400.

[0046] The via 500 and the first metal layer 300 and the second metal layer 400 may be formed by using a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), palladium (Pd), or an alloy thereof, or the via 500 and the first metal layer 300 and the second metal layer 400 may be formed by using a non-insulating material such as carbon fiber and a metal material. The electroless plating layer and the electrolytic plating layer of the via 500 formed by filling the via hole 500H may also include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), palladium (Pd), or an alloy thereof. In this case, the heterogeneous metal region 510 connecting the via 500 and the first metal layer 300 to each other may include at least one of nickel (Ni), silicon (Si), and titanium (Ti).

[0047] The heterogeneous metal region 510 may include at least one particle. More specifically, the heterogeneous metal region 510 may include a conductive material in the form of particles, the conductive material including at least one of nickel (Ni), silicon (Si), and titanium (Ti), but is not limited thereto.

[0048] The via 500 and the first and second metal layers 300 and 400 may be formed using the same material, but may also include different materials. After forming the first and second metal layers 300 and 400, the carrier copper foil formed on the first and second insulating layers 100 and 200 may be removed by etching or the like.

[0049] Each of the first metal layer 300 and the second metal layer 400 may be formed by providing a plating resist on the upper surface of the copper foil, performing an electrolytic plating process, etc., and then removing the plating resist. The plating resist may be removed by a commonly used plating resist removal method.

[0050] Regarding other components, what has been described above applies substantially the same, and therefore, their description will not be repeated.

[0051] Method for manufacturing printed circuit board

[0052] Figures 4 to 7 is a diagram schematically illustrating a process for manufacturing a printed circuit board according to the present disclosure.

[0053] Reference Figure 4 , a second insulating layer 200 having a metal foil (such as a copper foil) attached thereto may be prepared. In this case, the second insulating layer may be a carrier film and may include a copper clad laminate (CCL). Based on the purpose of use, the types of copper clad laminates may include: glass / epoxy copper clad laminates, heat-resistant resin copper clad laminates, paper / phenolic resin copper clad laminates, high-frequency copper clad laminates, flexible copper clad laminates, composite copper clad laminates, etc. In this case, taking the metal foil as copper foil as an example, the copper foil may contain copper (Cu).

[0054] Afterwards, refer to Figure 5 , a first metal layer 300 may be formed, and a first insulating layer 100 may be provided in which the first metal layer 300 is embedded. In this case, the first metal layer 300 may be formed by a known plating process (e.g., an additive process (AP), a semi-additive process (SAP), or a modified semi-additive process (MSAP)). As another example, the first metal layer 300 may be formed by a subtractive process (such as a sealing process).

[0055] In this case, the copper foil attached to the second insulating layer 200 except for the portion contacting the first metal layer 300 may be removed by an etching process, etc. That is, the copper foil attached to the second insulating layer 200 may be regarded as a part of the first metal layer 300 .

[0056] The first insulating layer 100 stacked on one surface of the second insulating layer 200 may further include a metal foil such as a copper foil. For example, the copper foil may include copper (Cu). The first insulating layer 100 may be configured to embed the first metal layer 300 therein.

[0057] Thereafter, a via hole 500H penetrating at least a portion of the first insulating layer 100 and exposing at least a portion of the first metal layer 300 may be formed, in which case a sandblasting method may be used. Specifically, the abrasive used in the sandblasting method may include an abrasive 10, and the abrasive 10 may include at least one of nickel (Ni), silicon (Si), and titanium (Ti), but is not limited thereto.

[0058] Reference Figure 6 , even after the via hole 500H is formed, the abrasive 10 including at least one of nickel (Ni), silicon (Si), and titanium (Ti) used in the sandblasting process may remain. Specifically, the abrasive 10 including at least one of nickel (Ni), silicon (Si), and titanium (Ti) may remain in the first region 500A of the via hole 500H adjacent to the first metal layer 300 and the second region 500B of the via hole 500H adjacent to the first insulating layer 100.

[0059] The abrasive 10 used in the sandblasting process may remain in at least a portion of the first region 500A and at least a portion of the second region 500B. In addition, the abrasive 10 may include at least one of nickel (Ni), silicon (Si), and titanium (Ti), and the abrasive 10 may have a particle size of 0.001 μm to 50 μm, and may be distributed in an irregular particle size, but is not limited thereto.

[0060] Reference Figure 7 , a via hole 500 filling the via hole 500H formed by using a sandblasting method may be formed. In this case, the via hole 500 may include an electroless plating layer and an electrolytic plating layer. More specifically, the electroless plating layer may be formed on the upper surface of the copper foil attached to the first insulating layer 100 and extend along the via hole 500H, and the electrolytic plating process may be performed using the electroless plating layer as a seed layer.

[0061] In the process of filling the via hole 500H, a region (i.e., a heterogeneous metal region 510) in which the remaining abrasive 10 and the plating layer are alloyed with each other may be formed. In this case, the abrasive 10 remaining in the via hole 500H after the sandblasting process may include at least one of nickel (Ni), silicon (Si), and titanium (Ti), and the remaining abrasive 10 may be combined with the plating layer used to form the via hole 500, thereby forming the heterogeneous metal region 510. The presence of the alloy may be observed by X-ray diffraction (XRD), for example, by a 1°-2° shift of at least one XRD peak corresponding to copper (Cu).

[0062] The heterogeneous metal region 510 may include at least one particle. More specifically, the heterogeneous metal region 510 may include a conductive material in the form of particles, the conductive material including at least one of nickel (Ni), silicon (Si), and titanium (Ti), but is not limited thereto.

[0063] In this case, although not shown, the heterogeneous metal area 510 formed by combining with the abrasive 10 may contact only at least a portion of the electroless plating layer formed to fill the via hole 500H, or the heterogeneous metal area 510 may contact at least a portion of each of the electroless plating layer and the electrolytic plating layer, but is not limited thereto.

[0064] In addition, the via hole 500H may include a first region 500A adjacent to the first metal layer 300 and a second region 500B adjacent to the first insulating layer 100. The first region 500A and the second region 500B may correspond to regions only within the electroless plating layer of the via hole 500, or may correspond to regions of the via hole 500 including both the electroless plating layer and the electrolytic plating layer, but are not limited thereto.

[0065] Here, the area of ​​the via 500 adjacent to each of the first metal layer 300 and the first insulating layer 100 may include the following area: from a portion of the via 500 that is completely in contact with each of the first metal layer 300 and the first insulating layer 100 to a portion of the via 500 that is spaced apart from each of the first metal layer 300 and the first insulating layer 100 by a predetermined distance (excluding a portion of the via 500 that is spaced apart from each of the first metal layer 300 and the first insulating layer 100 by more than a predetermined distance). The predetermined distance is not limited, but may refer to the length or shortest distance of a region of the via 500 that includes at least one of nickel (Ni), silicon (Si), and titanium (Ti).

[0066] In this case, for example, based on the total weight of copper (Cu), nickel (Ni), silicon (Si), and titanium (Ti) in the heterogeneous metal region 510, the heterogeneous metal region 510 may include 3wt% to 7wt% of nickel (Ni), silicon (Si), and titanium (Ti). When the content of nickel (Ni), silicon (Si), and titanium (Ti) contained in the heterogeneous metal region 510 is less than 3wt%, the mechanical strength may be excessively reduced. On the other hand, when the content of nickel (Ni), silicon (Si), and titanium (Ti) contained in the heterogeneous metal region 510 is greater than 7wt%, thermal conductivity and electrical conductivity may be greatly reduced. Considering the mechanical strength and conductivity of the via 500, etc., the content of nickel (Ni), silicon (Si), and titanium (Ti) contained in the heterogeneous metal region 510 is preferably maintained in the range of 3wt% to 7wt%, but is not limited thereto.

[0067] Since the heterogeneous metal region 510 (including at least one of nickel (Ni), silicon (Si) and titanium (Ti) remaining after the sandblasting process) is formed, the first metal layer 300 and the via 500 are connected to each other through the heterogeneous metal region 510, so the via 500 can be formed to have improved conductivity and excellent mechanical strength.

[0068] In addition, the second metal layer 400 disposed on the other surface of the first insulating layer 100 opposite to the one surface may be formed. In this case, the via hole 500 and the first metal layer 300 may be formed by a known plating process (e.g., an additive process (AP), a semi-additive process (SAP), or a modified semi-additive process (MSAP)). As another example, the via hole 500 and the first metal layer 300 may be formed by a subtractive process (such as a sealing process).

[0069] In this case, a portion of the copper foil attached to the first insulating layer 100 except for a portion in contact with the second metal layer 400 may be removed by an etching process or the like.

[0070] That is, the via 500 may include an electroless plating layer and an electrolytic plating layer, the second metal layer 400 may include an electroless plating layer and an electrolytic plating layer, and the copper foil attached to the first insulating layer 100 may be regarded as a part of the second metal layer 400 .

[0071] Specifically, each of the first metal layer 300 and the second metal layer 400 may be formed by providing a plating resist on the upper surface of the copper foil, performing an electrolytic plating process, etc., and then removing the plating resist. The plating resist may be removed by a commonly used plating resist removal method.

[0072] Regarding other components, what has been described above applies substantially the same, and therefore, their description will not be repeated.

[0073] As described above, as one effect of the present disclosure, a printed circuit board including a microcircuit and / or a microvia can be provided.

[0074] As another effect of the present disclosure, a printed circuit board in which a via hole of a microcircuit having excellent electrical and mechanical properties is formed can be provided.

[0075] While exemplary embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: a first insulating layer; a first metal layer disposed on one surface of the first insulating layer; a second metal layer disposed on the other surface of the first insulating layer opposite to the one surface; a via hole penetrating the first insulating layer; a through hole disposed in the via hole and penetrating the first insulating layer to connect the first metal layer and the second metal layer to each other; and a heterogeneous metal region disposed in a region of the through hole adjacent to the first metal layer and on an inner wall of the via hole adjacent to the first insulating layer, and the heterogeneous metal region includes a material different from that of the through hole, wherein the heterogeneous metal region contains at least one of nickel and titanium.

2. The printed circuit board according to claim 1, wherein, the heterogeneous metal region includes at least one particle.

3. The printed circuit board according to claim 1, wherein, the heterogeneous metal region further contains copper.

4. The printed circuit board according to claim 1, wherein, the heterogeneous metal region connects the first metal layer and the through hole to each other.

5. The printed circuit board according to claim 1, wherein, based on the total weight of the heterogeneous metal region, the content of the at least one of nickel, silicon and titanium in the heterogeneous metal region is 3 wt% to 7 wt%.

6. The printed circuit board according to claim 1, wherein, the first metal layer is embedded in the one surface of the first insulating layer, and the second metal layer protrudes from the other surface of the first insulating layer.

7. The printed circuit board according to any one of claims 1-6, the printed circuit board further includes a second insulating layer, the second insulating layer is disposed on the one surface of the first insulating layer and at least partially contacts the first metal layer.

8. The printed circuit board according to any one of claims 1-6, wherein, the first metal layer and the second metal layer include the same metal material.

9. The printed circuit board according to any one of claims 1-6, wherein, the through hole includes an electroless plating layer and an electrolytic plating layer, and the heterogeneous metal region contacts at least a part of the electroless plating layer.

10. The printed circuit board according to any one of claims 1-6, wherein, the heterogeneous metal region includes an abrasive.

11. The printed circuit board according to claim 10, wherein, the abrasive contains nickel.

12. The printed circuit board according to claim 10, wherein, the abrasive contains titanium.

13. The printed circuit board according to claim 10, wherein, the abrasive contains nickel, titanium and silicon.

14. The printed circuit board according to any one of claims 1, the printed circuit board further comprises: a second insulating layer, the second insulating layer is disposed on the one surface of the first insulating layer and at least partially contacts the first metal layer; a first metal foil, the first metal foil is located between the first insulating layer and the second metal layer; and A second metal foil, which is disposed between the first metal layer and the second insulating layer and covers the first metal layer in the stacking direction of the first metal layer, the first insulating layer, and the second metal layer.

15. The printed circuit board according to claim 14, wherein, the first metal foil is not in the via hole.

16. The printed circuit board according to claim 3, wherein, the heterogeneous metal region includes an alloy containing at least one of nickel, silicon, and titanium and copper.

17. The printed circuit board according to claim 1, wherein, the heterogeneous metal region further contains silicon.

18. A method of manufacturing a printed circuit board, the method comprising: preparing a first insulating layer disposed on a second insulating layer, and a first metal layer disposed on one surface of the first insulating layer; forming a via hole penetrating the first insulating layer to expose at least a part of the first metal layer; forming a via by filling the via hole; and forming a second metal layer connected to the via and disposed on the other surface of the first insulating layer, the other surface being opposite to the one surface, wherein the step of forming the via hole includes performing a sandblasting process using an abrasive containing at least one of nickel, silicon, and titanium.

19. The method according to claim 18, wherein, in the step of forming the via hole, the abrasive containing at least one of nickel, silicon, and titanium remains in the via hole.

20. The method according to claim 18, wherein, the step of forming the via by filling the via hole includes: forming a heterogeneous metal region disposed in at least one of a first region where the via is adjacent to the first metal layer and a second region where the via is adjacent to the first insulating layer, and the heterogeneous metal region includes a material different from the material of the via.

21. The method according to claim 20, wherein, the first metal layer is embedded in the one surface of the first insulating layer, the heterogeneous metal region contains at least one of nickel, silicon, and titanium.

22. A printed circuit board, comprising: a first insulating layer; a first metal layer disposed on one surface of the first insulating layer; a second metal layer disposed on the other surface of the first insulating layer opposite to the one surface; a via hole penetrating the first insulating layer to connect the first metal layer and the second metal layer to each other; and a heterogeneous metal region disposed in at least one of a region where the via hole is adjacent to the first insulating layer and a region where the via hole is adjacent to the first metal layer, and the heterogeneous metal region includes a material different from the material of the via hole, wherein the heterogeneous metal region contains at least one of nickel, silicon, and titanium, wherein the heterogeneous metal region includes an abrasive containing nickel.

23. A printed circuit board, comprising: a first insulating layer; a first metal layer disposed on one surface of the first insulating layer; a second metal layer disposed on the other surface of the first insulating layer opposite to the one surface; A via hole that penetrates the first insulating layer to connect the first metal layer and the second metal layer to each other; And A heterogeneous metal region provided in at least one of the region adjacent to the via hole and the first insulating layer and the region adjacent to the via hole and the first metal layer, and the heterogeneous metal region includes a material different from the material of the via hole, Wherein, the heterogeneous metal region contains at least one of nickel, silicon and titanium, Wherein, the heterogeneous metal region includes an abrasive, and the abrasive contains titanium.

24. A printed circuit board, Comprising: A first insulating layer; A first metal layer provided on one surface of the first insulating layer; A second metal layer provided on the other surface of the first insulating layer opposite to the one surface; A via hole that penetrates the first insulating layer to connect the first metal layer and the second metal layer to each other; And A heterogeneous metal region provided in at least one of the region adjacent to the via hole and the first insulating layer and the region adjacent to the via hole and the first metal layer, and the heterogeneous metal region includes a material different from the material of the via hole, Wherein, the heterogeneous metal region contains at least one of nickel, silicon and titanium, Wherein, the heterogeneous metal region includes an abrasive, and the abrasive contains nickel, titanium and silicon.

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