A GaN-based CMOS device and a method for fabricating the same

Abstract

The application discloses a GaN-based CMOS device and a preparation method thereof, relates to the field of semiconductors, and aims at the problem that a GaN-based device in the prior art does not have a good P channel. The main method is to utilize vertical electric fields in different directions to induce polarization flipping of epsilon-Ga2O3 in an epsilon-Ga2O3 / GaN heterojunction, so that 2DEG or 2DHG is formed at the heterojunction interface, and thus the NMOS and PMOS structures on the CMOS device are the same and are fully compatible. Meanwhile, a p-channel transistor with electrical parameters such as carrier concentration and mobility which are far greater than those of a traditional technology can be further obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a preparation method thereof, in particular to a GaN-based CMOS device and a preparation method thereof. BACKGROUND

[0002] GaN-based high electron mobility transistors (HEMTs) have a high-concentration and high-mobility two-dimensional electron gas (2DEG) at the heterojunction interface, which makes n-channel GaN HEMTs perform outstandingly in emerging fields such as fast charging, power switching, 5G communication, etc. In contrast, there is currently no suitable p-channel GaN device. On the one hand, existing p-channel devices doped with Mg have relatively low performance, with a channel hole mobility of 5-35 cm 2 Vs (CN114446892A, CN114725022A, CN114725020A). On the other hand, existing two-dimensional hole gas (2DHG) devices are not compatible with the epitaxial structure of n-channel HEMT devices, which is not conducive to integration, and the 2DHG concentration achieved is low (CN112185959A). In order to further develop the applications of GaN-based CMOS, it is particularly important to form a good p-channel. SUMMARY

[0003] The present application aims to provide a GaN-based CMOS device and a preparation method thereof to solve the problems existing in the prior art.

[0004] The GaN-based CMOS device according to the present application comprises NMOS and PMOS connected at the common point of the drain;

[0005] The NMOS and PMOS have the same structure, and a GaN layer and an ε-Ga2O3 layer are sequentially epitaxially grown on the same substrate; a dielectric layer is provided on the ε-Ga2O3 layer, and a gate electrode is provided on the dielectric layer; a source electrode and a drain electrode are provided on both sides of the gate electrode to vertically extend and contact the GaN layer; the GaN layer and the ε-Ga2O3 layer both have spontaneous polarization along the c-axis direction, and the polarization direction of the ε-Ga2O3 layer is regulated by a vertical electric field;

[0006] The GaN layer and the ε-Ga2O3 layer of the NMOS form an ε-Ga2O3 / GaN heterojunction, and a two-dimensional electron gas is formed at the interface;

[0007] The GaN layer and the ε-Ga2O3 layer of the PMOS form an ε-Ga2O3 / GaN heterojunction, and a two-dimensional hole gas is formed at the interface;

[0008] The two-dimensional electron gas and / or the two-dimensional hole gas are induced and converted by an electric field perpendicular to the interface of the ε-Ga2O3 / GaN heterojunction.

[0009] The NMOS and PMOS are provided with a recessed gate structure.

[0010] The thickness of the ε-Ga2O3 layer is 5nm-30nm.

[0011] The two-dimensional electron gas density of the NMOS is 3.5×10 20 cm -2 .

[0012] The two-dimensional hole gas density of the PMOS is 5×10 20 cm -2 .

[0013] The preparation method of the GaN-based CMOS device comprises the following steps:

[0014] Epitaxially growing an ε-Ga2O3 layer on the GaN layer, and forming two parallel ε-Ga2O3 / GaN heterojunctions through deep etching;

[0015] Growing a dielectric layer on each of the ε-Ga2O3 layers;

[0016] Providing a source and a drain on each of the GaN layers, so that the source and the drain penetrate the ε-Ga2O3 layer and are in ohmic contact with the GaN layer directly below;

[0017] Laying a gate on each of the dielectric layers;

[0018] Applying a vertically downward electric field to one of the ε-Ga2O3 / GaN heterojunctions, so that the interface of the ε-Ga2O3 / GaN heterojunction forms a two-dimensional electron gas; and applying a vertically upward electric field to the other ε-Ga2O3 / GaN heterojunction, so that the interface of the ε-Ga2O3 / GaN heterojunction forms a two-dimensional hole gas;

[0019] Removing all the electric fields.

[0020] The vertically downward electric field is applied by a power supply, the positive electrode of which is connected to the gate on the same GaN layer, and the negative electrode of which is connected to the source and the drain on the same GaN layer.

[0021] The vertically upward electric field is applied by another power supply, the negative electrode of which is connected to the gate on the same GaN layer, and the positive electrode of which is connected to the source and the drain on the same GaN layer.

[0022] The strength of the applied electric field is greater than the coercive field of the ε-Ga2O3 layer.

[0023] The dielectric layer is grown on the ε-Ga2O3 layer through ALD.

[0024] The GaN-based CMOS device and its fabrication method described in this invention have the advantage of maintaining the 2DEG and 2DHG states at the heterojunction interface after polarization control, forming high-quality n-channel and p-channel GaN devices. The carrier concentration and mobility in the p-channel are far greater than those of traditional p-channel transistors, significantly improving the PMOS power density of the CMOS device. The NMOS and PMOS epitaxial growth methods used in CMOS devices are identical, resulting in fully compatible epitaxial structures, simplifying the process and improving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a structural diagram of the depletion-type NMOS of the present invention.

[0026] Figure 2 Schematic diagram of the 2DEG distribution and polarization direction of the depletion-mode NMOS of the present invention.

[0027] Figure 3 It is the energy band curve and 2DEG concentration distribution curve of the depletion-type NMOS of the present invention.

[0028] Figure 4 The circuit of the polarization control method of the present invention is Figure 1 .

[0029] Figure 5 It is a structural diagram of the depletion-type PMOS of the present invention.

[0030] Figure 6 It is the energy band curve and 2DHG concentration distribution curve of the depletion-type PMOS of the present invention.

[0031] Figure 7 The circuit of the polarization control method of the present invention is Figure 2 .

[0032] Figure 8 It is a structural diagram of the enhancement mode NMOS of the present invention.

[0033] Figure 9 It is a transfer characteristic simulation curve diagram of the enhancement mode NMOS of the present invention.

[0034] Figure 10 It is a structural diagram of the enhancement mode PMOS of the present invention.

[0035] Figure 11 It is a transfer characteristic simulation curve diagram of the enhancement mode PMOS of the present invention.

[0036] Figure 12 A schematic structural diagram of a GaN-based CMOS device according to the present invention

[0037] Figure 13 Figure 1 is a simulation curve of output characteristics of the NMOS and PMOS of the GaN-based CMOS device according to the present application.

[0038] Reference signs:

[0039] 1-substrate, 2-GaN layer, 3-epsilon-Ga2O3 layer, 4-drain, 5-dielectric layer, 6-gate, 7-source;

[0040] P SP spontaneous polarization, P PZ piezoelectric polarization. DETAILED DESCRIPTION

[0041] Similar to GaN, epsilon-gallium oxide (epsilon-Ga2O3) is also a polar semiconductor with a strong spontaneous polarization (P SP about 0.23 C / m 2 ). A heterojunction can be constructed by using it to obtain a high concentration of 2DEG. At the same time, epsilon-Ga2O3 is also a ferroelectric material, and its polarization direction can change under the action of an external electric field, that is, the surface accumulated polarization charge can change. The heterojunction can regulate the polarization direction of epsilon-Ga2O3 through a vertical electric field, realizing the conversion of 2DEG and 2DHG at the heterojunction interface. Especially for the GaN-based CMOS device of epsilon-Ga2O3 material, the problems of insufficient p-channel electrical performance and poor epitaxial structure compatibility in the traditional technology are completely solved.

[0042] Compared with the existing GaN-based CMOS device, the present application proposes to construct an epsilon-GaO3 / GaN heterojunction to realize a CMOS device, which has the advantages that, on the one hand, a 2DEG and a 2DHG can be formed by using one epitaxial structure, which makes it easier to realize CMOS integration; on the other hand, a heterojunction is constructed by using epsilon-GaO3 with a higher spontaneous polarization strength, so as to obtain a higher concentration of 2DEG and 2DHG, and improve the performance of n-channel and p-channel devices.

[0043] Specifically, the GaN-based CMOS device according to the present application includes NMOS and PMOS connected at the drain.

[0044] As Figure 1As shown, the NMOS and PMOS described in the present application respectively include a medium layer, an ε-Ga2O3 layer, a GaN layer and a substrate which are stacked in sequence. There is also a buffer layer between the substrate and the GaN layer, which is common knowledge and thus not shown in the figure. The ε-Ga2O3 layer and the GaN layer are epitaxially grown to form an ε-Ga2O3 / GaN heterostructure. A medium layer is grown on the upper surface of the ε-Ga2O3 layer and then a gate is laid thereon. The two ends of the ε-Ga2O3 / GaN heterostructure are respectively provided with a drain and a source which penetrate through the ε-Ga2O3 layer. In the embodiment, the substrate can be made of Si, SiC, GaN, Al2O3 or the like. Its function is to have a good lattice match with the epitaxial GaN so as to grow a high-quality GaN layer.

[0045] The drain and the source penetrate through the ε-Ga2O3 layer and are deposited on the upper surface of the GaN layer to form an ohmic contact with the ε-Ga2O3 / GaN heterostructure, so as to reduce the series resistance between the channel and the electrode and increase the current of the device. The medium layer is grown on the ε-Ga2O3 layer by ALD (atomic layer deposition), and the gate is laid on the medium layer. The drain, the source and the gate are all made of metal materials such as aluminum, gold and platinum, and the specific selection is irrelevant to the concept of the present application. There is an insulating layer such as silicon nitride between the drain, the source and the gate to prevent leakage and breakdown between the electrodes. The medium layer can be made of an oxide.

[0046] The thickness of the ε-Ga2O3 layer is 5 nm to 30 nm. The electric field required for the ε-Ga2O3 layer to realize polarization reversal is greater than the coercive field of the gallium oxide material. In order to ensure the normal operation of the device, the operating voltage range of the device needs to be determined. The relationship between voltage and electric field is common knowledge, and those skilled in the art can calculate the electric field generated by the operating voltage to be less than the coercive field according to the actual area of the device.

[0047] GaN is also a polar semiconductor material, which has a spontaneous polarization P SP ~ 0.0034 C / m 2 along the c-axis direction. A high-concentration and high-mobility 2DEG can be easily obtained by polarization induction. The GaN which is lattice-matched with the ε-Ga2O3 is grown to form a high-quality heterojunction interface, which provides a strong guarantee for the formation of 2DEG and 2DHG at the interface.

[0048] The initial polarization of the ε-Ga2O3 and the spontaneous polarization of the GaN are both directed downward along the c-axis, and a 2DEG is generated at the interface, as shown in Figure 2As shown, generally, the laminated structure naturally forms NMOS. There are residual polarization positive charges at the interface of the ε-Ga2O3 / GaN. The polarization positive charges can attract body electrons, making them gather at the interface to form a high-density 2DEG, at which time the device is a depletion-mode device. Since the ε-Ga2O3 layer has a very strong spontaneous polarization and generates a very large piezoelectric polarization under epitaxial stress, the polarization charge density of the interface of the ε-Ga2O3 / GaN heterostructure is much higher than that of the AlGaN / GaN heterostructure, at which time the carrier concentration in the channel of the ε-Ga2O3 / GaN heterojunction is very high. The band diagram of the ε-Ga2O3 / GaN heterostructure and the 2DEG concentration distribution at the interface are as shown in Figure 3 As shown, the interface of the ε-Ga2O3 / GaN heterostructure forms a 3.5x10 20 cm -2 2D electron gas, forming a high-quality n-type conductive channel.

[0049] If it is necessary to regulate the NMOS as a PMOS, it is only necessary to apply a certain strength of electric field between the gate and the source-drain electrode to achieve this, wherein the source-drain electrode is at the same potential. Moreover, unlike the prior art, the electric field can be completely removed after the regulation is completed, and the regulation effect can be permanently maintained without retaining an external voltage. The circuit of the vertical electric field application is as shown in Figure 4 The negative pole of the power supply is connected to the gate, and the positive pole of the power supply is connected to the source-drain electrode. After the electric field is applied, the polarization direction is as shown in Figure 5 The polarization direction at the position below the gate is reversed, and the polarization direction points upward to the surface. There are residual polarization negative charges at the interface of the ε-Ga2O3 / GaN heterojunction, and the polarization negative charges attract holes to gather at the heterojunction interface. After the vertical electric field is removed, there is a high concentration of 2DHG in the channel below the gate at zero bias, at which time the device is in a normally-on state. The band diagram of the ε-Ga2O3 / GaN heterostructure after polarization regulation and the 2DHG concentration distribution at the interface are as shown in Figure 6 As shown, the interface of the ε-Ga2O3 / GaN heterostructure forms a 5x10 20 cm -2 2D hole gas, forming a high-quality p-type conductive channel.

[0050] The laminated structure discussed above, the initial polarization of the ε-Ga2O3 and the spontaneous polarization of the GaN both point downward along the c-axis, and after deep etching, two mutually isolated NMOS are obtained, and the CMOS device described in the present application can be obtained by performing polarization regulation on one of them and connecting the two drain electrodes. However, due to some uncontrollable process factors, the initial polarization of the ε-Ga2O3 and the spontaneous polarization of the GaN may point upward along the c-axis, or two PMOSs may appear in actual circuit operation, and the polarization regulation of one of the PMOSs by a reverse electric field can make it reverse into an NMOS. The circuit is as shown in Figure 7The positive pole of the external power supply of the gate electrode is connected, and the negative pole of the external power supply of the source-drain electrode is connected. After the electric field is added, the polarization direction is as shown in the figure Figure 2 The polarization direction is reversed at the position below the gate electrode, and the polarization direction points downward to the substrate. There are residual polarization positive charges at the interface of the ε-Ga2O3 / GaN heterojunction, and the polarization positive charges attract electrons to gather at the heterojunction interface. After the vertical electric field is removed, there is a high concentration of 2DEG in the channel under the gate at zero bias, and at this time, the device is in the always-on state. The band diagram of the ε-Ga2O3 / GaN heterostructure and the interface 2DEG concentration distribution after polarization regulation are as shown in the figure Figure 3 The ε-Ga2O3 / GaN heterostructure interface forms a two-dimensional electron gas of 3.5*10 20 cm -2 2.

[0051] The device with a planar gate structure is usually a depletion mode device, and a recessed gate structure can be used to realize the always-off design, as shown in the figures Figure 8 and Figure 10 It should be particularly pointed out that the CMOS device and the preparation method thereof described in the present application are not only suitable for depletion mode devices, but also suitable for enhancement mode devices, and the CMOS device is usually used in enhancement mode.

[0052] The simulation calculation obtained transfer characteristic curve is given for the enhancement mode NMOS. Figure 9 The opening voltage of the NMOS is about 1.1V, the working current after opening is close to 0.7A / mm, and the maximum transconductance is 330mS / mm. The simulation calculation obtained transfer characteristic curve is given for the enhancement mode PMOS. Figure 11 The opening voltage of the PMOS is about-1.4V, the working current after opening is more than 0.13A / mm, and the maximum transconductance is 66mS / mm.

[0053] The present embodiment takes the CMOS composed of the enhancement mode NMOS and PMOS as an example, and the structure is as shown in the figure Figure 12 The CMOS device realizes the conversion of two-dimensional electron gas and two-dimensional hole gas by polarization regulation and induction of the heterojunction interface, so as to form NMOS or PMOS at a specified position. Figure 13 The output characteristic simulation curve obtained by simulation calculation is given, wherein Vds is 5V, the gate width ratio of the NMOS and the PMOS is 1:10, and a relatively symmetrical output curve is obtained.

[0054] For those skilled in the art, other various corresponding changes and deformations can be made according to the technical solutions and concepts described above, and all of these changes and deformations should belong to the protection scope of the claims of the present application.

Claims

1. A GaN-based CMOS device comprising an NMOS and a PMOS with common drain connection; It is characterized in that The NMOS and PMOS have the same structure, with a GaN layer and an ε-Ga2O3 layer epitaxially grown on the same substrate; a dielectric layer is provided on the ε-Ga2O3 layer, and a gate is provided on the dielectric layer; a source electrode and a drain electrode are provided on both sides of the gate electrode, extending vertically to contact the GaN layer; both the GaN layer and the ε-Ga2O3 layer have spontaneous polarization along the c-axis, and the polarization direction of the ε-Ga2O3 layer is controlled by a vertical electric field; The GaN layer and the ε-Ga2O3 layer of the NMOS form an ε-Ga2O3 / GaN heterojunction, and a two-dimensional electron gas is formed at the interface; The GaN layer and the ε-Ga2O3 layer of the PMOS form an ε-Ga2O3 / GaN heterojunction, and a two-dimensional hole gas is formed at the interface; The two-dimensional electron gas and / or two-dimensional hole gas is induced to convert by an electric field perpendicular to the ε-Ga2O3 / GaN heterojunction interface.

2. A GaN-based CMOS device according to claim 1, characterized in that: The NMOS and PMOS are provided with a recessed gate structure.

3. A GaN-based CMOS device according to claim 1, characterized in that: The thickness of the ε-Ga2O3 layer is 5nm to 30nm.

4. The GaN-based CMOS device according to claim 1, wherein: The two-dimensional electron gas density of the NMOS is 3.5×10 20 cm -2 .

5. The GaN-based CMOS device according to claim 1, wherein: The two-dimensional hole density of the PMOS is 5×10 20 cm -2 .

6. A method for preparing a GaN-based CMOS device, comprising epitaxially growing a GaN layer on a substrate; It is characterized in that Epitaxially growing an ε-Ga2O3 layer on the GaN layer, and forming two parallel ε-Ga2O3 / GaN heterojunctions by deep etching; Growing a dielectric layer on each of the ε-Ga2O3 layers; Disposing a source electrode and a drain electrode on each of the GaN layers, so that the source electrode and the drain electrode penetrate the ε-Ga2O3 layer and make ohmic contact with the GaN layer directly below; Laying a gate on each of the dielectric layers; Applying a vertical downward electric field to one of the ε-Ga2O3 / GaN heterojunctions to form a two-dimensional electron gas at the interface of the ε-Ga2O3 / GaN heterojunction; applying a vertical upward electric field to the other ε-Ga2O3 / GaN heterojunction to form a two-dimensional hole gas at the interface of the ε-Ga2O3 / GaN heterojunction; Remove all electrical fields.

7. The preparation method according to claim 6, characterized in that: The vertically downward electric field is applied by a power supply, the positive electrode of the power supply is connected to the gate on the same GaN layer, and the negative electrode of the power supply is connected to the source and drain on the same GaN layer.

8. The preparation method according to claim 6, characterized in that: The vertically upward electric field is applied by another power supply, the negative electrode of which is connected to the gate on the same GaN layer, and the positive electrode of which is connected to the source and drain on the same GaN layer.

9. The preparation method according to claim 6, characterized in that: The applied electric field strength is greater than the coercive field of the ε-Ga2O3 layer.

10. The preparation method according to claim 6, characterized in that: The dielectric layer is grown on the ε-Ga2O3 layer by ALD.

Images