Preparation method of graphene-based quantum resistance chip

Abstract

The present invention provides a method for preparing a quantum resistor chip based on graphene. The method uses hydrogen-annealed silicon carbide as a substrate, silane as a gas catalyst, and acetylene as a carbon source to epitaxially grow a single layer of graphene using chemical vapor deposition. A graphene structure with good uniformity can be prepared. The prepared quantum resistor chip has a Hall resistance measurement accuracy of 1.2×10- ‑8 , and the relative uncertainty reaches 3×10 ‑8 , the reproducibility reaches 3×10 ‑9 The magnetic transport characteristics are highly stable within half a year. The quantum resistor chip has the advantages of miniaturization, high integration, cost optimization, high economic benefits and strong applicability. The quantum resistor chip can be directly integrated into the portable quantum resistance standard measurement system, which is conducive to promoting the further development of the precision measurement industry.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a graphene-based quantum resistance chip. Background Art

[0002] Graphene, with its high carrier mobility and mechanical strength, has attracted widespread attention from researchers worldwide. The preparation of graphene films, particularly on metal substrates, has made significant progress in recent years. However, to facilitate the application of graphene in electronic devices, bypassing the transfer process and directly synthesizing high-quality graphene films on dielectric substrates has become a key trend.

[0003] At present, the preparation of graphene on non-metallic substrates has also been widely studied. For example, graphene has been prepared on the surfaces of silicon carbide (SiC), hexagonal boron nitride (h-BN), silicon dioxide and sapphire substrates. For these substrates, how to grow large-area graphene and minimize the impact of substrate morphology (surface undulations, surface step height, etc.) on the performance of graphene devices remains an important issue that requires further study.

[0004] On the other hand, because the energy space between graphene's discrete Landau levels in a magnetic field is much wider than that of a gallium arsenide-based two-dimensional electron gas, graphene-based quantum resistance standards hold great promise for practical applications. Compared to gallium arsenide-based two-dimensional electron gases, graphene-based quantum resistance chips can operate under more relaxed experimental conditions, such as convenient low-temperature magnetic conditions, lower magnetic field ranges, and higher currents and temperatures. To date, there have been some reports on epitaxial graphene on silicon carbide (SiC). However, the performance of current graphene-based quantum resistance chips varies widely, with low accuracy and poor reproducibility, making them difficult to meet application requirements.

[0005] Therefore, it is necessary to provide a method for preparing a graphene-based quantum resistor chip. Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a method for preparing a graphene-based quantum resistor chip, which is used to solve the problem that the graphene-based quantum resistor chip prepared in the prior art is difficult to meet application requirements.

[0007] To achieve the above and other related objectives, the present invention provides a method for preparing a graphene-based quantum resistor chip, comprising the following steps:

[0008] Providing silicon carbide substrates;

[0009] performing annealing treatment on the silicon carbide substrate;

[0010] Using silane as a gas catalyst and acetylene as a carbon source, a chemical vapor deposition method is used to perform epitaxial growth on the surface of the annealed silicon carbide substrate to obtain a single layer of graphene covering the silicon carbide substrate;

[0011] forming a patterned electrical contact layer on the single-layer graphene;

[0012] Patterning the single-layer graphene to obtain a graphene structure, wherein the graphene structure is in contact with the electrical contact layer;

[0013] forming a patterned bonding electrode layer on the electrical contact layer, wherein the bonding electrode layer is electrically connected to the electrical contact layer;

[0014] performing carrier concentration control on the graphene structure;

[0015] The graphene structure is encapsulated.

[0016] Optionally, when the silicon carbide substrate is annealed, the processing atmosphere is a hydrogen atmosphere, and the processing temperature is 1200° C. to 1400° C.

[0017] Optionally, when preparing the single-layer graphene, the heating temperature is 1200° C. to 1400° C.

[0018] Optionally, the silicon carbide substrate includes a 4H-SiC substrate, and a step height of the silicon carbide substrate after annealing is 0.6 nm to 1.0 nm.

[0019] Optionally, the graphene structure includes a graphene Hall bar structure obtained by an ICP etching method, the etching gas includes oxygen, the etching power includes 180W to 220W, and the etching time includes 100s to 150s.

[0020] Optionally, the channel length of the formed graphene structure is 100 μm to 800 μm, and the channel width is 50 μm to 300 μm.

[0021] Optionally, the cross-sectional area of ​​the bonding electrode layer is greater than the cross-sectional area of ​​the electrical contact layer; the electrical contact layer includes a palladium / gold layer, and the bonding electrode layer includes a titanium / gold layer; in the electrical contact layer, the palladium layer has a thickness of 5 to 10 nm, and the gold layer has a thickness of 30 to 50 nm; in the bonding electrode layer, the titanium layer has a thickness of 5 to 10 nm, and the gold layer has a thickness of 50 to 100 nm.

[0022] Optionally, the steps of forming the electrical contact layer, the graphene structure and the bonding electrode layer include:

[0023] Providing a mask and placing it on the surface of the single-layer graphene;

[0024] depositing a palladium / gold layer by electron beam evaporation or magnetron sputtering to form an electrical contact layer on the single-layer graphene;

[0025] removing the mask;

[0026] The graphene structure was obtained by ICP etching;

[0027] Applying photoresist, exposing the photoresist by laser direct writing or electron beam exposure, and then developing the exposed area to reveal the electrical contact layer;

[0028] Depositing a titanium / gold layer by electron beam evaporation or magnetron sputtering to form a bonding electrode layer on the electrical contact layer;

[0029] The photoresist is removed.

[0030] Optionally, the method for regulating the carrier concentration of the graphene structure includes modifying the graphene structure with nitric acid, and regulating the carrier concentration of the graphene structure to the Dirac point before packaging.

[0031] Optionally, the packaging material includes MMA or PMMA.

[0032] As described above, the method for preparing a graphene-based quantum resistor chip of the present invention uses hydrogen-annealed silicon carbide as a substrate, silicon ethane as a gas catalyst, and acetylene as a carbon source, and adopts chemical vapor deposition to epitaxially grow a single layer of graphene. A graphene structure with good uniformity can be prepared at 1200°C to 1400°C, so that the step height of the silicon carbide substrate remains unchanged after the graphene is grown.

[0033] The quantum resistor chip prepared by the present invention has a Hall resistance measurement accuracy of 1.2×10 -8 , and the relative uncertainty reaches 3×10 -8 , the reproducibility reaches 3×10 -9 The magnetic transport characteristics are highly stable within half a year. The quantum resistor chip has the advantages of miniaturization, high integration, cost optimization, high economic benefits and strong applicability. The quantum resistor chip can be directly integrated into the portable quantum resistance standard measurement system, which is conducive to promoting the further development of the precision measurement industry. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Shown is a process flow chart of a method for preparing a graphene-based quantum resistor chip in an embodiment of the present invention.

[0035] Figure 2 Shown is a schematic structural diagram of a silicon carbide substrate provided in an embodiment of the present invention.

[0036] Figure 3 Shown is a schematic diagram of the structure after forming a single layer of graphene in an embodiment of the present invention.

[0037] Figure 4 It is a schematic diagram of the structure after the electrical contact layer is formed in an embodiment of the present invention.

[0038] Figure 5 Shown is a schematic structural diagram after a graphene structure is formed in an embodiment of the present invention.

[0039] Figure 6 It is a schematic structural diagram after forming a bonding electrode layer in an embodiment of the present invention.

[0040] Figure 7 Shown is an atomic force microscope scan of a single-layer graphene formed on a silicon carbide substrate in an embodiment of the present invention.

[0041] Figure 8 Shown is an optical microscope image of a quantum resistor chip according to an embodiment of the present invention.

[0042] Figure 9 Shown is a comparison diagram of the magnetotransport measurement characteristic curves of the quantum resistor chip in an embodiment of the present invention.

[0043] Figure 10 The figure shows a scatter plot of the longitudinal resistivity of the quantum resistor chip according to an embodiment of the present invention under magnetic field strengths of 4T to 6T and different currents.

[0044] Figure 11 The graph shows the accuracy, relative uncertainty, and reproducibility of the Hall resistance Rxy of the quantum resistor chip within 15 days according to an embodiment of the present invention.

[0045] Component number description

[0046] 100 Silicon Carbide Substrate

[0047] 200 single-layer graphene

[0048] 201 Graphene Structure

[0049] 300 electrical contact layer

[0050] 400 bonding electrode layer

[0051] a Channel length

[0052] b Channel width

[0053] Steps S1 to S8 DETAILED DESCRIPTION

[0054] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0056] For ease of description, spatial relational terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers. Among them, when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or indirectly connected to the other element.

[0057] Expressions such as "between..." may be used herein to indicate inclusiveness of both endpoints, and expressions such as "plurality" may be used to indicate two or more, unless otherwise specifically limited. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features.

[0058] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0059] like Figure 1 As shown, this embodiment provides a method for preparing a graphene-based quantum resistor chip, comprising the following steps:

[0060] S1: Provide silicon carbide substrate;

[0061] S2: performing annealing treatment on the silicon carbide substrate;

[0062] S3: epitaxially growing graphene on the surface of the annealed silicon carbide substrate using ethylene glycol as a gas catalyst and acetylene as a carbon source by chemical vapor deposition to obtain a single layer of graphene covering the silicon carbide substrate;

[0063] S4: forming a patterned electrical contact layer on the single-layer graphene;

[0064] S5: patterning the single-layer graphene to obtain a graphene structure, wherein the graphene structure is in contact with the electrical contact layer;

[0065] S6: forming a patterned bonding electrode layer on the electrical contact layer, wherein the bonding electrode layer is electrically connected to the electrical contact layer;

[0066] S7: regulating the carrier concentration of the graphene structure;

[0067] S8: Encapsulating the graphene structure.

[0068] The following is combined with Figures 2 to 6 The preparation method of the quantum resistor chip is further introduced.

[0069] First, see Figure 2 , perform step S1 to provide a silicon carbide substrate 100.

[0070] Next, step S2 is performed to perform annealing on the silicon carbide substrate 100 .

[0071] As an example, when the silicon carbide substrate 100 is annealed, the processing atmosphere is a hydrogen atmosphere, and the processing temperature may be 1200° C. to 1400° C.

[0072] Specifically, the steps of the initially provided silicon carbide substrate 100 are blurred. After the silicon carbide substrate 100 is annealed in a hydrogen atmosphere and at an annealing temperature of 1200°C to 1400°C, such as 1200°C, 1300°C, 1400°C, etc., the step height of the silicon carbide substrate 100 can be made uniform and clear, thereby facilitating the improvement of the performance of the subsequently prepared graphene.

[0073] As an example, the silicon carbide substrate 100 may include a 4H-SiC substrate, and the step height of the silicon carbide after annealing may include 0.6 nm to 1.0 nm, such as 0.6 nm, 0.7 nm, 0.8 nm, 1.0 nm, etc.

[0074] See Figure 7In this embodiment, the silicon carbide substrate 100 is a 4H-SiC substrate, and after annealing, the step height of the silicon carbide substrate 100 is 0.7 nm, but the type of the silicon carbide substrate 100 is not limited thereto.

[0075] Next, see Figure 3 , executing step S3, using ethylene glycol as a gas catalyst and acetylene as a carbon source, using chemical vapor deposition to perform epitaxial growth on the surface of the silicon carbide substrate 100 after annealing, to obtain a single layer of graphene 200 covering the silicon carbide substrate 100.

[0076] As an example, when preparing the single-layer graphene 200 , the heating temperature may be 1200° C. to 1400° C.

[0077] Specifically, when preparing the single-layer graphene 200, the heating temperature in the CVD furnace can be 1200°C, 1250°C, 1300°C, 1400°C, etc. In this embodiment, at a temperature of 1300°C, in a low-pressure CVD furnace, using ethylene glycol as a gas catalyst and acetylene as a carbon source, chemical vapor deposition (CVD) is performed on the silicon carbide substrate 100 to epitaxially grow the single-layer graphene 200 covering the entire surface of the silicon carbide substrate 100. The silicon carbide substrate 100 remaining after the growth is located below the single-layer graphene 200.

[0078] Next, see Figure 4 , executing step S4 to form a patterned electrical contact layer 300 on the single-layer graphene 200 .

[0079] As an example, the electrical contact layer 300 may include a palladium / gold layer, wherein, in the electrical contact layer 300, the palladium layer may have a thickness of 5 to 10 nm, such as 5 nm, 8 nm, 10 nm, etc., and the gold layer may have a thickness of 30 to 50 nm, such as 30, 45 nm, 50 nm, etc., but the materials and thicknesses of the layers in the electrical contact layer 300 are not limited thereto and may be selected as needed.

[0080] Next, see Figure 5 , executing step S5 , patterning the single-layer graphene 200 to obtain a graphene structure 201 , and the graphene structure 201 is in contact with the electrical contact layer 300 .

[0081] As an example, the graphene structure 201 may include a graphene Hall bar structure obtained by an ICP etching method, and the etching gas is oxygen, the etching power is 180W to 220W, such as 180W, 200W, 220W, etc., and the etching time is 100s to 150s, such as 100s, 120s, 150s, etc., but the graphene structure 201 is not limited to a graphene Hall bar structure and can be selected according to needs, and no excessive limitation is made here.

[0082] As an example, the channel length of the formed graphene structure 200 is 100 μm to 800 μm, and the channel width is 50 μm to 300 μm.

[0083] For details, see Figure 7 An atomic force microscope scan of the single-layer graphene 200 epitaxially grown on the silicon carbide substrate 100 is shown. In this embodiment, the silicon carbide substrate 100 adopts semi-insulating 4H-SiC and has a step with a height of 0.7 nm. After the single-layer graphene 200 is grown, the step height remains unchanged.

[0084] See Figure 8 An optical microscope image of the graphene Hall bar structure 201 formed by patterning the single-layer graphene 200 is shown, wherein the channel length a is 600 microns and the channel width b is 200 microns, but is not limited to this. The channel length a can also be 100μm, 200μm, 400μm, 800μm, etc., and the channel width b can be 50μm, 100μm, 300μm, etc. The specific values ​​of the channel length a and the channel length b can be selected according to needs and are not overly limited here.

[0085] Next, see Figure 6 , executing step S6 to form a patterned bonding electrode layer 400 on the electrical contact layer 300 , and the bonding electrode layer 400 is electrically connected to the electrical contact layer 300 .

[0086] Specifically, in this embodiment, a composite metal electrode having the electrical contact layer 300 and the bonding electrode layer 400 is used to improve the contact resistance of the single-layer graphene 200 , thereby improving device performance.

[0087] As an example, the bonding electrode layer 400 may include a titanium / gold layer; in the bonding electrode layer 400, the thickness of the titanium layer may be 5 to 10 nm, such as 5 nm, 8 nm, 10 nm, and the thickness of the gold layer may be 50 to 100 nm, such as 50 nm, 80 nm, 100 nm, etc., but the material and thickness of each layer in the bonding electrode layer 400 are not limited to this and can also be selected according to needs.

[0088] As an example, the cross-sectional area of ​​the bonding electrode layer 400 is larger than the cross-sectional area of ​​the electrical contact layer 300 to facilitate subsequent electrical connection.

[0089] in, Figure 6 Since it is a three-dimensional view and the cross-sectional area of ​​the bonding electrode layer 400 is larger than the cross-sectional area of ​​the electrical contact layer 300 , the electrical contact layer 300 located below the bonding electrode layer 400 is not shown.

[0090] As an example, the steps of forming the electrical contact layer 300 , the graphene structure 201 and the bonding electrode layer 400 may include:

[0091] Providing a mask (not shown) and placing it on the surface of the single-layer graphene 200;

[0092] Depositing a palladium / gold layer by electron beam evaporation or magnetron sputtering to form an electrical contact layer 300 on the single-layer graphene 200;

[0093] removing the mask;

[0094] The graphene structure was obtained by ICP etching;

[0095] Applying a photoresist (not shown), exposing the photoresist by laser direct writing or electron beam exposure, and then developing the exposed area to reveal the electrical contact layer 300;

[0096] Depositing a titanium / gold layer by electron beam evaporation or magnetron sputtering to form a bonding electrode layer 400 on the electrical contact layer 300;

[0097] The photoresist is removed.

[0098] Next, step S7 is performed to control the carrier concentration of the graphene structure.

[0099] As an example, the method for regulating the carrier concentration of the graphene structure includes modifying the graphene structure with nitric acid, and before packaging, regulating the carrier concentration of the graphene structure to the Dirac point, that is, the point where the graphene resistance value is maximum.

[0100] Next, step S8 is performed to encapsulate the graphene structure (not shown) to protect the graphene structure and improve device performance. The encapsulation material may include MMA or PMMA, but is not limited thereto.

[0101] See Figure 9A comparison of the magnetotransport characteristic curves of the quantum resistor chip measured six months ago and now is shown. The solid black line shows the magnetic field dependence of the longitudinal resistance Rxx(a) measured six months ago, the dotted black line shows the magnetic field dependence of the Hall resistance Rxy(a) measured six months ago, the dashed black line shows the magnetic field dependence of the current chip's longitudinal resistance Rxx(b), and the dashed black line shows the magnetic field dependence of the current chip's Hall resistance Rxy(b).

[0102] It can be seen that the magnetic transport characteristics of the chip have maintained a high degree of stability within half a year. The measurement results half a year ago and now show that the quantum resistor chip enters full quantization near 2T, showing a longitudinal resistance R xx It begins to enter the zero platform around 2T and maintains this platform until 6T, while the Hall resistance Rxy enters the quantum Hall platform around 1.5T. The value of the quantum Hall resistance platform is h / 2e 2 , unit Ω, where h is Planck constant and e is electron charge value. At 4.5K, the carrier concentration of the quantum resistor chip reaches 7.8×10 10 cm -2 In the magnetic field range of 4T to 6T, the quantum resistor chip is in a completely quantized state, and the longitudinal resistivity is less than 10mΩ / □. Figure 10 .

[0103] Figure 11 The Hall resistance R of the quantum resistor chip within 15 days is shown. xy The accuracy, relative uncertainty and reproducibility of the chip are shown in Figure 2. At a magnetic field strength of 6 T and a temperature of 4.5 K, the Hall resistance measurement accuracy of the chip (horizontal dotted line) reaches 1.2×10 -8 , and the relative uncertainty (half of the vertical error bar) reaches 3×10 -8 The reproducibility within 15 days (the standard deviation of the Hall resistance value within 15 days divided by its mean) reached 3×10 -9 .

[0104] In summary, the method for preparing a graphene-based quantum resistor chip of the present invention uses hydrogen-annealed silicon carbide as a substrate, ethylene glycol as a gas catalyst, and acetylene as a carbon source, and adopts chemical vapor deposition to epitaxially grow a single layer of graphene. A graphene structure with good uniformity can be prepared at 1200°C to 1400°C, so that the step height of the silicon carbide substrate remains unchanged after the graphene is grown.

[0105] The quantum resistor chip prepared by the present invention has a Hall resistance measurement accuracy of 1.2×10 -8 , and the relative uncertainty reaches 3×10 -8, the reproducibility reaches 3×10 -9 The magnetic transport characteristics are highly stable within half a year. The quantum resistor chip has the advantages of miniaturization, high integration, cost optimization, high economic benefits and strong applicability. The quantum resistor chip can be directly integrated into the portable quantum resistance standard measurement system, which is conducive to promoting the further development of the precision measurement industry.

[0106] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a graphene-based quantum resistor chip, characterized in that: The following steps are involved: Providing silicon carbide substrates; performing annealing treatment on the silicon carbide substrate; Using silane as a gas catalyst and acetylene as a carbon source, a chemical vapor deposition method is used to perform epitaxial growth on the surface of the annealed silicon carbide substrate to obtain a single layer of graphene covering the silicon carbide substrate; forming a patterned electrical contact layer on the single-layer graphene; Patterning the single-layer graphene to obtain a graphene structure, wherein the graphene structure is in contact with the electrical contact layer; A patterned bonding electrode layer is formed on the electrical contact layer, and the bonding electrode layer is electrically connected to the electrical contact layer, the electrical contact layer includes a palladium / gold layer, and the bonding electrode layer includes a titanium / gold layer; in the electrical contact layer, the palladium layer has a thickness of 5 to 10 nm, and the gold layer has a thickness of 30 to 50 nm; in the bonding electrode layer, the titanium layer has a thickness of 5 to 10 nm, and the gold layer has a thickness of 50 to 100 nm, and the cross-sectional area of ​​the bonding electrode layer is larger than the cross-sectional area of ​​the electrical contact layer; performing carrier concentration control on the graphene structure; encapsulating the graphene structure; The steps of forming the electrical contact layer, the graphene structure and the bonding electrode layer include: Providing a mask and placing it on the surface of the single-layer graphene; depositing a palladium / gold layer by electron beam evaporation or magnetron sputtering to form an electrical contact layer on the single-layer graphene; removing the mask; The graphene structure was obtained by ICP etching; Applying photoresist, exposing the photoresist by laser direct writing or electron beam exposure, and then developing the exposed area to reveal the electrical contact layer; Depositing a titanium / gold layer by electron beam evaporation or magnetron sputtering to form a bonding electrode layer on the electrical contact layer; The photoresist is removed.

2. The method for preparing a graphene-based quantum resistor chip according to claim 1, wherein: When the silicon carbide substrate is annealed, the processing atmosphere is a hydrogen atmosphere, and the processing temperature ranges from 1200° C. to 1400° C.

3. The method for preparing a graphene-based quantum resistor chip according to claim 1, wherein: When preparing the single-layer graphene, the heating temperature is 1200° C. to 1400° C.

4. The method for preparing a graphene-based quantum resistor chip according to claim 1, wherein: The silicon carbide substrate includes a 4H-SiC substrate, and a step height of the silicon carbide substrate after annealing is within a range of 0.6 nm to 1.0 nm.

5. The method for preparing a graphene-based quantum resistor chip according to claim 1, wherein: The graphene structure includes a graphene Hall bar structure obtained by an ICP etching method, wherein the etching gas is oxygen, the etching power is 180W to 220W, and the etching time is 100s to 150s.

6. The method for preparing a graphene-based quantum resistor chip according to claim 1, wherein: The channel length of the formed graphene structure is 100 μm to 800 μm, and the channel width is 50 μm to 300 μm.

7. The method for preparing a graphene-based quantum resistor chip according to claim 1, wherein: The method for regulating the carrier concentration of the graphene structure includes modifying the graphene structure with nitric acid, and regulating the carrier concentration of the graphene structure to the Dirac point before packaging.

8. The method for preparing a graphene-based quantum resistor chip according to claim 1, wherein: The packaging material includes MMA and PMMA.

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