A data transmission system, method, device and storage medium

Abstract

The present invention discloses a data transmission system, comprising: a controller chip, a printed circuit board, and at least one memory chipset; the memory chipset comprises a surface memory chip and a bottom memory chip; the high-byte signal line of the first sub-channel in the controller chip extends from the high-byte pin of the first sub-channel to the first preset area along the first direction on the surface layer, and enters the second wiring inner layer through a via in the first preset area, and then connects to the bottom memory chip after passing through the second wiring inner layer; wherein the first direction is the direction away from the low-byte pin of the second sub-channel. The technical solution of the embodiment of the present invention avoids the problem of large crosstalk caused by long-distance surface wiring without increasing the process complexity of manufacturing the printed circuit board, reduces the signal transmission impedance and external interference, improves the stability of the data transmission system, and avoids the crosstalk problem caused by the signal line being too close to the via.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a data transmission system, method, device and storage medium. Background Art

[0002] With the continuous increase in chip density and transmission rate, higher requirements are placed on the design of high-speed parallel transmission channels, and how to ensure signal integrity has become particularly important.

[0003] In the prior art, in order to ensure that the interconnection design between the controller chip and the memory chip has a high-speed parallel transmission channel, some routing channels are usually released through surface routing, or the number of layers of the printed circuit board (PCB) is increased to increase the number of routing channels.

[0004] However, the crosstalk of surface routing is large, the impedance is difficult to control, and it is easily affected by external interference, which reduces the stability of the system; the increase in the number of PCB layers has significantly increased the hardware cost and increased the complexity of the PCB manufacturing process. Summary of the invention

[0005] The present invention provides a data transmission system, method, device and storage medium to solve the crosstalk problem of high-speed parallel channels in a printed circuit board.

[0006] According to one aspect of the present invention, there is provided a data transmission system, comprising: a controller chip, a printed circuit board, and at least one memory chipset; the controller chip is located on the surface layer of the printed circuit board, and the memory chipset comprises a surface memory chip and a bottom memory chip;

[0007] The printed circuit board comprises a first wiring inner layer and a second wiring inner layer, the first wiring inner layer is connected to the surface layer memory chip, the second wiring inner layer is connected to the bottom layer memory chip, and the distance between the first wiring inner layer and the surface layer is smaller than the distance between the second wiring inner layer and the surface layer;

[0008] The controller chip includes at least one channel, the channel includes a first sub-channel and a second sub-channel, and the first sub-channel and the second sub-channel both include a low-byte pin and a high-byte pin;

[0009] The high-byte signal line of the first sub-channel extends from the high-byte pin of the first sub-channel to the first preset area along the first direction on the surface layer, and enters the second wiring inner layer through a via in the first preset area; wherein the first direction is the direction away from the low-byte pin of the second sub-channel.

[0010] The low-byte signal line of the first subchannel enters the first wiring inner layer through a blind hole or a back-drilled through hole under the low-byte pin of the first subchannel; and / or the low-byte signal line of the second subchannel enters the first wiring inner layer through a blind hole or a back-drilled through hole under the low-byte pin of the second subchannel. When the low-byte signal line enters the first wiring inner layer through the blind hole, the setting of the blind hole not only releases the surface space of the printed circuit board and improves electromagnetic compatibility, but also reduces signal residue and improves signal transmission quality; and when the low-byte signal line enters the first wiring inner layer through the back-drilled through hole under the current low-byte pin, the back-drilled through hole reduces noise interference and improves signal integrity, while ensuring signal transmission quality, reducing the process complexity of manufacturing printed circuit boards.

[0011] The first wiring inner layer is connected to the surface memory chip through a blind hole; and / or the second wiring inner layer is connected to the bottom memory chip through a blind hole. After the low-order byte signal line passes through the first wiring inner layer, it enters the surface memory chip through a blind hole, avoiding the existence of a via stub (stub), meeting the high-speed transmission requirements, and at the same time, ensuring that the vias in the surface memory chip area do not drill through the printed circuit board, avoiding interference with the signal fan-out of the bottom memory chip; after the high-order byte signal passes through the second wiring inner layer, it enters the bottom memory chip through a blind hole, also avoiding the existence of a via stub (stub), meeting the high-speed transmission requirements, and at the same time, ensuring that the vias in the bottom memory chip area do not drill through the printed circuit board, avoiding interference with the signal fan-out of the surface memory chip.

[0012] The high-byte signal line of the second subchannel enters the second wiring inner layer through the through hole or the back-drilled through hole below the high-byte pin of the second subchannel; and / or the high-byte signal line of the first subchannel enters the second wiring inner layer through the through hole or the back-drilled through hole in the first preset area. When the high-byte signal line enters the second wiring inner layer through the through hole, the setting of the through hole greatly reduces the process complexity of manufacturing the printed circuit board and reduces the hardware cost of the data transmission system; when the high-byte signal line enters the second wiring inner layer through the back-drilled through hole, the back-drilled through hole reduces noise interference and improves signal integrity. While ensuring the quality of signal transmission, it also reduces the process complexity of manufacturing the printed circuit board.

[0013] The boundary length of the first preset area in the first vertical direction is less than the boundary length of the area where the high-byte pin of the first sub-channel is located in the first vertical direction; wherein the first vertical direction is the vertical direction of the line between the center point of the high-byte pin of the first sub-channel and the center point of the bottom memory chip. Since the boundary length of the first preset area in the first vertical direction is less than the boundary length of the area where the high-byte pin of the first sub-channel is located, the shielding range of the low-byte signal line led out of the low-byte pin of the second sub-channel is reduced, the wiring space of the inner layer of the first wiring is expanded, and the distance between the low-byte signal line of the second sub-channel and the via corresponding to the high-byte pin of the first sub-channel is further increased, thereby avoiding the crosstalk problem caused by the signal line and the via being too close.

[0014] The first preset area includes at least one rectangular via area, the rectangular via area includes at least one signal hole group, the signal hole group includes two signal holes arranged diagonally and two ground holes arranged diagonally; each signal hole group is spaced by at least one ground hole group, the ground hole group includes two vertically arranged ground holes. The rectangular via area allows two rows of vias to be regularly arranged in the current area without redundant boundaries. At the same time, the signal hole group and the ground hole group are arranged so that each signal hole is surrounded by at least two ground holes, most of the signal holes are surrounded by three or more ground holes, and there is only one signal hole close to each signal hole, so that the crosstalk between the signal holes is greatly reduced while occupying a smaller surface space.

[0015] The low-order byte signal line of the second sub-channel extends from the low-order byte pin of the second sub-channel to the second preset area along the second direction on the surface layer, and enters the first wiring inner layer through the via in the second preset area; wherein, the second direction is the direction away from the high-order byte pin of the first sub-channel. The above technical scheme also allows the low-order byte signal of the second sub-channel to have sufficient wiring space in the first wiring layer, ensuring that the low-order byte signal line of the second sub-channel is away from the via corresponding to the high-order byte signal line of the first sub-channel, thereby avoiding the crosstalk problem caused by the signal line and the via being too close; in particular, due to the surface layout limitation of the printed circuit board, when the surface space does not have the first preset area, the low-order byte signal line of the second sub-channel can be set by setting the reverse second preset area to make the low-order byte signal line of the second sub-channel away from the via corresponding to the high-order byte signal line of the first sub-channel, thereby increasing the adaptability of the printed circuit board.

[0016] According to one aspect of the present invention, there is provided a data transmission method, which is applied to a data transmission system and includes:

[0017] The controller chip transmits the high-byte signal of the first sub-channel to the bottom storage chip through the high-byte signal line of the first sub-channel, and transmits the high-byte signal of the second sub-channel to the bottom storage chip through the high-byte signal line of the second sub-channel;

[0018] Wherein, the high-byte signal line of the first sub-channel extends from the high-byte pin of the first sub-channel to the first preset area along the first direction on the surface layer, and enters the second wiring inner layer through a via in the first preset area;

[0019] The controller chip transmits the low-byte signal of the first sub-channel to the surface storage chip through the low-byte signal line of the first sub-channel, and transmits the low-byte signal of the second sub-channel to the surface storage chip through the low-byte signal line of the second sub-channel.

[0020] According to one aspect of the present invention, there is provided a data transmission device, which is applied to a data transmission system and includes:

[0021] a high-byte signal transmission module, configured in the controller chip, for transmitting the high-byte signal of the first sub-channel to the bottom storage chip through the high-byte signal line of the first sub-channel, and transmitting the high-byte signal of the second sub-channel to the bottom storage chip through the high-byte signal line of the second sub-channel;

[0022] Wherein, the high-byte signal line of the first sub-channel extends from the high-byte pin of the first sub-channel to the first preset area along the first direction on the surface layer, and enters the second wiring inner layer through a via in the first preset area;

[0023] A low-byte signal transmission module is configured in the controller chip, and is used to transmit the low-byte signal of the first sub-channel to the surface storage chip through the low-byte signal line of the first sub-channel, and to transmit the low-byte signal of the second sub-channel to the surface storage chip through the low-byte signal line of the second sub-channel.

[0024] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the data transmission method described in any embodiment of the present invention when executed.

[0025] According to the technical solution of the embodiment of the present invention, the high-byte signal line of the first sub-channel in the controller chip extends from the high-byte pin of the first sub-channel to the first preset area along the first direction on the surface of the printed circuit board, enters the second wiring inner layer through a via in the first preset area, and then connects to the bottom storage chip after passing through the second wiring inner layer, so that the problem of large crosstalk caused by long-distance surface wiring is avoided without increasing the number of layers of the printed circuit board and the process complexity of manufacturing the printed circuit board, the signal transmission impedance and external interference are reduced, and the stability of the data transmission system is improved. In addition, the crosstalk problem caused by the close distance between the signal line and the via is avoided.

[0026] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1A is a structural diagram of a data transmission system provided according to Embodiment 1 of the present invention;

[0029] Figure 1B is a structural diagram of a data transmission system provided according to Embodiment 1 of the present invention;

[0030] Figure 1C is a structural diagram of a data transmission system provided according to Embodiment 1 of the present invention;

[0031] Figure 1D is a schematic diagram of the structure of a controller chip provided according to Embodiment 1 of the present invention;

[0032] Figure 1E Schematic diagram of a transmission method of a low-order byte signal and a high-order byte signal provided according to Embodiment 1 of the present invention;

[0033] Figure 1F is a schematic structural diagram of a first wiring inner layer provided according to Embodiment 1 of the present invention;

[0034] Figure 1G is a schematic diagram of the structure of the second wiring inner layer provided according to the first embodiment of the present invention;

[0035] Figure 1HSchematic diagram of the positional relationship between the low-byte signal line of the second sub-channel and the via hole below the high-byte pin of the first sub-channel provided in Embodiment 1 of the present invention;

[0036] Figure 2A is a schematic diagram of the structure of the first preset area provided according to the second embodiment of the present invention;

[0037] Figure 2B is a schematic diagram of an arrangement of signal holes and ground holes in a first preset area provided in accordance with a second embodiment of the present invention;

[0038] Figure 2C is a schematic diagram of an arrangement of signal holes and ground holes provided according to the second embodiment of the present invention;

[0039] Figure 3 is a flowchart of a data transmission method provided according to Embodiment 3 of the present invention;

[0040] Figure 4 It is a structural diagram of a data transmission device provided according to Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] Embodiment 1

[0044] Figure 1AThis is a structural schematic diagram of a data transmission system disclosed in Embodiment 1 of the present invention, the system comprising: a controller chip 100, a printed circuit board 200 and at least one storage chipset 300; the controller chip 100 is located on the surface of the printed circuit board 200, and the storage chipset 300 comprises a surface storage chip 301 and a bottom storage chip 302.

[0045] The controller chip 100 is used to send transmission data to the storage chip, which may specifically include a GPU (graphics processing unit), a CPU (central processing unit) or other chips with data transmission function; the storage chipset 300 is composed of two storage chips, namely, a surface storage chip 301 located on the surface of the printed circuit board 200 and a bottom storage chip 302 located on the bottom of the printed circuit board 200. Figure 1B As shown, the front surface of the surface storage chip 301 is attached to the surface of the printed circuit board 200, and the back surface of the bottom storage chip 302 is attached to the bottom of the printed circuit board 200; the storage chip is used to receive and store the transmission data sent by the controller chip 100, and specifically may include GDDR6 (Graphics Double Data Rate, version 6, the sixth generation graphics double data rate memory) and the like. Figure 1C As shown, when the data transmission system includes multiple storage chipsets 300, the surface storage chips 301 in each storage chipset 300 are sequentially attached to the surface of the PCB on the front side, and the bottom storage chips 302 in each storage chipset 300 are sequentially attached to the bottom of the PCB on the back side; in the embodiment of the present invention, optionally, the types of the controller chip 100 and the storage chips are not specifically limited.

[0046] The controller chip 100 includes at least one channel 110, and the channel 110 includes a first sub-channel 111 and a second sub-channel 112, and the first sub-channel 111 and the second sub-channel 112 both include low-byte pins and high-byte pins. The controller chip 100 may include one or more channels 110 according to its performance requirements, and in order to achieve high-performance processing, each channel 110 includes a dual-channel interface, that is, two sub-channels, namely, a first sub-channel 111 and a second sub-channel 112; low-byte signals and high-byte signals are defined in each sub-channel; obviously, low-byte signals are sent through low-byte pins, and high-byte signals are sent through high-byte pins; low-byte pins of different sub-channels in a channel are arranged in a diagonal manner, and high-byte pins of different sub-channels are also arranged in a diagonal manner.

[0047] like Figure 1DAs shown, taking the above-mentioned GDDR6 as an example, its corresponding controller chip 100 includes eight channels 110, namely channel A, channel B, channel C, channel D, channel E, channel F, channel G, and channel H. The low-order byte pins of the first sub-channel 111 in each channel 110 are arranged diagonally with the low-order byte pins of the second sub-channel 112, and the high-order byte pins of the first sub-channel 111 and the high-order byte pins of the second sub-channel 112 are also arranged diagonally. The low-order byte signal and the high-order byte signal of each sub-channel include 9 data lines and a group of reference clock lines; wherein the number of reference clock lines can be set as needed, for example, set to 2 reference clock lines.

[0048] The printed circuit board 200 includes a first wiring inner layer 201 and a second wiring inner layer 202, wherein the first wiring inner layer 201 is connected to the surface memory chip 301, and the second wiring inner layer 202 is connected to the bottom memory chip 302, and the distance between the first wiring inner layer 201 and the surface layer is smaller than the distance between the second wiring inner layer 202 and the surface layer. The first wiring inner layer 201 is used to carry the low-order byte signal line of the controller chip 100, and the first wiring inner layer 201 is connected to the surface memory chip 301, so that the low-order byte signal line transmits the low-order byte signal to the surface memory chip 301, so the first wiring inner layer 201 is closer to the surface layer; the second wiring inner layer 202 is used to carry the high-order byte signal line of the controller chip 100, and the second wiring inner layer 202 is connected to the bottom memory chip 302, so that the high-order byte signal line transmits the high-order byte signal to the bottom memory chip 302, so the second wiring inner layer 202 is closer to the bottom layer.

[0049] like Figure 1E As shown, the low-order byte signal of the first sub-channel 111 is transmitted to the surface storage chip 301, and the low-order byte signal of the second sub-channel 112 is also transmitted to the surface storage chip 301, and the storage positions of the above-mentioned low-order byte signals in the surface storage chip 301 are also arranged in a diagonal manner; similarly, the high-order byte signal of the first sub-channel 111 is transmitted to the bottom storage chip 302, and the high-order byte signal of the second sub-channel 112 is also transmitted to the bottom storage chip 302, and the storage positions of the above-mentioned high-order byte signals in the bottom storage chip 302 are also arranged in a diagonal manner.

[0050] like Figure 1FAs shown, after the low-order byte signal line of the first sub-channel 111 is led out from the low-order byte pin of the first sub-channel 111 of the controller chip 100, it enters the first wiring inner layer 201 through the via hole located below the low-order byte pin of the first sub-channel 111, passes through the first wiring inner layer 201, and then passes through the via hole below the surface storage chip 301 to connect to the surface storage chip 301, thereby the controller chip 100 transmits the low-order byte signal of the first sub-channel 111 to the surface storage chip 301; similarly, after the low-order byte signal line of the second sub-channel 112 is led out from the low-order byte pin of the second sub-channel 112 of the controller chip 100, it enters the first wiring inner layer 201 through the via hole located below the low-order byte pin of the second sub-channel 112, passes through the first wiring inner layer 201, and then passes through the via hole below the surface storage chip 301 to connect to the surface storage chip 301, thereby the controller chip 100 transmits the low-order byte signal of the second sub-channel 112 to the surface storage chip 301.

[0051] Optionally, in an embodiment of the present invention, the low-byte signal line of the first subchannel 111 enters the first wiring inner layer 201 through a blind hole or a back-drilled through hole below the low-byte pin of the first subchannel 111; and / or the low-byte signal line of the second subchannel 112 enters the first wiring inner layer 201 through a blind hole or a back-drilled through hole below the low-byte pin of the second subchannel 112. When the low-byte signal line enters the first wiring inner layer 201 through the blind hole, the setting of the blind hole not only releases the surface space of the printed circuit board 200 and improves electromagnetic compatibility, but also reduces signal residue and improves signal transmission quality; and when the low-byte signal line enters the first wiring inner layer 201 through the back-drilled through hole below the current low-byte pin, the back-drilled through hole reduces noise interference and improves signal integrity, thereby reducing the process complexity of manufacturing the printed circuit board 200 while ensuring signal transmission quality.

[0052] Optionally, in an embodiment of the present invention, the first wiring inner layer 201 is connected to the surface memory chip 301 through a blind hole; and / or the second wiring inner layer 202 is connected to the bottom memory chip 302 through a blind hole. After the low-order byte signal line passes through the first wiring inner layer 201, it enters the surface memory chip 301 through a blind hole, avoiding the existence of a via stub (stub), meeting the high-speed transmission requirement, and at the same time, ensuring that the via in the area of ​​the surface memory chip 301 does not drill through the printed circuit board 200, avoiding interference with the signal fan-out of the bottom memory chip 302; after the high-order byte signal passes through the second wiring inner layer 202, it enters the bottom memory chip 302 through a blind hole, also avoiding the existence of a via stub (stub), meeting the high-speed transmission requirement, and at the same time, ensuring that the via in the area of ​​the bottom memory chip 302 does not drill through the printed circuit board 200, avoiding interference with the signal fan-out of the surface memory chip 301.

[0053] Optionally, in an embodiment of the present invention, the high-byte signal line of the second sub-channel 112 enters the second wiring inner layer 202 through a through hole or a back-drilled through hole below the high-byte pin of the second sub-channel 112; and / or the high-byte signal line of the first sub-channel 111 enters the second wiring inner layer 202 through a through hole or a back-drilled through hole in the first preset area. When the high-byte signal line enters the second wiring inner layer 202 through the through hole, the provision of the through hole greatly reduces the process complexity of manufacturing the printed circuit board 200 and reduces the hardware cost of the data transmission system; when the high-byte signal line enters the second wiring inner layer 202 through the back-drilled through hole, the back-drilled through hole reduces noise interference and improves signal integrity, while ensuring the signal transmission quality, it also reduces the process complexity of manufacturing the printed circuit board 200.

[0054] The high-byte signal line of the first sub-channel 111 extends from the high-byte pin of the first sub-channel 111 to the first preset area along the first direction on the surface layer, and enters the second wiring inner layer 202 through a via in the first preset area; wherein the first direction is the direction away from the low-byte pin of the second sub-channel 112.

[0055] Specifically, Figure 1GAs shown, the high-byte signal line of the second sub-channel 112 is led out from the high-byte pin of the second sub-channel 112 of the controller chip 100, enters the second wiring inner layer 202 through the via hole located below the high-byte pin of the second sub-channel 112, passes through the second wiring inner layer 202, and then connects to the bottom memory chip 302 through the via hole above the bottom memory chip 302, so that the controller chip 100 transmits the high-byte signal of the second sub-channel 112 to the surface memory chip 301; and the high-byte signal line of the first sub-channel 111 is led out from the first sub-channel of the controller chip 100 to the surface memory chip 301; After the high-byte pin of the first sub-channel 111 is led out, it is first extended on the surface along the direction away from the low-byte pin of the second sub-channel 112 until it extends to the first preset area, and then passes through the via hole in the first preset area to enter the second wiring inner layer 202. After passing through the second wiring inner layer 202, it is connected to the bottom memory chip 302 through the via hole above the bottom memory chip 302. In this way, the controller chip 100 transmits the high-byte signal of the first sub-channel 111 to the bottom memory chip 302; wherein, the first preset area can be completed according to the actual structural configuration of the printed circuit board 200.

[0056] This is because the high-order byte signal of the first sub-channel 111 is transmitted through the second wiring inner layer 202, and the low-order byte signal of the second sub-channel 112 is transmitted through the first wiring inner layer 201. Therefore, the low-order byte signal line of the second sub-channel 112 must pass through the area where the via of the high-order byte signal line of the first sub-channel 111 is located; Figure 1H As shown, if a via is directly set below the high-byte pin of the first sub-channel 111, the low-byte signal line of the second sub-channel 112 can only pass through the gap between the vias below the high-byte pin of the first sub-channel 111, that is, the via of the high-byte signal line of the first sub-channel 111 is closer to the low-byte signal line of the second sub-channel 112, causing greater crosstalk to the transmission of the low-byte signal of the second sub-channel 112.

[0057] Therefore, as described in the above technical solution, vias are not directly set below the high-order byte pins of the first sub-channel 111, but vias are set in a first preset area far away from the low-order byte pins of the second sub-channel 112. The high-order byte signal line of the first sub-channel 111 extends for a distance on the surface layer and then enters the second wiring inner layer 202 through the vias in the first preset area. Obviously, since the vias in the first preset area are far away from the vias below the low-order byte pins of the second sub-channel 112, the low-order byte signal of the second sub-channel 112 has enough wiring space in the first wiring inner layer 201, which can ensure that the low-order byte signal line of the second sub-channel 112 is away from the vias corresponding to the high-order byte signal line of the first sub-channel 111, thereby avoiding the crosstalk problem caused by the signal line and the via being too close.

[0058] According to the technical solution of the embodiment of the present invention, the high-byte signal line of the first sub-channel in the controller chip extends from the high-byte pin of the first sub-channel to the first preset area along the first direction on the surface of the printed circuit board, enters the second wiring inner layer through a via in the first preset area, and then connects to the bottom storage chip after passing through the second wiring inner layer, so that the problem of large crosstalk caused by long-distance surface wiring is avoided without increasing the number of layers of the printed circuit board and the complexity of the process for manufacturing the printed circuit board, the signal transmission impedance and external interference are reduced, the stability of the data transmission system is improved, and the crosstalk problem caused by the close distance between the signal line and the via is avoided.

[0059] Embodiment 2

[0060] Embodiment 2 of the present invention provides a data transmission system. In the embodiment of the present invention, the boundary length of the first preset area in the first vertical direction is smaller than the boundary length of the area where the high-order byte pin of the first sub-channel is located in the first vertical direction; wherein, the first vertical direction is the vertical direction of the line connecting the center point of the high-order byte pin of the first sub-channel and the center point of the underlying storage chip.

[0061] Specifically, a line between the center point of the area where the high-order byte pins of the first sub-channel are located and the center point of the memory chip is defined as a first horizontal direction, and a direction perpendicular to the first horizontal direction is defined as a first vertical direction; Figure 2AAs shown, the area where the high-order byte pin of the first sub-channel is located is usually a rectangular area, and its boundary length in the first vertical direction is relatively long; obviously, the boundary length of the rectangular area in the first vertical direction has a larger shielding range for the low-order byte signal line led out of the low-order byte pin of the second sub-channel, thereby reducing the wiring space of the inner layer of the first wiring; and after the high-order byte signal line of the first sub-channel is extended to the first preset area, since the boundary length of the first preset area in the first vertical direction is smaller than the boundary length of the area where the high-order byte pin of the first sub-channel is located, the shielding range of the low-order byte signal line led out of the low-order byte pin of the second sub-channel is reduced, the wiring space of the inner layer of the first wiring is expanded, and the distance between the low-order byte signal line of the second sub-channel and the via corresponding to the high-order byte pin of the first sub-channel is further increased, thereby avoiding the crosstalk problem caused by the signal line and the via being too close.

[0062] Optionally, in an embodiment of the present invention, the first preset area includes at least one rectangular via area, the rectangular via area includes at least one signal hole group, the signal hole group includes two signal holes arranged diagonally and two ground holes arranged diagonally; each of the signal hole groups is separated by at least one ground hole group, and the ground hole group includes two vertically arranged ground holes.

[0063] Specifically, Figure 2B As shown, a signal hole group includes four vias, namely, two signal holes arranged diagonally and two ground holes arranged diagonally; each signal hole group is separated by a ground hole group, and each ground hole group includes two vertically arranged ground holes; the rectangular via area in the above technical solution allows the two rows of vias to be regularly arranged in the current area without redundant boundaries, and at the same time, the arrangement of the signal hole group and the ground hole group allows each signal hole to be surrounded by at least two ground holes, and most of the signal holes are surrounded by three or more ground holes, and there is only one signal hole close to each signal hole, thereby greatly reducing the crosstalk between the signal holes while occupying a smaller surface space.

[0064] In particular, when there are many high-byte signal lines of the first sub-channel and the surface space is insufficient to provide a complete area to simultaneously meet the via requirements of all high-byte signal lines of the first sub-channel, the first preset area can be divided into multiple unconnected rectangular via areas, which not only makes full use of the scattered space on the surface, but also the in-board space corresponding to the unconnected areas between the rectangular via areas, also provides wiring space for the high-byte signal lines of the first sub-channel, further reducing the crosstalk between the signal holes.

[0065] For vias in other locations of the printed circuit board, namely, vias below the low-byte pins of the first sub-channel of the controller chip, vias below the low-byte pins of the second sub-channel, vias below the high-byte pins of the second sub-channel, vias below the surface memory chip, and vias above the bottom memory chip, you can follow Figure 2C The cross-shaped arrangement shown is arranged, that is, each signal hole is arranged in a diagonal manner, and the upper, lower, left and right positions adjacent to each signal hole are ground holes, thereby minimizing the crosstalk between the two signal holes.

[0066] Optionally, in an embodiment of the present invention, the low-byte signal line of the second sub-channel extends from the low-byte pin of the second sub-channel to a second preset area along the second direction on the surface layer, and enters the first wiring inner layer through a via in the second preset area; wherein the second direction is the direction away from the high-byte pin of the first sub-channel.

[0067] Specifically, when the via below the high-byte pin of the first sub-channel is close to the low-byte signal line of the second sub-channel, it will cause greater crosstalk to the transmission of the low-byte signal of the second sub-channel. Therefore, the low-byte signal line of the second sub-channel can be led out from the low-byte pin of the second sub-channel of the controller chip, and then extended in the surface layer along the direction away from the high-byte pin of the first sub-channel until it extends to the second preset area, and then passes through the via in the second preset area to enter the first wiring inner layer, and after passing through the first wiring inner layer, it is connected to the surface storage chip through the via below the surface storage chip. In particular, the arrangement of the signal hole and the ground hole in the second preset area can adopt the same arrangement as that of the first preset area.

[0068] The above technical solution also ensures that the low-order byte signal of the second sub-channel has sufficient wiring space in the first wiring layer, ensuring that the low-order byte signal line of the second sub-channel is away from the via corresponding to the high-order byte signal line of the first sub-channel, thereby avoiding the crosstalk problem caused by the signal line and the via being too close; in particular, due to the limitations of the surface layout of the printed circuit board, when the surface space does not have the first preset area, the low-order byte signal line of the second sub-channel can be kept away from the via corresponding to the high-order byte signal line of the first sub-channel by setting the reverse second preset area, thereby increasing the adaptability of the printed circuit board.

[0069] According to the technical solution of the embodiment of the present invention, since the boundary length of the first preset area in the first vertical direction is smaller than the boundary length of the area where the high-byte pin of the first sub-channel is located, the shielding range of the low-byte signal line led out of the low-byte pin of the second sub-channel is reduced, the wiring space of the inner layer of the first wiring is expanded, and the distance between the low-byte signal line of the second sub-channel and the via corresponding to the high-byte pin of the first sub-channel is further increased, thereby avoiding the crosstalk problem caused by the signal line and the via being too close. At the same time, the setting of the rectangular via area allows two rows of vias to be regularly arranged in the current area without redundant boundaries. At the same time, the setting of the signal hole group and the spaced ground hole group allows each signal hole to be provided with at least two ground holes around it and there is only one signal hole, thereby greatly reducing the crosstalk between the signal holes while occupying a smaller surface space.

[0070] Embodiment 3

[0071] Figure 3 This is a flow chart of a data transmission method provided in Embodiment 3 of the present invention. This embodiment is applicable to a controller chip sending transmission data to a storage chipset. The method can be executed by the data transmission system in Embodiment 1 or Embodiment 2. The method includes:

[0072] S301, the controller chip transmits the high-byte signal of the first sub-channel to the underlying storage chip through the high-byte signal line of the first sub-channel, and transmits the high-byte signal of the second sub-channel to the underlying storage chip through the high-byte signal line of the second sub-channel; wherein the high-byte signal line of the first sub-channel extends from the high-byte pin of the first sub-channel to a first preset area along a first direction on the surface layer, and enters the second wiring inner layer through a via in the first preset area.

[0073] S302. The controller chip transmits the low-byte signal of the first sub-channel to the surface storage chip through the low-byte signal line of the first sub-channel, and transmits the low-byte signal of the second sub-channel to the surface storage chip through the low-byte signal line of the second sub-channel.

[0074] According to the technical solution of the embodiment of the present invention, the high-byte signal line of the first sub-channel in the controller chip extends from the high-byte pin of the first sub-channel to the first preset area along the first direction on the surface of the printed circuit board, enters the second wiring inner layer through a via in the first preset area, and then connects to the bottom storage chip after passing through the second wiring inner layer. This avoids the problem of large crosstalk caused by long-distance surface wiring without increasing the number of layers of the printed circuit board and the process complexity of manufacturing the printed circuit board, reduces signal transmission impedance and external interference, and improves the stability of the data transmission system. In addition, it avoids the crosstalk problem caused by the close distance between the signal line and the via.

[0075] Embodiment 4

[0076] Figure 4 : is a structural diagram of a data transmission device provided by Embodiment 4 of the present invention, the device specifically comprises:

[0077] A high-byte signal transmission module 401 is configured in the controller chip, and is used to transmit the high-byte signal of the first sub-channel to the bottom storage chip through the high-byte signal line of the first sub-channel, and to transmit the high-byte signal of the second sub-channel to the bottom storage chip through the high-byte signal line of the second sub-channel;

[0078] Wherein, the high-byte signal line of the first sub-channel extends from the high-byte pin of the first sub-channel to the first preset area along the first direction on the surface layer, and enters the second wiring inner layer through a via in the first preset area;

[0079] The low-byte signal transmission module 402 is configured in the controller chip, and is used to transmit the low-byte signal of the first sub-channel to the surface storage chip through the low-byte signal line of the first sub-channel, and to transmit the low-byte signal of the second sub-channel to the surface storage chip through the low-byte signal line of the second sub-channel.

[0080] According to the technical solution of the embodiment of the present invention, the high-byte signal line of the first sub-channel in the controller chip extends from the high-byte pin of the first sub-channel to the first preset area along the first direction on the surface of the printed circuit board, enters the second wiring inner layer through a via in the first preset area, and then connects to the bottom storage chip after passing through the second wiring inner layer. This avoids the problem of large crosstalk caused by long-distance surface wiring without increasing the number of layers of the printed circuit board and the process complexity of manufacturing the printed circuit board, reduces signal transmission impedance and external interference, and improves the stability of the data transmission system. In addition, it avoids the crosstalk problem caused by the close distance between the signal line and the via.

[0081] The above device can execute the data transmission method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method. For technical details not described in detail in this embodiment, please refer to the data transmission method provided by any embodiment of the present invention.

[0082] Embodiment 5

[0083] In some embodiments, the data transmission method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit. In some embodiments, part or all of the computer program may be loaded and / or installed on a heterogeneous hardware accelerator via a ROM and / or a communication unit. When the computer program is loaded into RAM and executed by a processor, one or more steps of the data transmission method described above may be performed. Alternatively, in other embodiments, the processor may be configured to perform the data transmission method in any other appropriate manner (e.g., by means of firmware).

[0084] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0085] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0086] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0087] To provide interaction with a user, the systems and techniques described herein may be implemented on a heterogeneous hardware accelerator having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) through which a user can provide input to the heterogeneous hardware accelerator. Other types of devices may also be used to provide interaction with a user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0088] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0089] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0090] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0091] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A data transmission system, characterized in that: include: A controller chip, a printed circuit board and at least one memory chipset; the controller chip is located on the surface of the printed circuit board, and the memory chipset includes a surface memory chip and a bottom memory chip; The printed circuit board comprises a first wiring inner layer and a second wiring inner layer, the first wiring inner layer is connected to the surface layer memory chip, the second wiring inner layer is connected to the bottom layer memory chip, and the distance between the first wiring inner layer and the surface layer is smaller than the distance between the second wiring inner layer and the surface layer; The controller chip includes at least one channel, the channel includes a first sub-channel and a second sub-channel, and the first sub-channel and the second sub-channel both include a low-byte pin and a high-byte pin; The high-byte signal line of the first sub-channel extends from the high-byte pin of the first sub-channel to the first preset area along the first direction on the surface layer, and enters the second wiring inner layer through a via in the first preset area; wherein the first direction is a direction away from the low-byte pin of the second sub-channel; The low-byte signal line of the second sub-channel extends from the low-byte pin of the second sub-channel to the second preset area along the second direction on the surface layer, and enters the first wiring inner layer through a via in the second preset area; wherein the second direction is the direction away from the high-byte pin of the first sub-channel.

2. The data transmission system according to claim 1, characterized in that: The low-byte signal line of the first sub-channel enters the first wiring inner layer through a blind hole or a back-drilled through hole below the low-byte pin of the first sub-channel; And / or the low-byte signal line of the second sub-channel enters the first wiring inner layer through a blind hole or a back-drilled through hole below the low-byte pin of the second sub-channel.

3. The data transmission system according to claim 1, characterized in that: The first wiring inner layer is connected to the surface storage chip through a blind via; And / or the second wiring inner layer is connected to the bottom memory chip through a blind via.

4. The data transmission system according to claim 1, characterized in that: The high-byte signal line of the second sub-channel enters the second wiring inner layer through a through hole or a back-drilled through hole below the high-byte pin of the second sub-channel; And / or the high-byte signal line of the first sub-channel enters the second wiring inner layer through a through hole or a back-drilled through hole in the first preset area.

5. The data transmission system according to claim 1, characterized in that: The boundary length of the first preset area in the first vertical direction is smaller than the boundary length of the area where the high-byte pin of the first sub-channel is located in the first vertical direction; wherein, the first vertical direction is the vertical direction of the line connecting the center point of the high-byte pin of the first sub-channel and the center point of the underlying storage chip.

6. The data transmission system according to claim 1, characterized in that: The first preset area includes at least one rectangular via area, the rectangular via area includes at least one signal hole group, the signal hole group includes two signal holes arranged diagonally and two ground holes arranged diagonally; each of the signal hole groups is separated by at least one ground hole group, and the ground hole group includes two vertically arranged ground holes.

7. A data transmission method, characterized in that: A data transmission system as claimed in any one of claims 1 to 6, comprising: The controller chip transmits the high-byte signal of the first sub-channel to the bottom storage chip through the high-byte signal line of the first sub-channel, and transmits the high-byte signal of the second sub-channel to the bottom storage chip through the high-byte signal line of the second sub-channel; Wherein, the high-byte signal line of the first sub-channel extends from the high-byte pin of the first sub-channel to the first preset area along the first direction on the surface layer, and enters the second wiring inner layer through a via in the first preset area; The controller chip transmits the low-byte signal of the first sub-channel to the surface storage chip through the low-byte signal line of the first sub-channel, and transmits the low-byte signal of the second sub-channel to the surface storage chip through the low-byte signal line of the second sub-channel.

8. A data transmission device, characterized in that: A data transmission system as claimed in any one of claims 1 to 6, comprising: a high-byte signal transmission module, configured in the controller chip, for transmitting the high-byte signal of the first sub-channel to the bottom storage chip through the high-byte signal line of the first sub-channel, and transmitting the high-byte signal of the second sub-channel to the bottom storage chip through the high-byte signal line of the second sub-channel; Wherein, the high-byte signal line of the first sub-channel extends from the high-byte pin of the first sub-channel to the first preset area along the first direction on the surface layer, and enters the second wiring inner layer through a via in the first preset area; A low-byte signal transmission module is configured in the controller chip, and is used to transmit the low-byte signal of the first sub-channel to the surface storage chip through the low-byte signal line of the first sub-channel, and to transmit the low-byte signal of the second sub-channel to the surface storage chip through the low-byte signal line of the second sub-channel.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the data transmission method according to claim 7 when executed.

Images