Array substrate and preparation method thereof, and display device

Abstract

The present application discloses an array substrate and a preparation method thereof, and a display device, wherein the array substrate comprises: a substrate; an active layer, which is arranged on one side of the substrate; a gate insulating layer, which is arranged on the substrate and covers the active layer; and a gate layer, which is arranged on the side of the gate insulating layer away from the substrate, and is arranged outside the active layer in a wrapped shape, and is located on the side of the active layer away from the substrate and on two side surfaces of the side perpendicular to the long extension direction of the active layer. The technical effect of the present application is to increase the gate control area, enhance the gate control capability, weaken the segment channel effect, reduce the parasitic capacitance, and increase the on-state current.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to an array substrate and a preparation method thereof, and a display device. Background Art

[0002] Current display devices require array substrates to have high pixel density (High PPI), high aperture ratio, narrow borders, etc., and also need to meet high frequency and low power consumption display requirements. Therefore, the size of thin film transistor devices (TFTs) on array substrates is further reduced to reduce the space occupied by thin film transistors, thereby reducing the power consumption and resistance capacitance delay (RC Delay) of thin film transistors.

[0003] However, as the size of thin-film transistor devices decreases, a drain-induced barrier lowering (DIBL) effect will occur, which will have a significant adverse effect on the device, such as increased leakage current, severe negative drift of threshold voltage, reduced device stability, etc., thereby reducing product performance and yield. In addition, as the size of thin-film transistors decreases, the proportion of parasitic resistance generated by the lightly doped drain (LDD) structure will increase, and the current switching ratio will decrease, which will affect the performance of the array substrate, so it is urgent to improve this. Summary of the invention

[0004] The purpose of the present application is to provide an array substrate and a preparation method thereof, and a display device, which can solve the technical problems of the existing array substrate such as the drain-induced barrier lowering effect caused by the reduction in the size of thin film transistors, the increase in the proportion of parasitic resistance, and the reduction in current switching ratio.

[0005] To achieve the above-mentioned purpose, the present application provides an array substrate, comprising: a substrate; an active layer, arranged on one side of the substrate; a gate insulating layer, arranged on the substrate and covering the active layer; and a gate layer, arranged on a side of the gate insulating layer away from the substrate, and arranged in a wrapped shape on the outside of the active layer, located on the side of the active layer away from the substrate and on two side surfaces of the side perpendicular to the long strip extension direction of the active layer.

[0006] Furthermore, a side of the active layer away from the substrate is defined as a first side, and two side surfaces perpendicular to the long strip extension direction of the active layer are defined as second side surfaces; the gate layer includes: a first gate portion, located outside the first side surface of the active layer; and a second gate portion, arranged outside the second side surface of the active layer.

[0007] Furthermore, the first gate portion and the second gate portion are arranged perpendicular to each other, and the first gate portion is connected to the second gate portion.

[0008] Furthermore, the active layer includes: a polysilicon region, located in the central area of ​​the active layer; a lightly doped drain region, two of the lightly doped drain regions are respectively arranged on both sides of the polysilicon region; and a conductor region, two of the conductor regions are respectively arranged on the side of the two lightly doped drain regions away from the polysilicon region.

[0009] Furthermore, the first gate portion covers the polysilicon region of the active layer, and a length extension direction of the first gate portion is perpendicular to a length extension direction of the active layer.

[0010] Furthermore, the second gate portion covers the polysilicon region and a portion of the lightly doped drain region of the active layer; and in the length extension direction of the active layer, the width of the second gate portion is greater than the width of the first gate portion.

[0011] Furthermore, the base includes: a glass substrate; a light-shielding layer, which is arranged on one side of the glass substrate and is arranged opposite to the active layer; and a buffer layer, which is arranged on one side of the glass substrate and covers the light-shielding layer; wherein the buffer layer has a flat portion and a raised portion, and the raised portion protrudes from the flat portion; and the active layer is arranged on the raised portion.

[0012] Furthermore, the gate layer further includes a third gate portion, which is arranged opposite to the flattened portion of the buffer layer; and the orthographic projection of the gate layer on the substrate is a continuous pattern.

[0013] To achieve the above-mentioned purpose, the present application also provides a method for preparing an array substrate, which is used to prepare the array substrate as described above; the preparation method comprises the following steps: providing a substrate; preparing an active layer on the substrate; preparing a gate insulating layer on the active layer and the substrate; and preparing a gate layer on the gate insulating layer, wherein the gate layer is located above the active layer and on two side surfaces on a side perpendicular to the extension direction of the long strips of the active layer.

[0014] To achieve the above objectives, the present application also provides a display device, comprising the array substrate as described above.

[0015] The technical effect of the present application is that the original planar gate is changed into a three-dimensional gate structure, and a gate layer is arranged above the active layer and on both sides. At the same time, the width of the gate layer at the side is greater than the width of the gate layer at the top, thereby increasing the control area of ​​the gate layer and enhancing the control capability of the gate layer. At the same time, the gate layer at the side will cover part of the lightly doped drain region to form a self-aligned gate and lightly doped drain region overlapping structure, which can reduce the parasitic resistance caused by the lightly doped drain region and increase the on-state current. No additional mask plate process is added in the whole process, which is conducive to the preparation of a high-resolution array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 is a three-dimensional diagram of a portion of an array substrate provided in an embodiment of the present application;

[0018] Figure 2 is a schematic diagram of a gate layer and an active layer provided in an embodiment of the present application;

[0019] Figure 3 The embodiment of this application provides Figure 2 A cross-sectional view of the array substrate in the AA direction;

[0020] Figure 4 The embodiment of this application provides Figure 2 A cross-sectional view of the array substrate in the BB direction;

[0021] Figure 5 is a flow chart of a method for preparing an array substrate provided in an embodiment of the present application;

[0022] Figure 6 is a schematic diagram of the structure after preparing the light shielding layer provided in an embodiment of the present application;

[0023] Figure 7 is a schematic diagram of preparing an active layer provided in an embodiment of the present application;

[0024] Figure 8 is a schematic diagram of the structure after the active layer is prepared according to an embodiment of the present application;

[0025] Fig. 9 is a schematic diagram of the structure after preparing the gate layer provided in an embodiment of the present application;

[0026] Fig.10 is a schematic diagram of the structure after preparing the dielectric layer provided in an embodiment of the present application;

[0027] Fig.11 is a schematic diagram of the structure after the source and drain layers are prepared according to an embodiment of the present application;

[0028] Fig.12 is a schematic diagram of the structure after preparing the flat layer provided in an embodiment of the present application;

[0029] Fig.13 is a schematic diagram of the structure after the touch signal electrode layer is prepared according to an embodiment of the present application;

[0030] Fig.14 It is a schematic diagram of the structure after preparing the passivation layer provided in an embodiment of the present application.

[0031] Description of reference numerals:

[0032] 100, substrate; 200, active layer; 300, gate insulating layer; 400, gate layer; 500, dielectric layer; 600, source and drain electrode layer; 700, planar layer; 800, touch signal electrode; 900, passivation layer; 1000, pixel electrode;

[0033] 101, glass substrate; 102, light shielding layer; 103, buffer layer;

[0034] 1031, flat portion; 1032, raised portion;

[0035] 201, polysilicon region; 202, lightly doped drain region; 203, conductor region;

[0036] 210, first side surface; 220, second side surface;

[0037] 401, a first gate portion; 402, a second gate portion; 403, a third gate portion. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words such as "upper" and "lower" used generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0039] like Figures 1 to 14As shown, the embodiments of the present application provide an array substrate and a method for manufacturing the same, and a display device. The following are detailed descriptions of each. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0040] like Figures 1 to 4 As shown, the array substrate provided in this embodiment includes: a substrate 100, an active layer 200, a gate insulating layer 300, a gate layer 400, a dielectric layer 500, a source-drain electrode layer 600, a planar layer 700, a touch signal electrode 800, a passivation layer 900 and a pixel electrode 1000. In the array substrate provided in this embodiment, the gate layer 400 is a three-dimensional gate structure, which is arranged outside the active layer 200 in a wrapped shape, and is located on a side of the active layer 200 away from the substrate 100 and on two side surfaces of a side perpendicular to the long strip extension direction of the active layer 200. The specific structure of the array substrate will be described in detail below.

[0041] The base 100 is a substrate structure, which includes a glass substrate 101 , a light shielding layer 102 and a buffer layer 103 .

[0042] The light shielding layer 102 is disposed on one side of the glass substrate 101 , that is, disposed on the upper surface of the glass substrate 101 .

[0043] The buffer layer 103 is disposed on one side of the glass substrate 101 and covers the light shielding layer 102. In this embodiment, the buffer layer 103 is disposed on the upper surface of the glass substrate 101. The buffer layer 103 has a flat portion 1031 and a raised portion 1032. The raised portion 1032 is protruding from the flat portion 1031 (see Figure 3 , Figure 4 ), the protrusion 1032 is arranged opposite to the light shielding layer 102 and is used to support the active layer 200.

[0044] The active layer 200 is disposed on the protruding portion 1032 of the buffer layer 103, and a side of the active layer 200 away from the substrate 100 is defined as a first side 210, and a long strip extending direction (i.e., Figure 1 The two side surfaces perpendicular to the length direction of the active layer 200 in the three-dimensional view are the second side surfaces 220 (see Figure 4 ).

[0045] The active layer 200 includes a polysilicon region 201 , a lightly doped drain region 202 and a conductor region 203 . The polysilicon region 201 is located in the central region of the active layer 200 , is made of polysilicon semiconductor material, and is the channel region of the active layer 200 .

[0046] The two lightly doped drain regions (LDD) 202 are respectively arranged on both sides of the polysilicon region 201. The lightly doped drain region 202 is a low-doped drain region near the drain in the channel region, so it is arranged outside the polysilicon region 201. The lightly doped drain region 202 also bears part of the voltage, and the active layer structure with the lightly doped drain region 202 can prevent the occurrence of hot electron degradation effect.

[0047] The two conductor regions 203 are respectively arranged on the side of the two lightly doped drain regions 202 away from the polysilicon region 201, that is, the conductor region 203 is arranged on the outside of the lightly doped drain region 202. The conductor region 203 is a structure after the semiconductor material is conductorized and has good conductive properties. The conductor region 203 is used to electrically connect to the source and drain layer 600 to transmit driving signals thereto.

[0048] The gate insulating layer 300 is disposed on one side of the substrate 100 and covers the active layer 200 . In this embodiment, the gate insulating layer 300 is disposed on the upper surface of the buffer layer 103 of the substrate 100 and covers the active layer 200 .

[0049] The gate layer 400 is disposed on a side of the gate insulating layer 300 away from the substrate 100. In this embodiment, the gate layer 400 is disposed on the gate insulating layer 300. The extension direction of the gate layer 400 (i.e., the BB direction) is perpendicular to the extension direction of the active layer 200 (i.e., the AA direction) (see FIG. 1 ). Figure 2 ), the gate layer 400 is a three-dimensional gate structure, and its structure is similar to the letter “I” shape. Specifically, the gate layer 400 includes a first gate portion 401, a second gate portion 402 and a third gate portion 403.

[0050] The first gate portion 401 is located outside the first side surface 210 of the active layer 200, that is, the first gate portion 401 is a gate portion located on one side above the active layer 200, and the length extension direction of the first gate portion 401 is perpendicular to the length extension direction of the active layer 200 (see Figure 1 ), the first gate portion 401 completely covers the polysilicon region 201 in the active layer 200 thereunder, such as Figure 2 As shown, the polysilicon region 201 is completely covered and is not marked in the figure.

[0051] The second gate portion 402 is disposed outside the second side surface 220 of the active layer 200, and the second gate portion 402 and the first gate portion 401 are disposed perpendicular to each other (see Figure 1 , Figure 4), the first gate portion 401 is connected to the second gate portion 402.

[0052] like Figure 1 As shown, in the length extension direction of the active layer 200, the width of the second gate portion 402 is greater than the width of the first gate portion 401, which can increase the control area of ​​the gate layer 400, enhance the control ability of the gate layer 400, and effectively improve the short channel effect caused by the reduction in size of the active layer 200 on the array substrate.

[0053] The second gate portion 402 will cover the polysilicon region 201 and part of the lightly doped drain region 202 of the active layer 200. At this time, a self-aligned gate and lightly doped drain region overlapping structure (gate overlap LDD, GOLDD) will be formed on the side, which can effectively improve the short channel effect caused by the reduction in the size of the active layer 200 on the array substrate, reduce the parasitic resistance caused by the lightly doped drain region, and increase the on-state current.

[0054] In a direction perpendicular to the first gate portion 401 , the width of the second gate portion 402 is greater than the width of the active layer 200 . This is because the second gate portion 402 extends to the upper surface of the gate insulating layer 300 , and because of the presence of the protruding portion 1032 , in the vertical direction, the thickness of the second gate portion 402 is greater than the thickness of the active layer 200 .

[0055] The third gate portion 403 is arranged opposite to the flat portion 1031 of the buffer layer 103, that is, the third gate portion 403 is laid flat on the gate insulating layer 300 above the flat portion 1031. Figure 2 When viewed from the BB direction, the orthographic projection of the gate layer 400 on the substrate 100 is a continuous pattern, which can ensure the control area of ​​the gate layer 400.

[0056] The dielectric layer 500 is disposed on the upper surface of the gate insulating layer 300 and covers the gate layer 400. The dielectric layer 500 and the gate insulating layer 300 are both made of insulating materials with good insulation properties, thereby preventing the gate layer 400 from forming an electrical connection with other conductive layers and thus affecting the use of the array substrate.

[0057] The source-drain electrode layer 600 is disposed on the upper surface of the dielectric layer 500 , and passes through the dielectric layer 500 and the gate insulating layer 300 , and is electrically connected to the conductor region 203 of the active layer 200 . The conductor region 203 provides electrical signals for the source-drain electrode layer 600 .

[0058] The planar layer 700 is disposed on the upper surface of the dielectric layer 500 and covers the source-drain electrode layer 600 . The planar layer 700 is an inorganic film layer, which ensures that the surface of the array substrate is flat and facilitates uniform preparation of subsequent film layers.

[0059] The touch signal electrode 800 is disposed on the upper surface of the flat layer 700 and is a bottom transparent indium tin oxide electrode (BITO) for receiving a touch signal. This part of the structure is not described in detail in this embodiment.

[0060] The passivation layer 900 is disposed on the upper surface of the planar layer 700 and covers the touch signal electrode 800 . The passivation layer 900 is an inorganic film layer with good insulation effect. A through hole is opened at a position relative to the source and drain electrode layer 600 (generally at the drain electrode) to facilitate the electrical connection between the pixel electrode 1000 and the source and drain electrode layer 600 .

[0061] The pixel electrode 1000 is disposed on the upper surface of the passivation layer 900 and is electrically connected to the source-drain electrode layer 600 through a through hole on the passivation layer 900 . The pixel electrode 1000 is a top transparent indium tin oxide electrode (TITO).

[0062] In the present embodiment, a display device including the above array substrate is also provided, and the display device also includes a packaging layer, a light emitting structure, a cover plate, a back plate and other structures, which are not described one by one in the present embodiment, but it should be clear that these structures are all within the protection scope of the present embodiment. The display device is generally an electronic device such as a laptop computer, a display screen, a mobile phone, a tablet computer, etc. The size of the array substrate is gradually reduced, but the active layer with a lightly doped drain region at the same time will cause parasitic capacitance, and the parasitic capacitance can be reduced after the lightly doped drain region in the present embodiment is overlapped and covered by the gate layer on the side, so the display device can have the characteristics of high aperture ratio, high pixel density, narrow frame, etc., and meet the display requirements of high frequency and low power consumption at the same time.

[0063] The technical effect of the array substrate and the display device described in this embodiment is that the original planar gate is changed into a three-dimensional gate structure, and the gate layer is arranged above the active layer and on both sides. At the same time, the width of the gate layer at the side is greater than the width of the gate layer at the top, thereby increasing the control area of ​​the gate layer and enhancing the control capability of the gate layer. At the same time, the gate layer at the side will cover part of the lightly doped drain region to form a self-aligned gate and lightly doped drain region overlapping structure, which can reduce the parasitic resistance caused by the lightly doped drain region and increase the on-state current.

[0064] like Figures 5 to 14 As shown, this embodiment further provides a method for preparing an array substrate, which is used to prepare the array substrate as described above, and includes steps S1 to S10.

[0065] S1 provides a substrate 100. The preparation steps of the substrate 100 include preparing a light shielding layer 102 on the upper surface of a glass substrate 101 and patterning it (see Figure 6 ), a buffer layer 103 is prepared on the light shielding layer 102 and the glass substrate 101, and the buffer layer 103 is patterned to form a flat portion 1031 and a convex portion 1032, wherein the convex portion 1032 protrudes from the flat portion 1031 (see Figure 7 ), the protrusion 1032 is arranged opposite to the light shielding layer 102 and is used to support the active layer 200.

[0066] S2: prepare an active layer 200 on the substrate 100 (see Figure 7 , Figure 8 ), a layer of semiconductor material is deposited on the upper surface of the buffer layer 103, and a channel process is performed on the buffer layer 103 to form a polysilicon region 201, a lightly doped drain region 202 and a conductor region 203. The polysilicon region 201 is located in the central region of the active layer 200 and is made of polysilicon semiconductor material, which is the channel region of the active layer 200. The two lightly doped drain regions 202 are respectively arranged on both sides of the polysilicon region 201. The lightly doped drain region 202 is a low-doped drain region near the drain in the channel region, so it is arranged outside the polysilicon region 201. The lightly doped drain region 202 also bears part of the voltage, and the active layer structure with the lightly doped drain region 202 can prevent the occurrence of hot electron degradation effect. The two conductor regions 203 are respectively arranged on one side of the two lightly doped drain regions 202 away from the polysilicon region 201, that is, the conductor region 203 is arranged outside the lightly doped drain region 202. The conductor region 203 is a structure after semiconductor material is conductorized and has good conductive properties.

[0067] S3 prepares a gate insulating layer 300 on the active layer 200 and the substrate 100 by depositing a layer of inorganic insulating material such as silicon nitride or silicon oxynitride. Due to the presence of the protrusion 1032 on the buffer layer 103, the thickness of the gate insulating layer 300 is not completely the same.

[0068] S4: a gate layer 400 is formed on the gate insulating layer 300 (see Fig. 9), wherein the gate layer 400 is located above the active layer 200 and at two side surfaces perpendicular to the long strip extension direction of the active layer 200. Specifically, a layer of metal material is sputtered, sprayed or deposited on the upper surface of the gate insulating layer 300. It should be noted that a layer of metal material is also prepared on the gate insulating layer 300 outside the protruding portion 1032 of the buffer layer 103 to form the gate layer 400. The gate layer 400 is a three-dimensional gate structure. Specifically, the gate layer 400 includes a first gate portion 401, a second gate portion 402 and a third gate portion 403.

[0069] The first gate portion 401 is located outside the first side surface 210 of the active layer 200, that is, the first gate portion 401 is a gate portion located on one side above the active layer 200, and the length extension direction of the first gate portion 401 is perpendicular to the length extension direction of the active layer 200 (see Figure 1 ), the first gate portion 401 completely covers the polysilicon region 201 in the active layer 200 thereunder, such as Figure 2 As shown, the polysilicon region 201 is completely covered and is not marked in the figure.

[0070] The second gate portion 402 is disposed outside the second side surface 220 of the active layer 200, and the second gate portion 402 and the first gate portion 401 are disposed perpendicular to each other (see Figure 1 , Figure 4 ), the first gate portion 401 is connected to the second gate portion 402.

[0071] like Figure 1 As shown, in the length extension direction of the active layer 200, the width of the second gate portion 402 is greater than the width of the first gate portion 401, which can increase the control area of ​​the gate layer 400, enhance the control ability of the gate layer 400, and effectively improve the short channel effect caused by the reduction in size of the active layer 200 on the array substrate.

[0072] The second gate portion 402 will cover the polysilicon region 201 and a portion of the lightly doped drain region 202 of the active layer 200. At this time, a self-aligned gate and lightly doped drain region overlapping structure will be formed on the side, which can effectively improve the short channel effect caused by the reduction in the size of the active layer 200 on the array substrate, reduce the parasitic resistance caused by the lightly doped drain region, and increase the on-state current.

[0073] In a direction perpendicular to the first gate portion 401 , the width of the second gate portion 402 is greater than the width of the active layer 200 . This is because the second gate portion 402 extends to the upper surface of the gate insulating layer 300 , and because of the presence of the protruding portion 1032 , in the vertical direction, the thickness of the second gate portion 402 is greater than the thickness of the active layer 200 .

[0074] The third gate portion 403 is arranged opposite to the flat portion 1031 of the buffer layer 103, that is, the third gate portion 403 is laid flat on the gate insulating layer 300 above the flat portion 1031. Figure 2 When viewed from the BB direction, the orthographic projection of the gate layer 400 on the substrate 100 is a continuous pattern, which can ensure the control area of ​​the gate layer 400.

[0075] S5: prepare a dielectric layer 500 on the gate layer 400 (see Fig.10 ), a layer of inorganic insulating material is deposited on the upper surface of the gate layer 400 and the gate insulating layer 300 as a dielectric layer 500 to play an insulating role. A through hole is opened on the dielectric layer 500, and the through hole is used as a connection channel between the subsequent source and drain layer 600 and the conductor area 203 of the active layer 200.

[0076] S6: Prepare a source-drain electrode layer 600 on the dielectric layer 500 (see Fig.11 ), sputtering or spraying a metal material on the dielectric layer 500, the metal material may be a metal stacked structure, and patterning is performed to form a source-drain electrode layer 600, the source-drain electrode layer 600 passes through the dielectric layer 500 and the gate insulating layer 300, and is electrically connected to the conductor region 203 of the active layer 200, the conductor region 203 provides an electrical signal for the source-drain electrode layer 600.

[0077] S7: Prepare a planar layer 700 on the source / drain electrode layer 600 and the dielectric layer 500 (see Fig.12 ), specifically, a layer of inorganic material is deposited on the source-drain electrode layer 600 and the dielectric layer 500, and after curing treatment, the surface of the array substrate is ensured to be flat, so as to facilitate the uniform preparation of subsequent film layers.

[0078] S8: Prepare the touch signal electrode 800 on the flat layer 700 (see Fig.13 ), a transparent indium tin oxide material is sputtered or sprayed on the upper surface of the flat layer 700 as a bottom transparent indium tin oxide electrode (BITO), which is patterned to form a touch signal electrode 800 for receiving a touch signal.

[0079] S9: Prepare a passivation layer 900 on the touch signal electrode 800 and the flat layer 700 (see Fig.14 ), specifically, an inorganic material is deposited on the touch signal electrode 800 and the planar layer 700 , and a passivation layer 900 is formed after patterning, and a through hole is formed on the passivation layer 900 .

[0080] S10: Prepare a pixel electrode 1000 on the passivation layer 900 (see Figure 1 ), a transparent indium tin oxide material is sputtered or sprayed on the upper surface of the passivation layer 900 as a top transparent indium tin oxide electrode (TITO), and is electrically connected to the source and drain layer 600 through a through hole on the passivation layer 900 to form a pixel electrode 1000.

[0081] The technical effect of the method for preparing the array substrate described in this embodiment is that the original planar gate is changed into a three-dimensional gate structure, and a gate layer is arranged above the active layer and on both sides. At the same time, the width of the gate layer at the side is greater than the width of the gate layer at the top, thereby increasing the control area of ​​the gate layer and enhancing the control capability of the gate layer. At the same time, the gate layer at the side will cover part of the lightly doped drain region to form a self-aligned gate and lightly doped drain region overlapping structure, which can reduce the parasitic resistance caused by the lightly doped drain region and increase the on-state current. No additional mask plate process is added in the whole process, which is conducive to the preparation of a high-resolution array substrate.

[0082] The above is a detailed introduction to an array substrate and a preparation method thereof, and a display device provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: substrate; An active layer is disposed on one side of the substrate, a side of the active layer away from the substrate is defined as a first side, and two side surfaces perpendicular to the extending direction of the long strips of the active layer are defined as second side surfaces; A gate insulating layer, disposed on the substrate and covering the active layer; as well as A gate layer, disposed on a side of the gate insulating layer away from the substrate, and disposed outside the active layer in a wrapped shape, and located on two side surfaces of the active layer away from the substrate and perpendicular to the long strip extension direction of the active layer; The gate layer comprises: a first gate portion, located outside the first side surface of the active layer; as well as The second gate portion is arranged outside the second side surface of the active layer, and covers the polysilicon region and part of the lightly doped drain region of the active layer. In the length extension direction of the active layer, the width of the second gate portion is greater than the width of the first gate portion.

2. The array substrate according to claim 1, characterized in that: The first gate portion and the second gate portion are disposed perpendicular to each other, and the first gate portion is connected to the second gate portion.

3. The array substrate according to claim 1, characterized in that: The active layer comprises: A polysilicon region located in the central region of the active layer; A lightly doped drain region, wherein two lightly doped drain regions are respectively arranged on both sides of the polysilicon region; and Conductor region, wherein the two conductor regions are respectively arranged on one side of the two lightly doped drain regions away from the polysilicon region.

4. The array substrate according to claim 1, wherein: The first gate portion covers the polysilicon region of the active layer, and a length extension direction of the first gate portion is perpendicular to a length extension direction of the active layer.

5. The array substrate according to claim 1, characterized in that: The substrate comprises: Glass substrate; a light shielding layer, disposed on one side of the glass substrate, and the light shielding layer is disposed opposite to the active layer; and A buffer layer, disposed on one side of the glass substrate and covering the light shielding layer; The buffer layer has a flat portion and a convex portion, and the convex portion protrudes from the flat portion; the active layer is arranged on the convex portion.

6. The array substrate according to claim 5, characterized in that: The gate layer further includes a third gate portion, which is arranged opposite to the flattened portion of the buffer layer; The orthographic projection of the gate layer on the substrate is a continuous pattern.

7. A method for preparing an array substrate, characterized in that: Used to prepare the array substrate according to any one of claims 1 to 6; the preparation method comprises the following steps: providing a substrate; An active layer is prepared on the substrate, a side of the active layer away from the substrate is defined as a first side, and two side surfaces perpendicular to the extending direction of the long strips of the active layer are defined as second side surfaces; Preparing a gate insulating layer on the active layer and the substrate; and A gate layer is prepared on the gate insulating layer, wherein the gate layer is located above the active layer and at two side surfaces perpendicular to the long strip extension direction of the active layer, the gate layer includes a first gate portion and a second gate portion, the first gate portion is located outside the first side surface of the active layer; the second gate portion is arranged outside the second side surface of the active layer, the second gate portion covers the polysilicon region and a part of the lightly doped drain region of the active layer, and in the length extension direction of the active layer, the width of the second gate portion is greater than the width of the first gate portion.

8. A display device, characterized in that: Comprising the array substrate as described in any one of claims 1 to 6.

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