Semiconductor device and method for manufacturing the same

Abstract

The object of the present disclosure is to provide a semiconductor device that can achieve miniaturization of the device and ensure the reliability of the connection in the solder joint. In addition, in the semiconductor device (51) of the present disclosure, a plurality of insulating coated wires (7) respectively make the insulating coated portion (72) in the central area contact with the surface of the semiconductor element (1) and cross the semiconductor element (1) to connect one end and the other end to the connection area (3b) in the upper electrode (3) of the DBC substrate (8). The plurality of insulating coated wires (7) are arranged along the X direction in the same manner as the plurality of metal wires (6). The plurality of insulating coated wires (7) are respectively arranged in a state without slack, so they have a pressing force that presses the semiconductor element (1) in the direction of the solder joint (2).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having a structure in which a semiconductor element is connected to a substrate using solder and a method for manufacturing the same. Background Art

[0002] In recent years, the reliability requirements for semiconductor devices have become increasingly higher, and in particular, there has been a demand for improvement in the life reliability of a joint between a semiconductor element and a circuit board having a large difference in thermal expansion coefficient.

[0003] Conventionally, semiconductor elements made of silicon (Si) and gallium arsenic (GaAs) are widely used, and their operating temperatures are 100°C to 125°C. Solder components for joining these semiconductor elements to circuit boards are required to have a high melting point for multi-stage soldering during manufacturing, crack resistance against repeated thermal stress associated with start / stop, and device contamination resistance.

[0004] In response to this requirement, solder parts made of the following materials are used: 95Pb-5Sn (mass %) in Si devices, 80Au-20Sn (mass %) in GaAs devices, etc. However, 95Pb-5Sn containing a large amount of harmful lead (Pb) has problems from the perspective of reducing environmental load, and 80Au-20Sn containing a large amount of precious metals has problems from the perspective of high precious metal prices and reserves, and both strongly expect the need for alternative materials.

[0005] On the other hand, in order to increase the output and miniaturize power semiconductor devices, there is a trend to adopt wide-bandgap semiconductors such as silicon carbide (SiC) as next-generation devices to achieve high current density and high operating temperature. Therefore, high bonding reliability is required in the solder joint under the semiconductor element.

[0006] As shown in Patent Document 1, in a power cycle test in which a semiconductor element is repeatedly powered on / off to generate heat, longitudinal cracks are generated in a direction perpendicular to the solder joint. Patent Document 1 discloses that after the longitudinal cracks occur, the longitudinal crack width increases and the heat dissipation decreases, and the cracks develop from the fragile parts of the solder joint to cause a defect.

[0007] In the semiconductor device disclosed in Patent Document 2, a pressing plate that functions as a pressing member is used to implement a countermeasure against longitudinal cracks in the solder joint. In the semiconductor device, since the solder joint thickness increases corresponding to the amount of space in which longitudinal cracks occur in the solder joint, the pressing plate is used to press the semiconductor element and the insulating substrate in a closer contact to avoid the increase in the solder joint thickness. The pressing function of the pressing plate controls the solder thickness between the insulating substrate and the semiconductor element so as not to increase, thereby suppressing longitudinal cracks in the center of the solder.

[0008] In addition, in the semiconductor device disclosed in Patent Document 3, a metal plate that contacts the upper surface side conductor connected to the upper surface electrode layer of the semiconductor element fixed on the DBC (Direct Bond Copper) substrate is provided as a push-in component. In the semiconductor device disclosed in Patent Document 3, the metal plate is connected to the copper circuit foil of the DBC substrate for fixing the metal plate in a manner that presses the upper surface side conductor toward the semiconductor element. Furthermore, the semiconductor device has a bonding structure in which a frame that serves as a guide for positioning the semiconductor element and the upper surface side conductor is fixed to the DBC substrate.

[0009] Prior art literature

[0010] Patent Literature

[0011] Patent Document 1: International Publication No. 2012 / 077228

[0012] Patent Document 2: Japanese Patent Application Publication No. 2017-135183

[0013] Patent Document 3: Japanese Patent Application Publication No. 2011-176087 Summary of the invention

[0014] In order to suppress the longitudinal cracks generated in the solder joint under the semiconductor element during the power cycle test as shown in Patent Document 1, it is effective to provide a structure of a pressing member for pressing the solder joint as disclosed in Patent Document 2 and Patent Document 3. That is, as the pressing member, the semiconductor device disclosed in Patent Document 2 uses a pressing plate, and the semiconductor device disclosed in Patent Document 3 uses a metal plate.

[0015] Generally speaking, it is difficult to form a uniform thickness of a solder joint, and the film thickness of the solder joint is often uneven. When a push-in component is used to press the solder joint through the semiconductor element on a semiconductor device having a solder joint with uneven film thickness, it becomes a partial contact state that only touches one side of the semiconductor element. Therefore, it is difficult to stably press the solder joint of a semiconductor device having a solder joint with uneven film thickness.

[0016] Here, the region of the semiconductor element that is sufficiently pressed by the pressing member when the partial contact state occurs is referred to as the properly pressed region, and the region of the semiconductor element that is not sufficiently pressed by the pressing member is referred to as the incompletely pressed region.

[0017] In the above case, longitudinal cracks occur in the solder joint in the region below the incompletely pressed region of the semiconductor element, and the solder joint thickness increases excessively, so that the heat dissipation of the solder joint is extremely reduced, resulting in a high possibility that the semiconductor element itself is destroyed during the power cycle test.

[0018] Furthermore, in the case of the metal plate used in the semiconductor device disclosed in Patent Document 3, if the surface of the metal plate is rough, the contact resistance is unstable in the point connection state when power is applied, and an overheated portion is locally generated due to power application during a power cycle test, resulting in premature bonding failure.

[0019] In addition, in the case of a semiconductor device having a push-in member, a pressing plate or a metal plate is redundantly provided, so there is a problem that the size of the joint structure including the push-in member in the semiconductor device increases, and the size of the power module increases.

[0020] The present disclosure aims to provide a semiconductor device that can solve the above-mentioned problems, realize miniaturization of the device, and ensure bonding reliability in a solder joint portion.

[0021] The semiconductor device disclosed in the present invention comprises: a substrate; and a semiconductor element, which is arranged on the substrate with a solder joint portion in between, and the substrate and the semiconductor element are joined through the solder joint portion, and also comprises: a metal wire, one end of which is connected to the semiconductor element, and the other end is connected to the substrate; and an insulating coated wire, which has a wire portion and an insulating coating portion arranged to cover the wire portion, is arranged independently of the metal wire, crosses the semiconductor element to connect one end and the other end to the substrate, and the insulating coated wire is arranged in a form in which the insulating coating portion contacts the surface of the semiconductor element, and has a pressing force that presses the semiconductor element in the direction of the solder joint portion.

[0022] The insulated coated wire in the semiconductor device of the present disclosure has a pressing force that presses the semiconductor element in the direction of the solder joint portion.

[0023] Therefore, the semiconductor device of the present disclosure can suppress the increase in film thickness due to longitudinal cracking of the solder joint, which can effectively suppress the undesirable phenomenon of heat generation in the semiconductor element when the film thickness of the solder joint is uneven.

[0024] As a result, the semiconductor device of the present disclosure can ensure high bonding reliability in the solder bonding portion.

[0025] The insulation coated wire has a structure in which the insulation coating covers the outer periphery of the wire portion. Therefore, even if the insulation coated wire contacts the surface of the semiconductor element, the semiconductor element and the wire portion are not electrically connected.

[0026] Therefore, in the semiconductor device of the present disclosure, the presence of the insulating coated wire does not affect the operation of the semiconductor element.

[0027] Furthermore, since the insulating coated wire having the wire portion and the insulating coating portion is a relatively small-scale component, the semiconductor device of the present disclosure can achieve miniaturization of the device.

[0028] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a flowchart showing the method for manufacturing the semiconductor device according to the first embodiment.

[0030] Figure 2 It is an explanatory diagram showing the method for manufacturing the semiconductor device according to the first embodiment.

[0031] Figure 3 It is an explanatory diagram showing the method for manufacturing the semiconductor device according to the first embodiment.

[0032] Figure 4 It is an explanatory diagram showing the method for manufacturing the semiconductor device according to the first embodiment.

[0033] Figure 5 It is an explanatory diagram showing the method for manufacturing the semiconductor device according to the first embodiment.

[0034] Figure 6 It is an explanatory diagram showing the method for manufacturing the semiconductor device according to the first embodiment.

[0035] Figure 7 It is an explanatory diagram showing the method for manufacturing the semiconductor device according to the first embodiment.

[0036] Figure 8 It is an explanatory diagram showing the method for manufacturing the semiconductor device according to the first embodiment.

[0037] Fig. 9 It is an explanatory diagram showing the method for manufacturing the semiconductor device according to the first embodiment.

[0038] Fig.10 It is an explanatory diagram showing the method for manufacturing the semiconductor device according to the first embodiment.

[0039] Fig.11 It is an explanatory diagram showing the method for manufacturing the semiconductor device according to the first embodiment.

[0040] Fig.12 It is an explanatory diagram showing the method for manufacturing the semiconductor device according to the first embodiment.

[0041] Fig.13 It is an explanatory diagram showing the method for manufacturing the semiconductor device according to the first embodiment.

[0042] Fig.14 This is a graph showing the variation in thickness of the solder joint portion.

[0043] Fig.15 It is shown Fig.12 as well as Fig.13 A cross-sectional view of the cross-sectional structure of the insulated coated wire shown.

[0044] Fig.16 This is an explanatory diagram showing the effects of the embodiment in a table format.

[0045] Fig.17 This is an explanatory diagram showing the structure of a semiconductor device as a second embodiment.

[0046] Fig.18 This is an explanatory diagram showing the structure of a semiconductor device as a second embodiment.

[0047] Fig.19 This is an explanatory diagram showing the structure of a semiconductor device as a third embodiment.

[0048] Fig. 20 This is an explanatory diagram showing the structure of a semiconductor device as a third embodiment.

[0049] Fig.21 It is an explanatory diagram showing the structure of a comparative semiconductor device.

[0050] Fig. 22 It is an explanatory diagram showing the structure of a comparative semiconductor device.

[0051] (Explanation of Reference Numerals)

[0052] 1: semiconductor element; 2: solder joint; 3, 11: upper electrode; 4, 12: insulating substrate; 5: lower electrode; 6: metal wire; 7, 17: insulating coated wire; 8: DBC substrate; 13: heat sink; 14: integrated substrate. DETAILED DESCRIPTION

[0053] <Implementation Method 1>

[0054] Figure 11 is a flowchart showing a method for manufacturing the semiconductor device 51 according to the first embodiment of the present disclosure. Figure 2 to Figure 13 It is an explanatory diagram showing a method for manufacturing the semiconductor device 51 according to the second embodiment. Figure 2 , Figure 4 , Figure 6 , Figure 8 , Fig.10 as well as Fig.12 It is a cross-sectional view. Figure 3 , Figure 5 , Figure 7 , Fig. 9 , Fig.11 as well as Fig.13 is a top view. Figure 2 to Figure 13 An XYZ orthogonal coordinate system is shown in . Hereinafter, the manufacturing process of the semiconductor device 51 will be described with reference to these figures.

[0055] First, in step S1, Figure 2 as well as Figure 3 As shown, a DBC (Direct Bonded Copper) substrate 8 is prepared. In addition, Figure 3 The AA section is Figure 2 .

[0056] The DBC substrate 8 serving as the substrate for the semiconductor element 1 includes, as main components, an upper electrode 3, an insulating base 4, and a lower electrode 5. The upper electrode 3 is provided on the upper surface of the insulating base 4, and the lower electrode 5 is provided on the lower surface of the insulating base 4.

[0057] The insulating base 4 is made of silicon nitride (Si3N4) and has a thickness of 0.32 mm. The upper electrode 3 is made of copper (Cu) and has a thickness of 0.4 mm.

[0058] The lower electrode 5 has a structure in which three layers (Cu / Si3N4 / Cu) are bonded together, and has a film thickness of 0.4 mm. As a method for bonding the three layers constituting the lower electrode 5, direct bonding based on an anchoring effect using a surface roughening technique or bonding based on a brazing filler metal is considered. As the brazing filler metal, for example, Ag solder, Cu solder, Al solder, and Zn solder are considered.

[0059] The upper electrode 3 of the DBC substrate 8 is formed with a pattern including a main region 3m and connection regions 3a to 3c. As a method for forming the above pattern, a first method of first performing a desired patterning on the upper electrode 3 and then attaching it to the insulating base 4 using a jig or the like, or a second method of attaching the constituent material of the upper electrode 3 to the insulating base 4 and then patterning the upper electrode 3 by etching is considered.

[0060] The patterned upper electrode 3 has a main region 3m and connection regions 3a to 3c. The main region 3m becomes a solder joint region to be joined to the semiconductor element 1 via a solder joint portion 2 described later.

[0061] Among the connection areas 3a to 3c, the connection area 3a and the connection area 3b are electrically independent, and the connection area 3a and the connection area 3c are electrically independent. Among the connection areas 3a to 3c, the connection area 3a is classified as a first connection area actually used for electrical connection with an external terminal, and the connection areas 3b and 3c are classified as second connection areas for joining the insulation covered wires 7 and 17 described later.

[0062] Therefore, the connection regions 3 b and 3 c classified as the second connection regions are not actually used without being electrically connected to external terminals, and no current flows through the insulation covered conductors 7 and 17 described later.

[0063] Next, in step S2, Figure 4 as well as Figure 5 As shown, a solder sheet 20 is arranged on the DBC substrate 8. In addition, Figure 5 The BB profile becomes Figure 4 .

[0064] The solder sheet 20 is disposed on the main region 3m of the upper electrode 3 and has a film thickness of 100 μm and a size slightly larger than 10 mm×10 mm when viewed from the XY plane. The solder sheet 20 is a solder member that will become the solder joint 2 in the future.

[0065] In this embodiment, Sn-3Ag-0.5Cu, which is a general-purpose lead-free solder, is used as a component of the solder sheet 20. In "Sn-3Ag-0.5Cu", the weight percentages of Sn, Ag, and Cu are Sn: 96.5%, Ag: 3.0%, and Cu: 0.5%.

[0066] Here, the solder may be in the form of solder paste instead of a sheet. That is, solder paste may be placed on the upper electrode 3 of the DBC substrate 8 instead of the solder sheet 20. In the case of solder paste, it is considered to be formed using a metal mask printing technique or a flat dispensing supply method.

[0067] As the composition of the solder sheet 20 and the solder component including the solder paste, Sn may be used as the main component and other metals (Ag, Cu, Sb, Ni, Fe, Al, Ti, Zn, etc.) may be added arbitrarily. Furthermore, although the joining temperature becomes higher, Zn may be used as the main component of the solder component, and if the product is not subject to RoHs (Restriction on Hazardous Substances) restrictions, Pb may be used as the main component of the solder component.

[0068] Then, in step S3, Figure 6 as well as Figure 7 As shown, the semiconductor element 1 is arranged on the solder sheet 20. In addition, Figure 7 The CC section is Figure 6 .

[0069] The semiconductor element 1 has a film thickness of 0.3 mm and a size of 10 mm×10 mm when viewed from above in the XY plane. The constituent material of the semiconductor element 1 is SiC.

[0070] The back surface of the semiconductor element 1 becomes a bonding surface with the solder sheet 20, and a back metal film (not shown) is formed on the back surface of the semiconductor element 1. The back metal film is formed in the order of Ti50nm / Ni700nm / Au200nm toward the -Z direction.

[0071] In addition, the surface of the semiconductor element 1 becomes a bonding surface with a plurality of metal wires 6 described later. A surface metal film (not shown) is formed on the surface of the semiconductor element 1. As the surface metal film, Al5 μm is formed. In addition, in the back metal film and the surface metal film, Xddnm means that the constituent material is X and the film thickness is dd (nm).

[0072] Here, when placing the semiconductor element 1 on the solder sheet 20, if a general-purpose chip mounter is used, the semiconductor element 1 can be mounted on the solder sheet 20 with high accuracy. In order to suppress positional deviation when mounting the semiconductor element 1, the semiconductor element 1 may be placed on the solder sheet 20 and temporarily fixed by pressing the semiconductor element 1 with a chip mounter heated to a temperature lower than 220° C., which is the melting point of the solder, for example, 175° C.

[0073] Next, in step S4, Figure 8 as well as Fig. 9 As shown, the semiconductor element 1 and the DBC substrate 8 are bonded via the solder bonding portion 2. Fig. 9 The DD profile is Figure 8 .

[0074] That is, in step S4, the solder sheet 20 is heated and melted. The melted solder sheet 20 after step S4 becomes the solder joint 2, and the front surface of the DBC substrate 8 and the back surface of the semiconductor element 1 are joined via the solder joint 2.

[0075] In the solder joining process performed in step S4, an organic acid having a reducing and removing ability of the metal oxide film is used, and then a heat treatment is performed at 260° C. for 5 minutes after a heat treatment is performed at 180° C. in a general formic acid atmosphere. In addition, in the case of solder paste instead of the solder sheet 20, since the flux as a reducing and removing agent is already contained, formic acid is not required, and it can also be performed in a N2 atmosphere.

[0076] If the flux is not of the no-residue type, the organic residue attached to the periphery of the solder joint 2 can be easily removed by wet cleaning. If it is of the no-residue type, cleaning is not necessary.

[0077] Fig.14 Graph 2 is a graph showing the deviation in thickness of the solder joint 2 obtained after step S4 is executed. Fig.14 In Fig. 9 The film thickness displacement in the Z direction of the solder joint portion 2 between the points D1 and D2 along the X direction is shown as a film thickness difference Δt.

[0078] Fig.14 The film thickness difference Δt shown represents the deviation of the film thickness of the solder joint 2, which is calculated by measuring the film thickness of the semiconductor element 1 from the center with a laser displacement meter and assuming that the thickness of the semiconductor element 1 is constant. When the film thickness at point D1 is T1 and the film thickness at point D2 is T2, the film thickness difference Δt is expressed by the following formula (1).

[0079] Δt=|T1-T2|(μm)…(1)

[0080] In formula (1), |Y| means the absolute value of Y.

[0081] Next, in step S5, Fig.10 as well as Fig.11 As shown, a plurality of metal wires 6 are formed. In addition, Fig.11 The EE profile is Fig.10 In the drawings, the plurality of metal wires 6 are indicated by dotted lines for ease of illustration, but are of course formed continuously.

[0082] The metal wires 6 have a wire diameter of 150 μm and are made of Al. In step S5 , one end of each metal wire 6 is bonded to the surface of the semiconductor element 1 , and the other end of each metal wire 6 is bonded to the connection region 3 a of the upper electrode 3 of the DBC substrate 8 .

[0083] The metal wire 6 may be made of a material other than Al. For example, the metal wire 6 may be made of an Al alloy mainly composed of Al, Cu and a Cu alloy mainly composed of Cu, or a Cu / Al clad wire clad with Cu and Al.

[0084] The surface of the semiconductor element 1 and one end of the metal wire 6, and the upper electrode 3 of the DBC substrate 8 and the other end of the metal wire 6 are bonded using an ultrasonic bonding method that applies ultrasonic waves and loads. However, as long as the electrical connection between the semiconductor element 1 and the upper electrode 3 is ensured and components such as the surface metal film of the semiconductor element 1 and the upper electrode 3 of the DBC substrate 8 are not damaged, any bonding method other than the ultrasonic bonding method can be used as the bonding method for the metal wire 6.

[0085] The wire diameter of the metal wire 6 is also a design matter and can be adjusted arbitrarily. In the second embodiment, for the semiconductor element 1 with a chip size of 10 mm×10 mm, a plurality of metal wires 6 are arranged at intervals of 2.5 mm along the Y direction, which is the second direction. The plurality of metal wires 6 extend in the X direction, respectively. That is, the arrangement direction of the plurality of metal wires 6 is the X direction, which is the first direction.

[0086] Then, in step S6, Fig.12 as well as Fig.13 As shown, a plurality of insulating coated wires 7 are formed independently of the plurality of metal wires 6. In addition, Fig.13 The FF section is Fig.12 The plurality of insulating coated conductive wires 7 each include constituent materials and have the same structure.

[0087] Fig.15 2 is a cross-sectional view showing an example of the cross-sectional structure of the insulation coated wire 7. As shown in the figure, the insulation coated wire 7 includes a wire portion 71 and an insulation coating portion 72 provided to cover the outer periphery of the wire portion 71 as main components.

[0088] The conductor portion 71 of the insulating coated conductor 7 is made of Cu as a constituent material, and has a wire diameter of 150 μm.

[0089] The material constituting the lead portion 71 may be any of Al, Fe, Ti, Ni and Cr in addition to Cu. The lead portion 71 is required to have a function of suppressing an increase in the bonding thickness that occurs when the solder bond portion 2 is longitudinally cracked.

[0090] Therefore, the lead portion 71 needs to satisfy the following yield stress requirement: the yield stress calculated by the tensile test method specified in the international standard ISO6892-1 in the temperature range of 25°C to 150°C is higher than that of the constituent material of the solder joint 2. That is, if the lead portion 71 of each of the plurality of insulated coated leads 7 satisfies the above yield stress requirement in the operating environment of the semiconductor element 1 specified in the temperature range of 25°C to 150°C, the increase in the solder thickness of the solder joint 2 can be suppressed.

[0091] On the other hand, in the insulating coating 72, a resin insulating film of class F having high heat resistance is used as a constituent material, and the film thickness is set to 10 μm. The resin insulating film constituting the insulating coating 72 may have a heat resistance type of any of class F, H, N, and R specified in the international standard IEC60085.

[0092] Furthermore, according to the international standard IEC60085, the maximum allowable temperature of class F is 155°C, the maximum allowable temperature of class H is 180°C, the maximum allowable temperature of class N is 200°C, and the maximum allowable temperature of class R is 220°C.

[0093] When executing step S6, the plurality of insulated coated wires 7 are respectively connected to the connection region 3b in the upper electrode 3 of the DBC substrate 8 at one end and the other end thereof, with the insulating coating portion 72 of the central region in contact with the surface of the semiconductor element 1, and cross the semiconductor element 1. Specifically, in the two connection regions 3b, 3b separately existing on the -X side and the +X side, one end of the plurality of insulated coated wires 7 is connected to the connection region 3b on the -X side, and the other end is connected to the connection region 3b on the +X side.

[0094] At this time, since the plurality of insulated coated wires 7 are disposed without any slack, they have a pressing force that presses the semiconductor element 1 in the direction of the solder joint portion 2 .

[0095] Furthermore, the plurality of insulated coated wires 7 are respectively arranged along the X direction, which is the first direction, and the plurality of insulated coated wires 7 are arranged so as not to overlap with the plurality of metal wires 6 when viewed from above. Specifically, one insulated coated wire 7 is arranged between two metal wires 6, 6 arranged in the Y direction. In this way, the plurality of insulated coated wires 7 are arranged independently of the plurality of metal wires 6, and the plurality of insulated coated wires 7 and the plurality of metal wires 6 are not electrically connected.

[0096] Regarding the fixation of one end and the other end of the insulated coated wire 7 crossing the semiconductor element 1 to the DBC substrate 8, the surface insulating coating part 72 is repelled to the outside by ultrasonic energy in the ultrasonic bonding method, and the wire part 71 and the connection area 3b are bonded by metal diffusion bonding.

[0097] After executing step S6 , the semiconductor device 51 of the first embodiment is completed.

[0098] Fig.16 This is an explanatory diagram showing the effects of the embodiment in a table format. Fig.21 as well as Fig. 22 1 is an explanatory diagram showing the structure of a comparative semiconductor device 60 serving as a comparative technique. Fig.21 It is a cross-sectional view. Fig. 22 It is a top view. Fig. 22 The II section is Fig.21 .exist Fig.21 as well as Fig. 22 The XYZ orthogonal coordinate system is shown in FIG.

[0099] like Fig.21 as well as Fig. 22 As shown, the comparative semiconductor device 60 is different from the semiconductor device 51 of the first embodiment in that it does not include the insulating coated wire 7 but includes the insulating film 9 and the copper block 10 .

[0100] The insulating film 9 is provided on the surface of the semiconductor element 1 so as not to be in contact with the plurality of metal wires 6, and the copper block 10 is provided on the insulating film 9. The copper block 10 uses the solder joint 2 as a pressing member.

[0101] exist Fig.16 In the text, "good" and "bad" are used to indicate the Fig.14 The experimental results shown are when a power cycle test was performed on semiconductor devices having a plurality of types of solder joints 2 having different film thickness differences Δt.

[0102] exist Fig.16 , experimental results are shown for cases where the film thickness difference Δt of the solder joint portion 2 is 5, 8, 15, 33, 52, 78, and 90 (μm), respectively.

[0103] For each of the comparative semiconductor device 60, the semiconductor device 51 of the first embodiment, and the semiconductor device 52 of the second embodiment described later, a power cycle test was performed in such a manner that the junction temperature of the solder joint 2 when the semiconductor element 1 was set to the power-on state was 150° C., and the junction temperature of the solder joint 2 when the semiconductor element 1 was set to the power-off state was 80° C. That is, each voltage and current were adjusted in such a manner that ΔT = 70° C. (150° C. - 80° C.), and the semiconductor device 51 and the like were subjected to a cycle test 50,000 times with constant power on.

[0104] exist Fig.16 In the test, after 50,000 cycles, if the operating temperature is lower than 155°C, which is set 5°C higher than 150°C, it is judged as "good", and if it is higher than 155°C, it is judged as "bad".

[0105] like Fig.16 As shown, in the comparative semiconductor device 60 using the copper block 10 as the push-in member, when the thickness deviation is greater than Δt=5μm, the initial connection is unstable, so the heat generation increases and it is judged as "defective". The reason is that if it is a solid like the copper block 10, it cannot follow the thickness deviation of the solder joint 2, and the push-in effect of the copper block 10 is small, resulting in a partial contact state.

[0106] On the other hand, in the semiconductor device 51 shown in the first embodiment, the pressing force of the plurality of insulating coated wires 7 acts on each portion of the solder joint 2 , so that good results are obtained in all thickness variation ranges of the solder joint 2 .

[0107] In addition, the cross-sectional shape of the conductor portion 71 of the insulating coated conductor 7 may also be a rectangular shape instead of a rectangular shape. Fig.15 That is, even if a rectangular wire is used as the insulating coated conductive wire 7, the same pressing force can be exerted as in the case where the cross-sectional shape is circular.

[0108] (Effect)

[0109] By executing Figure 1 The semiconductor device 51 of the first embodiment is manufactured through steps S1 to S6. The plurality of insulated coated wires 7 in the semiconductor device 51 each have a pressing force that presses the semiconductor element 1 in the direction of the solder joint portion 2.

[0110] Therefore, the semiconductor device 51 of the first embodiment can suppress the increase in film thickness due to longitudinal cracking of the solder joint 2. This effect can effectively suppress the problem of heat generation in the semiconductor element 1 when the film thickness of the solder joint 2 is uneven.

[0111] As a result, the semiconductor device 51 according to the first embodiment can ensure high bonding reliability in the solder joint 2 .

[0112] Each of the plurality of insulation coated wires 7 has a structure in which the insulation coating 72 covers the outer periphery of the wire portion 71. Therefore, even if the plurality of insulation coated wires 7 come into contact with the surface of the semiconductor element 1, the semiconductor element 1 and the wire portion 71 are not electrically connected.

[0113] Therefore, in the semiconductor device 51 according to the first embodiment, the presence of the plurality of insulating coated wires 7 does not affect the operation of the semiconductor element 1 .

[0114] Furthermore, since the plurality of insulating coated wires 7 each having the wire portion 71 and the insulating coating portion 72 are relatively small-scale components, the semiconductor device 51 can be miniaturized.

[0115] In the semiconductor device 51 of embodiment 1, the multiple insulated coated wires 7 do not overlap with the multiple metal wires 6 when viewed from above, so the semiconductor device 51 does not cause adverse effects caused by the contact between the multiple insulated coated wires 7 and the multiple metal wires 6, and the multiple insulated coated wires 7 can exert the above-mentioned pressing force respectively.

[0116] In the upper electrode 3 of the DBC substrate 8, the connection region 3a as the first connection region and the connection region 3b as the second connection region are electrically independent of each other. Therefore, in the semiconductor device 51, even if one end of each of the plurality of metal wires 6 and one end and the other end of each of the plurality of insulating coated wires 7 are commonly connected to the upper electrode 3, the presence of the plurality of insulating coated wires 7 will not hinder the operation of the semiconductor element 1.

[0117] The lead portion 71 of each insulating coated lead 7 satisfies the yield stress requirement that the yield stress is higher than that of the solder joint portion 2 under the operating environment of the semiconductor element 1 defined in the temperature range of 25° C. to 150° C.

[0118] Therefore, when the semiconductor element 1 is operated in a temperature range of 25° C. to 150° C., the semiconductor device 51 of the first embodiment can suppress the increase in the film thickness of the solder joint 2 without hindrance by the pressing force of each of the plurality of insulating coated wires 7 .

[0119] Furthermore, when the semiconductor element 1 is a SiC device, the above-mentioned yield stress requirement needs to be satisfied in an operating environment of the semiconductor element 1 defined in a temperature range exceeding 150° C.

[0120] The constituent material of the lead portion 71 includes at least one of Al (aluminum), Cu (copper), Fe (iron), Ti (titanium), Ni (nickel), and Cr (chromium), and thus can satisfy the above-mentioned yield stress requirement.

[0121] The insulating coating 72 in each insulating coated wire 7 is of the heat-resistant type mentioned above, so even if the semiconductor element 1 is operated in the above temperature range, the insulating coating 72 will not be peeled off, and the increase in the film thickness of the solder joint 2 can be smoothly suppressed by the pressing force of each of the multiple insulating coated wires 7.

[0122] <Implementation Method 2>

[0123] Fig.17 as well as Fig.18 It is an explanatory diagram showing the structure of a semiconductor device 52 as Embodiment 2 of the present disclosure. Fig.17 is a cross-sectional view showing the cross-sectional structure of the semiconductor device 52, Fig.18 is a top view showing the planar structure of the semiconductor device 52. In addition, Fig.18The GG section is Fig.17 In addition, Fig.17 as well as Fig.18 The XYZ orthogonal coordinate system is shown in FIG.

[0124] Hereinafter, regarding the structure of the semiconductor device 52 according to the second embodiment, the same reference numerals are given to the same parts as those of the semiconductor device 51 according to the first embodiment, and the description thereof will be omitted as appropriate, and the description will be mainly focused on the characteristic parts of the second embodiment.

[0125] The plurality of insulated coated wires 17 are respectively composed of constituent materials and present the same structure. The cross-sectional structure of the insulated coated wires 17 is as follows: Fig.15 As shown, the insulating coated wire 17 includes a conductor portion 71 and an insulating coating portion 72 as main components, similarly to the insulating coated wire 7. The conductor portion 71 and the insulating coating portion 72 of the insulating coated wire 17 are also made of the same materials as those of the insulating coated wire 7.

[0126] like Fig.17 as well as Fig.18 As shown, the plurality of insulated coated wires 17 are respectively connected to the surface of the semiconductor element 1 by making the insulating coating portion 72 of the central region contact with the semiconductor element 1 and crossing the semiconductor element 1, and one end and the other end are bonded to the connection region 3c in the upper electrode 3 of the DBC substrate 8. Specifically, in the two connection regions 3c, 3c separately existing on the +Y side and the -Y side, one end of the plurality of insulated coated wires 17 is bonded to the connection region 3c on the +Y side, and the other end is bonded to the connection region 3c on the -Y side.

[0127] Furthermore, since the plurality of insulated coated wires 17 are provided without any slack, they have a pressing force that presses the semiconductor element 1 in the direction of the solder joint 2 , similarly to the plurality of insulated coated wires 7 .

[0128] Furthermore, the plurality of insulated coated conductive wires 17 are respectively provided along the Y direction intersecting the X direction at right angles. Here, the X direction is the first direction, and the Y direction is the second direction.

[0129] However, the plurality of insulating coated wires 17 are arranged so as not to have a contact relationship with the plurality of metal wires 6. Specifically, as Fig.17 As shown, the portions of the plurality of metal wires 6 that intersect with any of the plurality of insulation coated wires 17 are arranged above the corresponding insulation coated wires 17 separated by a space. In this way, the plurality of insulation coated wires 17 are independently provided with the plurality of metal wires 6, and the plurality of insulation coated wires 17 and the plurality of metal wires 6 are not electrically connected.

[0130] Regarding fixing one end and the other end of the insulated coated wire 17 to the DBC substrate 8 across the semiconductor element 1, for example, the surface insulating coating portion 72 is repelled to the outside by ultrasonic energy in an ultrasonic bonding method, and the wire portion 71 and the connection area 3c are bonded by metal diffusion bonding.

[0131] The method for manufacturing the semiconductor device 52 according to the second embodiment proceeds to steps S1 to S5 in the same manner as the method for manufacturing the semiconductor device 51 according to the first embodiment.

[0132] Then, as step S6 , a process of forming a plurality of insulating coated wires 17 instead of the plurality of insulating coated wires 7 is performed, thereby completing the semiconductor device 52 of the second embodiment.

[0133] In the semiconductor device 52 shown in the second embodiment, the pressing force of the plurality of insulating coated wires 17 acts on each portion of the solder joint 2, so that Fig.16 As shown, similarly to the semiconductor device 51 of the first embodiment, good results were obtained in all ranges of thickness variations in the solder joint portion 2 .

[0134] In addition, the cross-sectional shape of the conductor portion 71 of the insulating coated conductor 17 may also be a rectangular shape instead of a rectangular shape. Fig.15 That is, even if a rectangular wire is used as the insulating coated conductive wire 17, the same pressing force as the case where the cross-sectional shape is circular can be exerted.

[0135] (Effect)

[0136] via Figure 1 The semiconductor device 52 of the second embodiment is manufactured by performing steps S1 to S5 and a step of forming the plurality of insulating coated wires 17. The plurality of insulating coated wires 17 in the semiconductor device 52 each have a pressing force that presses the semiconductor element 1 in the direction of the solder joint 2.

[0137] Therefore, the semiconductor device 52 of the second embodiment has the effect of being able to suppress an increase in film thickness due to vertical cracking of the solder joint portion 2, similarly to the first embodiment.

[0138] As a result, the semiconductor device 52 according to the second embodiment can ensure high bonding reliability in the solder joint 2 .

[0139] Each of the plurality of insulation coated wires 17 has a structure in which the insulation coating 72 covers the outer periphery of the wire portion 71. Therefore, even if the plurality of insulation coated wires 17 come into contact with the surface of the semiconductor element 1, the semiconductor element 1 and the wire portion 71 are not electrically connected.

[0140] Therefore, in the semiconductor device 52 of the second embodiment, the presence of the plurality of insulating coated wires 17 does not affect the operation of the semiconductor element 1 .

[0141] Furthermore, since the plurality of insulating coated wires 17 each having the wire portion 71 and the insulating coating portion 72 is a relatively small-scale component, the semiconductor device 52 can be miniaturized.

[0142] In the semiconductor device 52 , the plurality of insulated coated wires 17 are not in contact with the plurality of metal wires 6 , so that the plurality of insulated coated wires 17 can exert the above-mentioned pressing force respectively without causing adverse effects caused by the contact between the plurality of insulated coated wires 17 and the plurality of metal wires 6 .

[0143] In the upper electrode 3 of the DBC substrate 8, the connection region 3a as the first connection region and the connection region 3c as the second connection region are electrically independent of each other. Therefore, in the semiconductor device 52, even if one end of each of the plurality of metal wires 6 and one end and the other end of each of the plurality of insulating coated wires 17 are connected to the upper electrode 3 in common, the presence of the plurality of insulating coated wires 17 will not hinder the operation of the semiconductor element 1.

[0144] Furthermore, the insulation coated conductive wire 17 is composed of a conductive wire portion 71 and an insulation coating portion 72 similarly to the insulation coated conductive wire 7 .

[0145] Therefore, the semiconductor device 52 according to the second embodiment can exhibit the effects associated with the lead portion 71 and the insulating coating portion 72 similarly to the semiconductor device 51 according to the first embodiment.

[0146] <Implementation Method 3>

[0147] Fig.19 as well as Fig. 20 It is an explanatory diagram showing the structure of a semiconductor device 53 as Embodiment 3 of the present disclosure. Fig.19 is a cross-sectional view showing the cross-sectional structure of the semiconductor device 53, Fig. 20 is a top view showing the planar structure of the semiconductor device 53. In addition, Fig. 20 The HH profile is Fig.19 In addition, Fig.19 as well as Fig. 20 The XYZ orthogonal coordinate system is shown in FIG.

[0148] Hereinafter, regarding the structure of the semiconductor device 53 , the same reference numerals are given to the same parts as those of the semiconductor device 51 , and the description thereof will be omitted as appropriate, and the description will be mainly focused on the characteristic parts of the third embodiment.

[0149] The semiconductor device 53 according to the third embodiment is characterized in that the DBC substrate 8 in the semiconductor device 51 according to the first embodiment is replaced with an integrated substrate 14 .

[0150] The integrated substrate 14 serving as the substrate for the semiconductor element 1 includes the upper electrode 11, the insulating base 12, and the heat sink 13 as main components. The upper electrode 11 is provided on the upper surface of the insulating base 12, and the heat sink 13 is provided on the lower surface of the insulating base 12.

[0151] The constituent material and structure of the upper electrode 11 are the same as those of the upper electrode 3 of the DBC substrate 8. The constituent material and structure of the insulating base 12 are the same as those of the insulating base 4 of the DBC substrate 8.

[0152] The heat sink 13 has conductivity as a “lower electrode” in a broad sense, similarly to the lower electrode 5 of the DBC substrate 8 .

[0153] However, the heat sink 13 is different from the lower electrode 5 of the DBC substrate 8 in that it has an upper surface wider than the lower surface of the insulating base 12 and has a greater film thickness than the insulating base 12 .

[0154] The upper electrode 11 of the integrated substrate 14 is patterned similarly to the upper electrode 3 of the DBC substrate 8 .

[0155] The patterned upper electrode 11 has a main region 11m and connection regions 11a to 11c. In the relationship between the upper electrode 11 and the upper electrode 3, the main region 11m corresponds to the main region 3m, and the connection regions 11a to 11c correspond to the connection regions 3a to 3c.

[0156] The main region 11m is a region bonded to the semiconductor element 1 via the solder joint 2. Among the connection regions 11a to 11c, the connection region 11a and the connection region 11b are electrically independent, and the connection region 11a and the connection region 11c are electrically independent. The connection region 11a is classified as a first connection region actually used for electrical connection to an external terminal, and the connection regions 11b and 11c are classified as second connection regions for bonding the insulated coated wire 7 and the insulated coated wire 17.

[0157] Therefore, the connection region 11 b and the connection region 11 c classified as the second connection region are not actually used without being electrically connected to the external terminal, and no current flows through the insulated covered conductive wires 7 and 17 .

[0158] like Fig.19 as well as Fig. 20As shown, the plurality of insulated coated wires 7 are respectively connected to the surface of the semiconductor element 1 by making the insulating coating portion 72 of the central region contact the semiconductor element 1 and crossing the semiconductor element 1, and one end and the other end are bonded to the connection region 11b in the upper electrode 11 of the integrated substrate 14. Specifically, in the two connection regions 11b and 11b separately existing on the -X side and the +X side, one end of the plurality of insulated coated wires 7 is bonded to the connection region 11b on the -X side, and the other end is bonded to the connection region 11b on the +X side.

[0159] Furthermore, since the plurality of insulated coated wires 7 are provided without any slack, they have a pressing force that presses the semiconductor element 1 in the direction of the solder joint 2 .

[0160] Furthermore, the plurality of insulated coated wires 7 are respectively arranged along the X direction which is the first direction, and the plurality of insulated coated wires 7 are arranged so as not to overlap with the plurality of metal wires 6 when viewed from above. Thus, the plurality of insulated coated wires 7 are arranged independently of the plurality of metal wires 6, and the plurality of insulated coated wires 7 and the plurality of metal wires 6 are not electrically connected.

[0161] Regarding fixing one end and the other end of the insulating coated wire 7 to the integrated substrate 14 across the semiconductor element 1, the insulating coated portion 72 on the surface is repelled to the outside by ultrasonic energy in the ultrasonic bonding method, and the wire portion 71 and the connection area 11b are bonded by metal diffusion bonding.

[0162] The method for manufacturing the semiconductor device 53 according to the third embodiment is performed in the same manner as the semiconductor device 51 according to the first embodiment, except that the DBC substrate 8 is replaced with the integrated substrate 14 .

[0163] Therefore, through Figure 1 After the same steps as steps S1 to S5 shown, a step of forming a plurality of insulating coated wires 7 so as to be bonded to the integrated substrate 14 is performed as step S6, whereby the semiconductor device 53 of the third embodiment can be manufactured.

[0164] In addition, the cross-sectional shape of the conductor portion 71 of the insulating coated conductor 7 may also be a rectangular shape instead of a rectangular shape. Fig.15 That is, even if a rectangular wire is used as the insulating coated conductive wire 7, the same pressing force as the case where the cross-sectional shape is circular can be exerted.

[0165] (Effect)

[0166] The semiconductor device 53 of the third embodiment is manufactured through steps S1 to S6 similar to those of the first embodiment. The plurality of insulated coated wires 7 in the semiconductor device 53 each have a pressing force that presses the semiconductor element 1 in the direction of the solder joint portion 2 .

[0167] Therefore, the semiconductor device 53 of the third embodiment has the effect of being able to suppress an increase in film thickness due to vertical cracking of the solder joint portion 2, similarly to the first and second embodiments.

[0168] As a result, the semiconductor device 53 according to the third embodiment can ensure high bonding reliability in the solder joint 2 .

[0169] Therefore, it can be inferred that Fig.16 The same results as those of the first and second embodiments were obtained in the power cycle test shown.

[0170] Furthermore, in semiconductor device 53 of the fifth embodiment, heat sink 13 functioning as the lower electrode of integrated substrate 14 has dimensional characteristics of having an upper surface wider than the lower surface of insulating base 12 and having a film thickness thicker than insulating base 12 .

[0171] Therefore, the integrated substrate 14 itself including the heat sink 13 can fully exert a heat dissipation function for the semiconductor device 53. Therefore, it is not necessary to provide a heat dissipation member outside the semiconductor device 53.

[0172] Furthermore, since the semiconductor device 53 of the third embodiment includes the plurality of insulated coated wires 7 having substantially the same features as those of the first embodiment, the plurality of insulated coated wires 7 can provide the same effects as those of the first embodiment.

[0173] In addition, in the upper electrode 11 of the integrated substrate 14 of the semiconductor device 53, the connection region 11a as the first connection region and the connection region 11b as the second connection region are electrically independent of each other. Therefore, in the semiconductor device 53, even if one end of each of the plurality of metal wires 6 and one end and the other end of each of the plurality of insulating coated wires 7 are commonly connected to the upper electrode 11, the presence of the plurality of insulating coated wires 7 will not hinder the operation of the semiconductor element 1.

[0174] In addition, the plurality of insulated coated wires 7 of the semiconductor device 53 may be replaced with the insulated coated wires 17 of the second embodiment. That is, instead of the plurality of insulated coated wires 7, the plurality of insulated coated wires 17 may be connected between the connection regions 11c, 11c of the upper electrode 11 as in the second embodiment.

[0175] In addition, the present disclosure can freely combine the various embodiments within the scope of the disclosure, or can appropriately modify or omit the various embodiments.

Claims

1. A semiconductor device comprising: substrate; and A semiconductor element is provided on the substrate via a solder joint portion. The substrate and the semiconductor element are joined via the solder joint portion, The semiconductor device further comprises: a metal wire, one end of which is connected to the semiconductor element, and the other end of which is connected to the substrate; and an insulating coated wire having a wire portion and an insulating coating portion provided to cover the wire portion, provided independently of the metal wire, and crossing over the semiconductor element to connect one end and the other end to the substrate, The insulation coated wire is provided in a form in which the insulation coating portion is in contact with the surface of the semiconductor element, and has a pressing force for pressing the semiconductor element in a direction of the solder joint portion.

2. The semiconductor device according to claim 1, wherein The metal wire includes a plurality of metal wires respectively arranged along a first direction, The insulated coated wire includes a plurality of insulated coated wires respectively arranged along the first direction. The plurality of insulation coated wires do not overlap with the plurality of metal wires in a plan view.

3. The semiconductor device according to claim 1, wherein The metal wire includes a plurality of metal wires respectively arranged along a first direction, The insulated coated wire includes a plurality of insulated coated wires respectively arranged along a second direction intersecting the first direction. The plurality of insulation coated wires are not in contact with the plurality of metal wires.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The substrate comprises: an insulating substrate; and an upper electrode, disposed on the upper surface of the insulating substrate, The upper electrode has a first connection region and a second connection region, The other end of the metal wire is connected to the first connection region of the upper electrode. One end and the other end of the insulating coated wire are connected at the second connection region of the upper electrode. The first connection region and the second connection region are electrically independent from each other.

5. The semiconductor device according to claim 4, wherein: The substrate further includes a heat sink disposed on the lower surface of the insulating base. The heat sink has an upper surface wider than a lower surface of the insulating base and has a thickness thicker than that of the insulating base.

6. The semiconductor device according to any one of claims 1 to 3, wherein: The lead portion of the insulation coated lead meets a yield stress requirement that the yield stress is higher than that of the solder joint portion under the operating environment of the semiconductor element.

7. The semiconductor device according to claim 6, wherein: A constituent material of the lead portion includes at least one of Al, Cu, Fe, Ti, Ni, and Cr.

8. The semiconductor device according to any one of claims 1 to 3, wherein: The heat-resistant type of the insulating coating is any of the F type, the H type, the N type, and the R type specified in the international standard IEC60085.

9. A method for manufacturing a semiconductor device, comprising: (a) a step of preparing a substrate; (b) a step of disposing a solder component on the substrate; (c) a step of disposing a semiconductor element on the solder member; (d) heating and melting the solder member, wherein the solder member after performing step (d) becomes a solder joint portion, and the substrate and the semiconductor element are joined via the solder joint portion; (e) a step of bonding one end of a metal wire to the semiconductor element and bonding the other end to the substrate; as well as (f) using an insulating coated wire having a wire portion and an insulating coating portion provided to cover the wire portion, the insulating coating portion being brought into contact with a surface of the semiconductor element and crossing the semiconductor element to join one end and the other end of the insulating coated wire to the substrate, wherein the insulating coated wire is formed independently of the metal wire, After the step (f) is performed, the insulated coated wire has a pressing force that presses the semiconductor element in the direction of the solder joint portion.

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