An over-temperature protection circuit

Abstract

This invention provides an over-temperature protection circuit comprising at least: a reference module, an adjustment module, a reference signal generation module, an error amplification module, a constant current module, and a sampling feedback module. The reference module provides a reference voltage and a negative temperature coefficient voltage. The reference signal generation module is connected to the output of the reference module. The adjustment module is connected between the outputs of the reference voltage generation module and the reference module. The error amplification module is connected to the outputs of the feedback signal generation module and the reference signal generation module. The constant current module is connected to the output of the error amplification module. The sampling feedback module is connected to the output of the constant current module. This circuit enables the charging chip to perform temperature protection by linearly reducing the charging current under different temperatures, especially under non-extreme high temperatures, improving charging safety and reducing chip wear. Furthermore, its simple structure makes it suitable for various charging chips and facilitates integrated applications.

Description

Technical Field

[0001] This invention relates to the field of over-temperature protection technology, and in particular to an over-temperature protection circuit. Background Technology

[0002] Circuits, especially high-current charging circuits, experience temperature increases during operation due to heat generated by the components. To prevent damage from overheating, it's necessary to control the circuit temperature during operation. This ensures normal component operation, extends component lifespan, and reduces hardware wear and tear.

[0003] In existing charging chips, the internal circuitry mostly uses conventional thermal shutdown for temperature protection. However, in practical applications, charging chips need to protect the chip from different temperatures, especially under non-extreme high-temperature conditions, where the charging current should be appropriately reduced to ensure charging safety and reduce chip wear. Therefore, using only thermal shutdown for chip temperature protection is no longer sufficient to meet the needs of existing charging chips. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an over-temperature protection circuit to solve the problem that the charging chip can only use thermal shutdown for temperature protection in the prior art, which leads to increased chip loss and reduced safety.

[0005] To achieve the above and other related objectives, the present invention provides an over-temperature protection circuit, which includes at least: a reference module, an adjustment module, a reference signal generation module, an error amplification module, a constant current module, and a sampling feedback module, wherein:

[0006] The reference module is used to provide a reference voltage and a negative temperature coefficient voltage;

[0007] The reference signal generation module is connected to the output terminal of the reference module and divides the reference voltage to generate a reference signal;

[0008] The adjustment module is connected between the output terminals of the reference voltage generation module and the reference module. It generates a drive signal based on the difference between the reference voltage and the negative temperature coefficient voltage, and adjusts the voltage value of the reference signal in reverse phase based on the temperature change. As the temperature increases, the negative temperature coefficient voltage decreases, and the voltage value of the drive signal decreases. When the voltage value of the drive signal is less than the voltage value of the reference signal, the reference signal sinks current to the adjustment module to reduce the voltage value of the reference signal.

[0009] The error amplification module is connected to the output of the feedback signal and the reference signal generation module to amplify the difference between the reference signal and the feedback signal.

[0010] The constant current module is connected to the output terminal of the error amplification module, and generates a charging current that varies proportionally with the reference signal based on the output signal of the error amplification module.

[0011] The sampling feedback module is connected to the output terminal of the constant current module, collects the charging current, and converts it into the feedback signal corresponding to the charging current.

[0012] Optionally, the over-temperature protection circuit further includes: a first resistor, a second resistor, and a first capacitor, wherein: the first end of the first resistor is connected to the output terminal of the reference module to divide and output the reference voltage; the second resistor is connected between the second end of the first resistor and the reference ground; and the first capacitor is connected in parallel with the second resistor.

[0013] Optionally, the reference module includes: a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first PNP transistor, a second PNP transistor, and a first error amplifier, wherein: the base and collector of the first PNP transistor are connected to reference ground; the first terminal of the third resistor is connected to the emitter of the first PNP transistor; the base and collector of the second PNP transistor are connected to reference ground, and the emitter outputs the negative temperature coefficient voltage; the non-inverting input terminal of the first error amplifier is connected to the second terminal of the third resistor, and the inverting input terminal is connected to the emitter of the second PNP transistor, outputting the reference voltage; the first terminal of the fourth resistor is connected to the second terminal of the third resistor; the fifth resistor is connected between the second terminal of the fourth resistor and the emitter of the second PNP transistor; and the sixth resistor is connected between the second terminal of the fourth resistor and the output terminal of the first error amplifier.

[0014] Optionally, the resistance values ​​of the fourth resistor and the fifth resistor are equal.

[0015] Optionally, the ratio of the first PNP transistor to the second PNP transistor is N:1, where N is a natural number greater than or equal to 2.

[0016] Optionally, the adjustment module includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a seventh resistor, an eighth resistor, a current source, and an adjustment unit, wherein: the gate and drain of the first NMOS transistor are connected, and the source is connected to a reference ground; the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor, and the source is connected to a reference ground; the gate and drain of the third NMOS transistor are connected, and the source is connected to a reference ground; the gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor, and the source is connected to a reference ground; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the gate receives the reference voltage; the first terminal of the seventh resistor is connected to the source of the first PMOS transistor; The drain of the second PMOS transistor is connected to the drain of the third NMOS transistor, and the gate receives the negative temperature coefficient voltage; the eighth resistor is connected between the second terminal of the seventh resistor and the source of the second PMOS transistor; the current source is connected between the second terminal of the seventh resistor and the supply voltage; the drain and gate of the third PMOS transistor are connected to the drain of the second NMOS transistor, and the source is connected to the supply voltage; the source of the fourth PMOS transistor is connected to the supply voltage, the gate is connected to the gate of the third PMOS transistor, and the drain is connected to the drain of the fourth NMOS transistor and outputs the drive signal; one end of the adjustment unit is connected to the drive signal, and the other end is connected to the output terminal of the reference signal generation module. When the voltage value of the drive signal is less than the voltage value of the reference signal, the adjustment unit is turned on to pull the reference signal low.

[0017] Optionally, the adjustment unit includes a fifth NMOS transistor, the drain of which is connected to the drain of the fourth PMOS transistor, and the source and gate of which are connected to the reference signal.

[0018] Optionally, the seventh resistor has the same resistance value as the eighth resistor.

[0019] Optionally, the width-to-length ratio of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor is 2:2:1:4; and the width-to-length ratio of the third PMOS transistor to the fourth PMOS transistor is 1:2.

[0020] Optionally, the reference signal generation module includes: a ninth resistor, a tenth resistor, an eleventh resistor, and a second capacitor, wherein: the first terminal of the ninth resistor receives the reference voltage; the tenth resistor is connected between the second terminal of the ninth resistor and a reference ground; the first terminal of the eleventh resistor is connected to the second terminal of the ninth resistor; and the second capacitor is connected between the second terminal of the eleventh resistor and a reference ground.

[0021] Optionally, the error amplification module includes a second error amplifier, wherein the non-inverting input of the second error amplifier receives the reference signal, and the inverting input receives the feedback signal.

[0022] Optionally, the constant current module includes: a PWM modulator (Pulse Width Modulator), switching logic, a fifth PMOS transistor, a sixth NMOS transistor, an inductor, a sampling resistor, and an energy storage capacitor, wherein: the input terminal of the PWM modulator receives the output signal of the error amplification module; the input terminal of the switching logic is connected to the output terminal of the PWM modulator; the source of the fifth PMOS transistor is connected to the power supply voltage, and its gate is connected to the first output terminal of the switching logic; the drain of the sixth NMOS transistor is connected to the drain of the fifth PMOS transistor, its gate is connected to the second output terminal of the switching logic, and its source is connected to reference ground; the first terminal of the inductor is connected to the drain of the fifth PMOS transistor; the first terminal of the sampling resistor is connected to the second terminal of the inductor; and the energy storage capacitor is connected between the second terminal of the sampling resistor and the reference ground.

[0023] Optionally, the sampling feedback module includes: a twelfth resistor, a thirteenth resistor, a fourteenth resistor, an operational amplifier, and a sixth PMOS transistor, wherein: the non-inverting input terminal of the operational amplifier collects the charging current through the thirteenth resistor, and the inverting input terminal collects the charging current through the twelfth resistor; the gate of the sixth PMOS transistor is connected to the output terminal of the operational amplifier, the source is connected to the inverting input terminal of the operational amplifier, and the drain outputs the feedback signal; the fourteenth resistor is connected between the drain of the sixth PMOS transistor and the reference ground.

[0024] Optionally, the resistance values ​​of the twelfth resistor and the thirteenth resistor are equal.

[0025] As described above, the over-temperature protection circuit of the present invention has the following beneficial effects:

[0026] 1) The charging chip uses a linear reduction in charging current to protect the temperature under different temperatures, especially under non-extreme high temperature conditions, which improves charging safety and reduces chip wear.

[0027] 2) This over-temperature protection circuit has a simple structure, is suitable for various charging chips, and is easy to integrate. Attached Figure Description

[0028] Figure 1 The diagram shown is a schematic diagram of the over-temperature protection circuit provided in an embodiment of this application.

[0029] Figure 2The diagram shows the voltage of the reference signal provided in this embodiment as a function of temperature.

[0030] Component designation explanation

[0031] 100 Reference Module

[0032] 101 First Error Amplifier

[0033] 200 Adjustment Module

[0034] 201 Current Source

[0035] 202 Adjustment Unit

[0036] 300 Reference Signal Generation Module

[0037] 400 Error Amplification Module

[0038] 401 Second Error Amplifier

[0039] 500 constant current module

[0040] 501 PWM modulator

[0041] 502 Switching Logic

[0042] 600 Sampling Feedback Module

[0043] 601 Operational Amplifier Detailed Implementation

[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] Please see Figure 1 and Figure 2 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] like Figure 1 As shown, this embodiment provides an over-temperature protection circuit, which includes at least: a reference module 100, an adjustment module 200, a reference signal generation module 300, an error amplification module 400, a constant current module 500, and a sampling feedback module 600, wherein:

[0047] like Figure 1 As shown, the reference module 100 is used to provide the reference voltage VBGR and the negative temperature coefficient voltage VBE.

[0048] Specifically, as an example, such as Figure 1 As shown, the reference module 100 includes: a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first PNP transistor Q1, a second PNP transistor Q2, and a first error amplifier 101, wherein: the base and collector of the first PNP transistor Q1 are connected to reference ground; the first end of the third resistor R3 is connected to the emitter of the first PNP transistor Q1; the base and collector of the second PNP transistor Q2 are connected to reference ground, and the emitter outputs the negative temperature coefficient voltage VBE; the non-inverting input of the first error amplifier 101 is connected to the second end of the third resistor R3, and the inverting input is connected to the emitter of the second PNP transistor Q2, outputting the reference voltage VBGR; the first end of the fourth resistor R4 is connected to the second end of the third resistor R3; the fifth resistor R5 is connected between the second end of the fourth resistor R4 and the emitter of the second PNP transistor Q2; and the sixth resistor R6 is connected between the second end of the fourth resistor R4 and the output of the first error amplifier 101.

[0049] More specifically, such as Figure 1 As shown, the resistance values ​​of the fourth resistor R4 and the fifth resistor R5 are equal; the ratio of the first PNP transistor to the second PNP transistor is N:1, where N is a natural number greater than or equal to 2. As an example, the ratio of the first PNP transistor to the second PNP transistor is generally 8:1. The specific setting should be based on the actual application scenario and is not limited to this embodiment. It should be noted that the reference module 100 can also be implemented using IP cores (Intellectual Property cores, pre-designed circuit function modules used in application-specific integrated circuits or field-programmable gate arrays), application-specific integrated circuits, digital signal processors, etc. Any method that can provide the reference voltage VBGR and the negative temperature coefficient voltage VBE is applicable and is not limited to this embodiment.

[0050] Specifically, as an example, such as Figure 1As shown, the over-temperature protection circuit further includes: a first resistor R1, a second resistor R2, and a first capacitor C1, wherein: the first end of the first resistor R1 is connected to the output terminal of the reference module 100, and divides the reference voltage VBGR to obtain voltage VR1, which is used to power the next stage device; the second resistor R2 is connected between the second end of the first resistor R1 and the reference ground; the first capacitor C1 is connected in parallel with the second resistor R2. It should be noted that the voltage division operation of the reference voltage VBGR includes, but is not limited to, the first resistor R1, the second resistor R2, and the first capacitor C1, and needs to be set according to the specific application scenario, and is not limited to this embodiment.

[0051] like Figure 1 As shown, the reference signal generation module 300 is connected to the output terminal of the reference module 100 and performs voltage division on the reference voltage VBGR to generate the reference signal VREF.

[0052] Specifically, as an example, such as Figure 1 As shown, the reference signal generation module 300 includes: a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a second capacitor C2, wherein: the first terminal of the ninth resistor R9 receives the reference voltage VBGR; the tenth resistor R10 is connected between the second terminal of the ninth resistor R9 and the reference ground; the first terminal of the eleventh resistor R11 is connected to the second terminal of the ninth resistor R9; and the second capacitor C2 is connected between the second terminal of the eleventh resistor R11 and the reference ground. It should be noted that the acquisition method of the reference signal VREF includes, but is not limited to, combinations of the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, and the second capacitor C2, and needs to be set according to the specific application scenario, and is not limited to this embodiment.

[0053] like Figure 1 As shown, the adjustment module 200 is connected between the output terminals of the reference voltage generation module 300 and the reference module 100. It generates a drive signal OUT based on the difference between the reference voltage VBGR and the negative temperature coefficient voltage VBE, and adjusts the voltage value of the reference signal VREF in reverse phase based on the temperature change. As the temperature increases, the negative temperature coefficient voltage VBE decreases, and the voltage value of the drive signal OUT decreases. When the voltage value of the drive signal OUT is less than the voltage value of the reference signal VREF, the reference signal VREF sinks current to the adjustment module 200, thereby reducing the voltage value of the reference signal VREF.

[0054] Specifically, as an example, such as Figure 1As shown, the adjustment module 200 includes: a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a seventh resistor R7, an eighth resistor R8, a current source 201, and an adjustment unit 202, wherein: the gate and drain of the first NMOS transistor MN1 are connected, and the source is connected to reference ground; the gate of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1, and the source is connected to reference ground; the gate and drain of the third NMOS transistor MN3 are connected, and the source is connected to reference ground; the gate of the fourth NMOS transistor MN4 is connected to the gate of the third NMOS transistor MN3, and the source is connected to reference ground; the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1, and the gate receives the reference voltage; the first terminal of the seventh resistor R7 is connected to the source of the first PMOS transistor MP1; the second... The drain of PMOS transistor MP2 is connected to the drain of the third NMOS transistor MN3, and its gate receives the negative temperature coefficient voltage VBE. The eighth resistor R8 is connected between the second terminal of the seventh resistor R7 and the source of the second PMOS transistor MP2. The current source 201 is connected between the second terminal of the seventh resistor R7 and the supply voltage VDD. The drain and gate of the third PMOS transistor MP3 are connected to the drain of the second NMOS transistor MN2, and its source is connected to the supply voltage VDD. The source of the fourth PMOS transistor MP4 is connected to the supply voltage VDD, its gate is connected to the gate of the third PMOS transistor MP3, and its drain is connected to the drain of the fourth NMOS transistor MN4, and it outputs the drive signal OUT. One end of the adjustment unit 202 is connected to the drive signal OUT, and the other end is connected to the output terminal of the reference signal generation module 300. When the voltage value of the drive signal OUT is less than the voltage value of the reference signal VREF, the adjustment unit 202 is turned on to pull the reference signal VREF low.

[0055] More specifically, such as Figure 1As shown, the adjustment unit 202 includes a fifth NMOS transistor MN5. The drain of the fifth NMOS transistor MN5 is connected to the drain of the fourth PMOS transistor MP4, and the source and gate are connected to the reference signal VREF. It should be noted that the adjustment unit 202 includes, but is not limited to, the fifth NMOS transistor MN5. Any method that can adjust the reference signal VREF is applicable and is not limited to this embodiment. The resistance values ​​of the seventh resistor R7 and the eighth resistor R8 are equal. The width-to-length ratio of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 is 2:2:1:4. The width-to-length ratio of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 is 1:2. It should be noted that the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 can be set to have equal width-to-length ratios, with a ratio of 2:2:1:4; or they can be set to equal ratios with a width-to-length ratio of 2:2:1:4. The specific setting depends on the actual application scenario and is not limited to this embodiment. Similarly, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 can be set to equal width-to-length ratios, with a ratio of 1:2; or they can be set to equal ratios with a width-to-length ratio of 1:2. The specific setting depends on the actual application scenario and is not limited to this embodiment.

[0056] Furthermore, it needs to be explained that, such as Figure 1As shown, due to the properties of the negative temperature coefficient voltage VBE, the gate voltage of the second PMOS transistor MP2 decreases as the temperature increases, causing the current through the fourth NMOS transistor MN4 to increase. Since the current I1 of the current source 201 is a constant, the drain voltage of the fourth PMOS transistor MP4 decreases, that is, the voltage value of the drive signal OUT decreases. When the voltage value of the drive signal OUT is lower than the voltage value of the reference signal VREF, the reference signal VREF flows back current to the drive signal OUT, which is equivalent to drawing current from the branch of the ninth resistor R9 and the tenth resistor R10. If the current drawn at this time is Iref, then the ninth resistor... The voltage at the connection point X of R9 and the tenth resistor R10 is: Vx = 1.2 - {(1.2 / (R9+R10)+Iref)*R9}. The voltage of the reference signal VREF is: VREF = Vx - (Iref*R11). Usually, the resistance of the eleventh resistor R11 is much larger than that of the ninth resistor R9 and the tenth resistor R10, so the voltage of Vx is not much different from that of the reference voltage VBGR. However, the voltage difference across the eleventh resistor R11 increases with the increase of Iref. The value of Iref increases with the increase of temperature. It can be seen that the voltage of the reference signal VREF will decrease with the increase of temperature, showing a linear decreasing trend.

[0057] As an example, such as Figure 2 As shown, within the temperature range of 100℃ to 110℃, the negative temperature coefficient voltage VBE decreases with temperature, approaching the voltage value of voltage VR1. At this time, the voltage of the reference signal VREF can decrease almost linearly. When the temperature exceeds 110℃, the voltage value of the negative temperature coefficient voltage VBE gradually decreases, and the current of the fourth NMOS transistor MN4 tends to level off, exhibiting an exponential decreasing trend.

[0058] like Figure 1 As shown, the error amplification module 400 is connected to the output terminal of the feedback signal VCHRG and the reference signal generation module 300, and amplifies the difference between the reference signal VREF and the feedback signal VCHRG.

[0059] Specifically, as an example, such as Figure 1 As shown, the error amplification module 400 includes a second error amplifier 401, wherein the non-inverting input of the second error amplifier 401 receives the reference signal VREF, and the inverting input receives the feedback signal VCHRG. It should be noted that the error amplification module 400 includes, but is not limited to, the second error amplifier 401; any method capable of amplifying the difference between the reference signal VREF and the feedback signal VCHRG is applicable and is not limited to this embodiment.

[0060] like Figure 1 As shown, the constant current module 500 is connected to the output terminal of the error amplification module 400, and generates a charging current that varies proportionally with the reference signal VREF based on the output signal COMP of the error amplification module 400.

[0061] Specifically, as an example, such as Figure 1 As shown, the constant current module 500 includes: a PWM modulator 501, a switching logic 502, a fifth PMOS transistor MP5, a sixth NMOS transistor MN6, an inductor L, a sampling resistor RS, and an energy storage capacitor COUT. The input terminal of the PWM modulator 501 receives the output signal COMP from the error amplification module 400. The input terminal of the switching logic 502 is connected to the output terminal of the PWM modulator 501. The source of the fifth PMOS transistor MP5 is connected to the power supply voltage VDD, and its gate is connected to the first output terminal of the switching logic 502. The drain of the sixth NMOS transistor MN6 is connected to the drain of the fifth PMOS transistor MP5, its gate is connected to the second output terminal of the switching logic 502, and its source is connected to reference ground. The first terminal of the inductor L is connected to the drain of the fifth PMOS transistor MP5. The first terminal of the sampling resistor RS is connected to the second terminal of the inductor L. The energy storage capacitor COUT is connected between the second terminal of the sampling resistor RS and the reference ground. It should be noted that the switching logic 502 is used to drive the fifth PMOS transistor MP5 and the sixth NMOS transistor MN6. The high and low levels generated by the PWM modulator 501 ensure that the dead time (the dead time is the period after the fifth PMOS transistor MP5 is turned off before the sixth NMOS transistor MN6 is turned on, or the period after the sixth NMOS transistor MN6 is turned off before the fifth PMOS transistor MP5 is turned on, thus preventing power components from burning out; this delay time is the dead time) and the switching losses of the fifth PMOS transistor MP5 and the sixth NMOS transistor MN6 during their turn-on and turn-off are minimized. This effectively enables the fifth PMOS transistor MP5 and the sixth NMOS transistor MN6 to charge and discharge the inductor L, and under the action of the energy storage capacitor COUT, the charging current remains stable, maintaining a constant current for the load such as the battery BAT.

[0062] like Figure 1 As shown, the sampling feedback module 600 is connected to the output terminal of the constant current module 500, and collects the charging current and converts it into the feedback signal VCHRG corresponding to the charging current.

[0063] Specifically, as an example, such as Figure 1As shown, the sampling feedback module 600 includes: a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, an operational amplifier 601, and a sixth PMOS transistor MP6. Specifically: the non-inverting input of the operational amplifier 601 collects the charging current via the thirteenth resistor R13, and the inverting input collects the charging current via the twelfth resistor R12; the gate of the sixth PMOS transistor MP6 is connected to the output of the operational amplifier 601, its source is connected to the inverting input of the operational amplifier 601, and its drain outputs the feedback signal VCHRG; the fourteenth resistor R14 is connected between the drain of the sixth PMOS transistor MP6 and reference ground. More specifically, the resistance values ​​of the twelfth resistor R12 and the thirteenth resistor R13 are equal. It should be noted that... Figure 1 As shown, due to the voltage drop across the sampling resistor RS, when the resistances of the twelfth resistor R12 and the thirteenth resistor R13 are equal, the voltage drop generates a current difference through the twelfth resistor R12 and the thirteenth resistor R13. This current difference is amplified by the operational amplifier 601, controlling the conduction of the sixth PMOS transistor MP6. The current then passes through the fourteenth resistor R14 to form the feedback signal VCHRG. Normally, the voltage value of the feedback signal VCHRG is equal to the product of the charging current and the sampling resistor RS. When a load such as a battery BAT is being charged at a constant current, the voltage value of the feedback signal VCHRG reaches the voltage value of the reference signal VREF. When the temperature rises, the voltage of the reference signal VREF decreases. Since the sampling resistor RS remains unchanged, the voltage of the feedback signal VCHRG decreases, and the charging current decreases, achieving a linear reduction in the charging current. This enables the over-temperature protection circuit to perform power foldback, thus achieving over-temperature protection.

[0064] Specifically, as an example, such as Figure 1 As shown, the application scenarios of the over-temperature protection circuit provided in this embodiment include, but are not limited to, charging chips, sockets, charging piles, etc. It is applicable to any device that requires over-temperature protection, and will not be described in detail here.

[0065] In summary, the over-temperature protection circuit provided by the present invention is characterized in that the over-temperature protection circuit includes at least: a reference module, an adjustment module, a reference signal generation module, an error amplification module, a constant current module, and a sampling feedback module, wherein: the reference module is used to provide a reference voltage and a negative temperature coefficient voltage; the reference signal generation module is connected to the output terminal of the reference module and divides the reference voltage to generate a reference signal; the adjustment module is connected between the output terminal of the reference voltage generation module and the reference module, generates a drive signal based on the difference between the reference voltage and the negative temperature coefficient voltage, and performs inverse adjustment on the voltage value of the reference signal based on the temperature change, wherein, as the temperature increases... The negative temperature coefficient voltage decreases, and the voltage value of the driving signal decreases. When the voltage value of the driving signal is less than the voltage value of the reference signal, the reference signal injects current into the adjustment module, reducing the voltage value of the reference signal. The error amplification module is connected to the output terminals of the feedback signal and the reference signal generation module, amplifying the difference between the reference signal and the feedback signal. The constant current module is connected to the output terminal of the error amplification module, generating a charging current that changes proportionally to the reference signal based on the output signal of the error amplification module. The sampling feedback module is connected to the output terminal of the constant current module, acquiring the charging current and converting it into the feedback signal corresponding to the charging current. This invention provides an over-temperature protection circuit that enables the charging chip to perform temperature protection by linearly reducing the charging current at different temperatures, especially under non-extreme high temperatures, improving charging safety and reducing chip wear. This over-temperature protection circuit has a simple structure, is suitable for various charging chips, and is easy to integrate. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0066] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An over-temperature protection circuit, characterized in that, The over-temperature protection circuit includes at least: a reference module, an adjustment module, a reference signal generation module, an error amplification module, a constant current module, and a sampling feedback module, wherein: The reference module provides a reference voltage and a negative temperature coefficient voltage. The reference module includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first PNP transistor, a second PNP transistor, and a first error amplifier. The base and collector of the first PNP transistor are connected to a reference ground. The first terminal of the third resistor is connected to the emitter of the first PNP transistor. The base and collector of the second PNP transistor are connected to a reference ground, and the emitter outputs the negative temperature coefficient voltage. The non-inverting input of the first error amplifier is connected to the second terminal of the third resistor, and the inverting input is connected to the emitter of the second PNP transistor, outputting the reference voltage. The first terminal of the fourth resistor is connected to the second terminal of the third resistor. The fifth resistor is connected between the second terminal of the fourth resistor and the emitter of the second PNP transistor. The sixth resistor is connected between the second terminal of the fourth resistor and the output terminal of the first error amplifier. The reference signal generation module is connected to the output terminal of the reference module and divides the reference voltage to generate a reference signal; The adjustment module is connected between the output terminals of the reference signal generation module and the reference module. It generates a drive signal based on the difference between the reference voltage and the negative temperature coefficient voltage, and adjusts the voltage value of the reference signal in reverse phase based on the temperature change. As the temperature increases, the negative temperature coefficient voltage decreases, and the voltage value of the drive signal decreases. When the voltage value of the drive signal is less than the voltage value of the reference signal, the reference signal sinks current to the adjustment module to reduce the voltage value of the reference signal. The error amplification module is connected to the output of the feedback signal and the reference signal generation module to amplify the difference between the reference signal and the feedback signal. The constant current module is connected to the output terminal of the error amplification module, and generates a charging current that varies proportionally with the reference signal based on the output signal of the error amplification module. The sampling feedback module is connected to the output terminal of the constant current module, collects the charging current, and converts it into the feedback signal corresponding to the charging current.

2. The over-temperature protection circuit according to claim 1, characterized in that: The over-temperature protection circuit further includes: a first resistor, a second resistor, and a first capacitor, wherein: the first end of the first resistor is connected to the output terminal of the reference module to divide and output the reference voltage; the second resistor is connected between the second end of the first resistor and the reference ground; and the first capacitor is connected in parallel with the second resistor.

3. The over-temperature protection circuit according to claim 1, characterized in that: The fourth resistor has the same resistance value as the fifth resistor.

4. The over-temperature protection circuit according to claim 1, characterized in that: The ratio of the first PNP transistor to the second PNP transistor is N:1, where N is a natural number greater than or equal to 2.

5. The over-temperature protection circuit according to claim 1, characterized in that: The adjustment module includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a seventh resistor, an eighth resistor, a current source, and an adjustment unit, wherein: the gate and drain of the first NMOS transistor are connected, and the source is connected to a reference ground; the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor, and the source is connected to a reference ground; the gate and drain of the third NMOS transistor are connected, and the source is connected to a reference ground; the gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor, and the source is connected to a reference ground; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the gate receives the reference voltage; the first terminal of the seventh resistor is connected to the source of the first PMOS transistor; the seventh resistor is connected to the eighth resistor; the eighth resistor is connected to the seventh resistor; the seventh resistor is connected to the eighth resistor; the seventh resistor is connected to the seventh ... The drains of the second PMOS transistor are connected to the drain of the third NMOS transistor, and the gate receives the negative temperature coefficient voltage. The eighth resistor is connected between the second terminal of the seventh resistor and the source of the second PMOS transistor. The current source is connected between the second terminal of the seventh resistor and the supply voltage. The drain and gate of the third PMOS transistor are connected to the drain of the second NMOS transistor, and the source is connected to the supply voltage. The source of the fourth PMOS transistor is connected to the supply voltage, the gate is connected to the gate of the third PMOS transistor, and the drain is connected to the drain of the fourth NMOS transistor, and the driving signal is output. One end of the adjustment unit is connected to the driving signal, and the other end is connected to the output of the reference signal generation module. When the voltage value of the driving signal is less than the voltage value of the reference signal, the adjustment unit is turned on to pull the reference signal low.

6. The over-temperature protection circuit according to claim 5, characterized in that: The adjustment unit includes a fifth NMOS transistor, the drain of which is connected to the drain of the fourth PMOS transistor, and the source and gate of which are connected to the reference signal.

7. The over-temperature protection circuit according to claim 5, characterized in that: The seventh resistor has the same resistance value as the eighth resistor.

8. The over-temperature protection circuit according to claim 5, characterized in that: The width-to-length ratio of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor is 2:2:1:4; the width-to-length ratio of the third PMOS transistor to the fourth PMOS transistor is 1:

2.

9. The over-temperature protection circuit according to claim 1, characterized in that: The reference signal generation module includes a ninth resistor, a tenth resistor, an eleventh resistor, and a second capacitor, wherein: the first terminal of the ninth resistor receives the reference voltage; the tenth resistor is connected between the second terminal of the ninth resistor and a reference ground; the first terminal of the eleventh resistor is connected to the second terminal of the ninth resistor; and the second capacitor is connected between the second terminal of the eleventh resistor and a reference ground.

10. The over-temperature protection circuit according to claim 1, characterized in that: The error amplification module includes a second error amplifier, wherein the non-inverting input of the second error amplifier receives the reference signal, and the inverting input receives the feedback signal.

11. The over-temperature protection circuit according to any one of claims 1-10, characterized in that: The constant current module includes: a PWM modulator, switching logic, a fifth PMOS transistor, a sixth NMOS transistor, an inductor, a sampling resistor, and an energy storage capacitor, wherein: the input terminal of the PWM modulator receives the output signal of the error amplification module; the input terminal of the switching logic is connected to the output terminal of the PWM modulator; the source of the fifth PMOS transistor is connected to the power supply voltage, and its gate is connected to the first output terminal of the switching logic; the drain of the sixth NMOS transistor is connected to the drain of the fifth PMOS transistor, its gate is connected to the second output terminal of the switching logic, and its source is connected to reference ground; the first terminal of the inductor is connected to the drain of the fifth PMOS transistor; the first terminal of the sampling resistor is connected to the second terminal of the inductor; and the energy storage capacitor is connected between the second terminal of the sampling resistor and the reference ground.

12. The over-temperature protection circuit according to any one of claims 1-10, characterized in that: The sampling feedback module includes: a twelfth resistor, a thirteenth resistor, a fourteenth resistor, an operational amplifier, and a sixth PMOS transistor, wherein: the non-inverting input terminal of the operational amplifier collects the charging current through the thirteenth resistor, and the inverting input terminal collects the charging current through the twelfth resistor; the gate of the sixth PMOS transistor is connected to the output terminal of the operational amplifier, the source is connected to the inverting input terminal of the operational amplifier, and the drain outputs the feedback signal; the fourteenth resistor is connected between the drain of the sixth PMOS transistor and the reference ground.

13. The over-temperature protection circuit according to claim 12, characterized in that: The resistance values ​​of the twelfth resistor and the thirteenth resistor are equal.

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