Test methods and test systems for serializer and deserializer modules
By constructing control modules and storage units in an FPGA and preloading the configuration information of the serializer and deserializer modules, efficient testing of the serializer and deserializer modules is achieved, solving the problems of excessively long testing time and high cost in existing technologies.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI ANLOGIC INFOTECH CO LTD
- Filing Date
- 2022-09-29
- Publication Date
- 2026-05-26
AI Technical Summary
Existing ATE testing of FPGA serializer and deserializer modules requires multiple loading of bit streams, resulting in excessively long testing time and increased costs, and making it difficult to guarantee test coverage.
A control module is constructed that preloads all configuration information through a storage unit. The control module reads and configures the serializer and deserializer modules in sequence, and performs a test after each configuration to reduce the number of bit stream loading operations.
The test can be completed by loading the bitstream only once, which significantly shortens the test time and reduces the test cost.
Smart Images
Figure CN115542137B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of FPGA technology, and in particular to a test method and test system for serializer and deserializer modules. Background Technology
[0002] A Field Programmable Gate Array (FPGA) is a special type of chip characterized by its high flexibility. The serializer and deserializer (SERDES) modules within an FPGA can be applied to different operating modes, such as wired communication, wireless communication, video and audio transmission, and user-defined protocols.
[0003] Automated Test Equipment (ATE) testing of FPGAs typically requires generating bit streams for each test pattern of the FPGA separately. Each bit stream can only test a portion of the functionality, so multiple bit streams must be used to improve test coverage.
[0004] During testing, different test bit streams need to be loaded sequentially via an external module, with each bit stream testing a specific function. To ensure test coverage, hundreds of bit streams are typically needed to fully cover the test points. Furthermore, these functions need to be tested repeatedly at different temperatures, further increasing the number of bit streams required. Therefore, in ATE testing of the serializer and deserializer modules in an FPGA, to improve the coverage of each submodule, the serializer and deserializer modules need to be configured into multiple modes. Each mode generates a different bit stream, and each bit stream carries different configuration information for the serializer and deserializer modules. For example... Figure 1 As shown, bit stream 1 is loaded, which contains configuration information 1 for the serializer and deserializer modules. The serializer and deserializer modules are configured, and then test mode 1 is applied to the serializer and deserializer modules. Bit stream 2 is loaded, which contains configuration information 2 for the serializer and deserializer modules. The serializer and deserializer modules are configured, and then test mode 2 is applied to the serializer and deserializer modules. This process is repeated, and bit stream n is loaded, which contains configuration information n for the serializer and deserializer modules. The serializer and deserializer modules are configured, and then test mode n is applied to the serializer and deserializer modules.
[0005] The more complex the test function, the larger the amount of bit stream data, and the longer the bit stream loading time. In addition, each bit stream loading requires waiting for the FPGA to clear the previous configuration content before a new bit stream can be loaded, which greatly increases the test time.
[0006] Therefore, it is necessary to provide a novel test method and test system for serializer and deserializer modules to solve the above-mentioned problems existing in the prior art. Summary of the Invention
[0007] The purpose of this invention is to provide a testing method and system for serializer and deserializer modules, thereby shortening the testing time for these modules.
[0008] To achieve the above objectives, the testing method for the serializer and deserializer modules of the present invention, applied to an FPGA, includes:
[0009] Build a control module;
[0010] The control module loads a bit stream and sequentially reads configuration information from the storage unit to configure the serializer and deserializer modules according to the bit stream. After each configuration of the serializer and deserializer modules, the serializer and deserializer modules are tested.
[0011] The beneficial effects of the testing method for the serializer and deserializer modules are as follows: a control module is constructed, a bit stream is loaded, and the control module reads configuration information from the storage unit sequentially according to the bit stream to configure the serializer and deserializer modules. After each configuration of the serializer and deserializer modules, the serializer and deserializer modules are tested. Only the bit stream needs to be loaded once, instead of loading the bit stream multiple times, which greatly shortens the testing time of the serializer and deserializer modules and thus reduces the testing cost.
[0012] Optionally, before executing the loading bitstream, the method further includes:
[0013] All configuration information for the serializer and deserializer modules is stored in the storage unit.
[0014] Optionally, storing all configuration information of the serializer and deserializer modules into the storage unit includes:
[0015] Different portions of all configuration information for the serializer and deserializer modules are stored in the storage unit.
[0016] Optionally, the storage unit includes FPGA registers, distributed RAM, or block RAM.
[0017] Optionally, the control module reads configuration information from the storage unit sequentially according to the bit stream to configure the serializer and deserializer modules, including:
[0018] The control module reads configuration information from the storage unit and writes the configuration information into the control register of the serializer and deserializer modules to configure the serializer and deserializer modules.
[0019] Optionally, after each configuration of the serializer and deserializer modules, the method further includes initializing the serializer and deserializer modules.
[0020] Optionally, the control module includes a state machine or a soft-core microprocessor.
[0021] This invention also provides a test system for serializer and deserializer modules applied to an FPGA, including a construction unit, a bit stream loading unit, and a test unit. The construction unit is used to construct a control module, the bit stream loading unit is used to load a bit stream, the control module is used to sequentially read configuration information from a storage unit according to the bit stream to configure the serializer and deserializer modules, and the test unit is used to test the serializer and deserializer modules after each configuration.
[0022] The beneficial effects of the test system for the serializer and deserializer modules are as follows: the construction unit is used to construct the control module, the bit stream loading unit is used to load the bit stream, the control module is used to read configuration information from the storage unit sequentially according to the bit stream to configure the serializer and deserializer modules, and the test unit is used to test the serializer and deserializer modules after each configuration. Only one bit stream needs to be loaded, instead of multiple loadings, which greatly shortens the test time of the serializer and deserializer modules and thus reduces the test cost.
[0023] Optionally, the storage unit includes FPGA registers, distributed RAM, or block RAM.
[0024] Optionally, the control module includes a state machine or a soft-core microprocessor. Attached Figure Description
[0025] Figure 1 This is a flowchart of the ATE test for serializer and deserializer modules in the prior art.
[0026] Figure 2 This is a flowchart of a test method for the serializer and deserializer modules in some embodiments of the present invention;
[0027] Figure 3 This is a structural block diagram of a test system for the serializer and deserializer modules in some embodiments of the present invention. Detailed Implementation
[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.
[0029] To address the problems existing in the prior art, embodiments of the present invention provide a testing method for serializer and deserializer modules. (Refer to...) Figure 2 The test method for the serializer and deserializer modules, applied to FPGA, includes the following steps:
[0030] S1: Construct the control module;
[0031] S2: Load bit stream. The control module reads configuration information from the storage unit sequentially according to the bit stream to configure the serializer and deserializer modules, and tests the serializer and deserializer modules after each configuration.
[0032] In some embodiments, before executing the loading bit stream, the method further includes storing all configuration information of the serializer and deserializer modules into the storage unit.
[0033] In some embodiments, after each configuration of the serializer and deserializer modules, the method further includes initializing the serializer and deserializer modules.
[0034] Figure 3 This is a structural block diagram of a test system for the serializer and deserializer modules in some embodiments of the present invention. (Refer to...) Figure 3 The test system for the serializer and deserializer modules is used to implement the test method for the serializer and deserializer modules. The test system 100 for the serializer and deserializer modules includes a construction unit 101, a bit stream loading unit 102, and a test unit 103. The construction unit 101 is used to construct a control module 1011. The bit stream loading unit 102 is used to load a bit stream. The control module 1011 is used to read configuration information from the storage unit 104 sequentially according to the bit stream to configure the serializer and deserializer modules 105. The test unit 103 is used to test the serializer and deserializer modules 105 after each configuration.
[0035] In some embodiments, storing all configuration information of the serializer and deserializer modules into the storage unit includes storing different portions of all configuration information of the serializer and deserializer modules into the storage unit.
[0036] In some embodiments, the testing method for the serializer and deserializer modules further includes a configuration parameter extraction step. This step involves: extracting parameter names and values from all tests, identifying parameter values that vary between tests and their corresponding names, until all parameter names and values are obtained, thus acquiring the different parts of all configuration parameters. The parameter names include port values and attribute values. Specifically, configuring the serializer and deserializer modules can be achieved by mapping the parameter values to register addresses and data of the dynamic configuration interface of the serializer and deserializer modules according to their parameter names, or by mapping them to different values on the user logic ports of the serializer and deserializer modules.
[0037] In some embodiments, the control module reads configuration information from the storage unit sequentially according to the bit stream to configure the serializer and deserializer modules, including: the control module reads the configuration information from the storage unit and writes the configuration information into the control registers of the serializer and deserializer modules to configure the serializer and deserializer modules.
[0038] In some embodiments, the storage unit includes FPGA registers, distributed RAM, or block RAM, and the control module includes a state machine or a soft-core microprocessor. The specific process of constructing the control module is common knowledge in the art, and those skilled in the art can implement the control module using the programmable functions of the FPGA; therefore, the specific construction process will not be described in detail here.
[0039] In some embodiments, the test system further includes a configuration information writing unit, which is used to store all configuration information of the serializer and deserializer modules into the storage unit before the configuration unit loads the bit stream.
[0040] In some embodiments, the test system further includes an initialization module, which is used to initialize the serializer and deserializer modules each time the configuration unit configures the serializer and deserializer modules.
[0041] In some embodiments, the configuration information includes first configuration information, second configuration information, ..., nth configuration information, wherein the first configuration information corresponds to the first test item, the second configuration information corresponds to the second test item, and so on, and the nth configuration information corresponds to the nth test item. n is an integer greater than 0.
[0042] In some specific embodiments, the first configuration information, the second configuration information, ..., the nth configuration information are all stored in distributed RAM. The bit stream loading unit loads the bit stream, the control module reads the first configuration information from the distributed RAM according to the bit stream, and then writes the first configuration information into the control register of the serializer and deserializer modules to configure the serializer and deserializer modules. The initialization module initializes the serializer and deserializer modules, and then the testing unit performs a first test on the serializer and deserializer modules. The control module reads the second configuration information from the distributed RAM according to the bit stream. The control module reads the nth configuration information from the distributed RAM according to the bit stream, and then writes the nth configuration information into the control register of the serializer and deserializer modules to configure them. The initialization module initializes the serializer and deserializer modules, and then the testing unit performs the nth test on the serializer and deserializer modules. Similarly, the control module reads the nth configuration information from the distributed RAM according to the bit stream, and then writes the nth configuration information into the control register of the serializer and deserializer modules to configure them. The initialization module initializes the serializer and deserializer modules, and then the testing unit performs the nth test on the serializer and deserializer modules. This method requires loading the bit stream only once, eliminating the need for loading multiple bit streams, thus significantly reducing the time required.
[0043] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.
Claims
1. A test method for a serializer and deserializer module, applied to an FPGA, characterized in that, include: Build a control module; The control module loads a bit stream and sequentially reads configuration information from the storage unit to configure the serializer and deserializer modules according to the bit stream. After each configuration of the serializer and deserializer modules, the serializer and deserializer modules are tested. The testing method for the serializer and deserializer modules further includes a configuration parameter extraction step. The configuration parameters include parameter names and parameter values. The configuration parameter extraction step includes: extracting parameter values that change between all tests and their corresponding parameter names until all parameter names and parameter values are obtained, thereby obtaining the different parts of all configuration parameters. The parameter names include port values and attribute values. Specifically, the parameter values are mapped to the register addresses and data of the dynamic configuration interface of the serializer and deserializer modules according to the parameter names, or mapped to different values on the user logic ports of the serializer and deserializer modules, so as to realize the configuration of the serializer and deserializer modules.
2. The test method for the serializer and deserializer modules according to claim 1, characterized in that, Before executing the loaded bitstream, the following is also included: All configuration information for the serializer and deserializer modules is stored in the storage unit.
3. The test method for the serializer and deserializer modules according to claim 2, characterized in that, The step of storing all configuration information of the serializer and deserializer modules into the storage unit includes: Different portions of all configuration information for the serializer and deserializer modules are stored in the storage unit.
4. The test method for the serializer and deserializer modules according to any one of claims 1 to 3, characterized in that, The storage unit includes FPGA registers, distributed RAM, or block RAM.
5. The test method for the serializer and deserializer modules according to claim 1, characterized in that, The control module reads configuration information from the storage unit sequentially according to the bit stream to configure the serializer and deserializer modules, including: The control module reads configuration information from the storage unit and writes the configuration information into the control register of the serializer and deserializer modules to configure the serializer and deserializer modules.
6. The test method for the serializer and deserializer module according to claim 1 or 5, characterized in that, Each time the serializer and deserializer modules are configured, the following is also included: Initialize the serializer and deserializer modules.
7. The test method for the serializer and deserializer modules according to claim 1, characterized in that, The control module includes a state machine or a soft-core microprocessor.
8. A test system for a serializer and deserializer module, applied to an FPGA, for implementing the test method as described in any one of claims 1 to 7, characterized in that, The testing system includes a construction unit, a bit stream loading unit, and a testing unit. The construction unit is used to construct a control module, the bit stream loading unit is used to load a bit stream, the control module is used to read configuration information from the storage unit sequentially according to the bit stream to configure the serializer and deserializer modules, the control module is also used to extract configuration parameters, and the testing unit is used to test the serializer and deserializer modules after each configuration.
9. The test system for the serializer and deserializer module according to claim 8, characterized in that, The storage unit includes FPGA registers, distributed RAM, or block RAM.
10. The test system for the serializer and deserializer module according to claim 8, characterized in that, The control module includes a state machine or a soft-core microprocessor.