Computing device and its memory dependency management method and machine readable storage medium

Abstract

The present application provides a kind of computing device and its memory dependency management method and machine readable storage medium to solve load-store hazards problem.The memory dependency management method includes: checking whether the store instruction currently issued and the first load instruction previously issued have load-store hazards;In the case where the store instruction currently issued and the first load instruction previously issued have load-store hazards, all load instructions that should be invalid due to out-of-order load-store hazards are retrieved from the plurality of issued instructions previously issued, and the out-of-order issued instructions dependent on these load instructions, the subsequent out-of-order instructions triggered, are determined to be invalid.If the instructions determined to be invalid must be reissued because they must be cleared for other reasons (such as due to incorrect branch prediction, etc.), they must be reissued.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an electronic device, and particularly relates to a computing device and a memory dependency management method and a machine readable storage medium thereof. BACKGROUND

[0002] Generally speaking, the execution of multiple instructions in a computing program is in order. For example, after a previous computing instruction generates a computing result, a store instruction can store the computing result of the processor to a memory, and then a load instruction can fetch the computing result from the memory to the processor for use by a next computing instruction. During the execution of the computing program, the processor can be idle for some reason to wait for the next instruction. In order to improve the performance of the processor, an out-of-order execution (OoOE or OOE) technique is applied in the field of computing engineering. In the out-of-order execution technique, the order of the execution of the instructions by the processor is determined by the availability of the input data, rather than the original order of the computing program. The out-of-order execution can avoid the idling / delay of the processor caused by waiting for the next instruction, and thus can avoid a certain type of delay consumption.

[0003] The out-of-order execution operation can cause a load-store conflict (or load-store hazard) in the execution of the computing program. For example, assuming that a store instruction must be executed before a load instruction can be executed, the out-of-order execution operation can execute the load instruction before the store instruction is executed. As can be imagined, the data fetched from the memory by the load instruction is incorrect, and such a problem is a load-store conflict. How to efficiently solve the load-store conflict problem is one of the technical problems in the field. SUMMARY

[0004] The present disclosure provides a computing device and a memory dependency management method and a machine readable storage medium thereof to solve the load-store conflict (or load-store hazard) problem.

[0005] In an embodiment according to the present application, the memory dependence management method comprises: checking whether a currently issued store instruction and a previously issued first load instruction have a load-store conflict; in the case that the currently issued store instruction and the previously issued first load instruction have a load-store conflict, retrieving at least one conflicting instruction dependent on the first load instruction from a plurality of previously issued instructions, wherein the at least one conflicting instruction comprises the first load instruction; and re-issuing the at least one conflicting instruction.

[0006] In an embodiment according to the present application, the machine-readable storage medium is configured to store non-transitory machine-readable instructions. When the non-transitory machine-readable instructions are executed by a computer, the memory dependence management method can be implemented.

[0007] In an embodiment according to the present application, the computing device comprises a memory and a core. The core is coupled to the memory. The core checks whether a currently issued store instruction and a previously issued first load instruction have a load-store conflict, wherein the store instruction is configured to store data to the memory and the first load instruction is configured to fetch data from the memory. In the case that the currently issued store instruction and the previously issued first load instruction have a load-store conflict, the core retrieves at least one conflicting instruction dependent on the first load instruction from a plurality of previously issued instructions, wherein the at least one conflicting instruction comprises the first load instruction. The core re-issues the at least one conflicting instruction.

[0008] Based on the above, when a currently issued store instruction and a previously issued first load instruction have a load-store conflict, a plurality of previously issued instructions that have been issued for execution and have not been committed in order can contain instructions that are not related to the first load instruction. If all of these previously issued instructions are re-issued, the re-issuing (re-execution) of the instructions that are not related to the first load instruction is a waste of time and resources. In an embodiment of the present application, the core can select one or more instructions from the plurality of previously issued instructions as the conflicting instructions (including the first load instruction and the instructions dependent on the first load instruction) when a load-store conflict occurs, and then re-issue the conflicting instructions to resolve the load-store conflict problem. That is, when a currently issued store instruction and a previously issued first load instruction have a load-store conflict, the instructions that are not related to the first load instruction are not re-issued (re-executed). Therefore, the memory dependence management method can efficiently resolve the load-store conflict problem. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 FIG. 1 is a circuit block diagram of a computing device according to an embodiment of the present application.

[0010] Figure 2 FIG. 2 is a flowchart of a memory dependency management method of a computing device according to an embodiment of the present application.

[0011] Figure 3 FIG. 3 is a circuit block diagram of an operation core according to an embodiment of the present application.

[0012] BRIEF DESCRIPTION OF DRAWINGS

[0013] 100: computing device

[0014] 110: memory DETAILED DESCRIPTION

[0015] Reference will now be made to specific embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. The drawings and description are not necessarily to scale.

[0016] The term "coupled" or "connected" used in the detailed description section of the present application and in the claims, if any, means any direct or indirect coupling or connection. For example, if a first device is coupled or connected to a second device, it can be directly connected to the second device or it can be indirectly connected to the second device through one or more other devices or connections. The terms "first", "second", and the like, if any, used in the detailed description section of the present application and in the claims, if any, are used to name elements, and are not necessarily intended to denote a particular order or order of elements. Also, the use of the same reference numbers in different figures indicates the same or similar elements.

[0017] Figure 1 FIG. 1 is a circuit block diagram of a computing device 100 according to an embodiment of the present application. Figure 1The illustrated computing device 100 includes a memory 110 and an operation core 120. The memory 110 is used to store operands and other data. The present embodiments do not limit the specific data structure of the operands / data. For example, in the application of neural networks, the operands can be vectors, matrices, tensors, or other data. The operation core 120 is coupled to the memory 110. In different application examples, the operation core 120 includes a tensor core, a general matrix multiply (GEMM) core, an arithmetic logic unit (ALU), and / or other operation units. Depending on different design requirements, in some embodiments, the implementation of the operation core 120 described above can be a hardware circuit. In other embodiments, the implementation of the operation core 120 can be firmware, software (i.e., a program), or a combination of the above two. In yet other embodiments, the implementation of the operation core 120 can be a combination of multiple ones of hardware, firmware, and software.

[0018] In terms of hardware, the operation core 120 described above can be implemented as a logic circuit on an integrated circuit. For example, the functions of the operation core 120 can be implemented as various logic blocks, modules, and circuits in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), and / or other processing units. The functions of the operation core 120 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in an integrated circuit, using a hardware description language (e.g., Verilog HDL or VHDL) or other suitable programming language.

[0019] In software and / or firmware form, the functions of the operation core 120 can be implemented as programming codes. For example, the operation core 120 can be implemented by using general programming languages (such as C, C++, or assembly language) or other suitable programming languages. The programming codes can be recorded / stored in a non-transitory machine-readable storage medium. In some embodiments, the machine-readable storage medium includes, for example, semiconductor memories and / or storage devices. The semiconductor memories include memory cards, Read Only Memory (ROM), FLASH memories, programmable logic circuits, or other semiconductor memories. The storage devices include tapes, disks, hard disk drives (HDDs), solid-state drives (SSDs), or other storage devices. Electronic devices (such as computers, Central Processing Units (CPUs), controllers, microcontrollers, or microprocessors) can read and execute the programming codes from the machine-readable storage medium, thereby implementing the functions of the operation core 120. Alternatively, the programming codes can be provided to the electronic devices via any transmission medium (such as communication networks or broadcast waves).

[0020] Figure 2 is a flowchart of a memory dependency management method of a computing device according to an embodiment of the present disclosure. In some embodiments, Figure 2 The memory dependency management method shown in FIG. 1 can be implemented in firmware or software (i.e., a program). For example, Figure 2 The operations of the memory dependency management method shown in FIG. 1 can be implemented as non-transitory machine-readable instructions (programming codes or a program), which can be stored in a machine-readable storage medium. When the non-transitory machine-readable instructions are executed by a computer, the memory dependency management method shown in FIG. 1 can be implemented. Figure 2 In other embodiments, Figure 2 The memory dependency management method shown in FIG. 1 can be implemented in hardware, for example, in the computing device 100 shown in FIG. 2. Figure 1 The computing device 100 shown in FIG. 2.

[0021] Please refer toFigure 1 With Figure 2 The arithmetic core 120 can fetch an instruction (hereinafter, a current instruction) from the memory 110. For example, the arithmetic core 120 can fetch an instruction such as a load instruction, a matrix multiply and accumulation (MMA) instruction, a store instruction, or another instruction from the memory 110. The store instruction is used to store data of the arithmetic core 120 to the memory 110, and the load instruction is used to fetch data (loaded data) from the memory 110 to the arithmetic core 120. The arithmetic core 120 can reorder the fetched instruction so as to issue the instruction to an execution circuit inside the arithmetic core 120. Thus, the arithmetic core 120 can perform out-of-order execution (OoOE or OOE). In order to avoid a load-store hazard, in step S210, the arithmetic core 120 can check whether a store instruction currently issued and a load instruction previously issued have a load-store hazard. In a case where the store instruction currently issued and the load instruction previously issued do not have a load-store hazard (a result of the determination in step S220 is No), the arithmetic core 120 can perform a subsequent normal operation (step S230).

[0022] Here, the load-store hazard can be defined as a case where a part or all of an access address range of the store instruction currently issued overlaps with a part or all of an access address range of the load instruction previously issued, and a reorder queue ID (ROQ ID) of the store instruction is earlier than a reorder queue ID of the load instruction. In a case where the store instruction currently issued and the load instruction previously issued have a load-store hazard (a result of the determination in step S220 is Yes), the arithmetic core 120 can perform step S240. In step S240, the arithmetic core 120 can retrieve at least one conflicting instruction dependent on the load instruction from a plurality of issued instructions previously issued and not committed in order. Here, the at least one conflicting instruction includes the load instruction having a load-store hazard. In a case where one or more instructions of these issued instructions use loaded data of the load instruction having a load-store hazard, the at least one conflicting instruction further includes the one or more instructions (related instructions of the load instruction having a load-store hazard) using the loaded data of the load instruction.

[0023] In step S250, the core 120 can re-issue the conflicting instructions (the load instruction and its related instructions that cause the load-store conflict) retrieved in step S240 so as to re-execute the conflicting instructions after the currently issued store instruction completes execution. After step S250, the core 120 can proceed with the subsequent normal operation (step S230). Thus, Figure 2 The memory dependency management method can solve the load-store conflict problem. It is emphasized that when the currently issued store instruction causes a load-store conflict with the previously issued load instruction, the multiple issued instructions that have been issued for execution and have not been ordered yet can include instructions that are not related to (i.e., not affected by) the load instruction. If all of these issued and not ordered instructions are re-issued and re-executed, the re-issuing (re-executing) of instructions that are not related to the load instruction that causes the load-store conflict is a waste of time and resources. In an embodiment of the present application, the core 120 can retrieve one or more instructions from the multiple issued instructions that have been issued previously as the conflicting instructions when the load-store conflict occurs, and then re-issue (re-execute) the conflicting instructions to solve the load-store conflict problem. That is, when the currently issued store instruction causes a load-store conflict with the previously issued load instruction, the instructions that are not related to the load instruction are not re-issued (re-executed). Thus, Figure 2 The memory dependency management method can efficiently solve the load-store conflict problem.

[0024] Figure 3 FIG. 1 shows a circuit block diagram of an operation core 120 according to an embodiment of the present application. Figure 3 The memory 110 and the operation core 120 can refer to the related descriptions of the memory 110 and the operation core 120 shown in FIG. 1, and thus the descriptions are not repeated. In the embodiment shown in FIG. 1, Figure 1 The memory 110 and the operation core 120 can refer to the related descriptions of the memory 110 and the operation core 120 shown in FIG. 1, and thus the descriptions are not repeated. In the embodiment shown in FIG. 1, Figure 3 In the embodiment shown in FIG. 1, the operation core 120 includes a reorder queue (ROQ) circuit 121, an execution circuit 122, and a load-store queue (LSQ) circuit 123. The reorder queue circuit 121 can fill the correlation between multiple instructions into a correlation information table. The specific structure of the correlation information table can be determined according to actual design.

[0025] For example, Table 1 is one specific example of a dependency information table. The dependency information table shown in Table 1 includes a reorder queue identification number (ROQJD) field, an instruction field, a source operand field, and a destination operand field. The instruction field shown in Table 1 is for the benefit of the reader, and an actual dependency information table can not have the instruction field shown in Table 1. The instruction field shown in Table 1 exhibits pseudo code for a plurality of instructions, where st_mem(adr 100) represents a store instruction with an address of "adr 100," st_mem(adr 200) represents a store instruction with an address of "adr 200," ld_mem(adr 100) represents a load instruction with an address of "adr 100," ld_mem(adr 300) represents a load instruction with an address of "adr 300," inst_4(#2) represents an instruction with a source operand of reorder queue identification number "2," inst_5(#3) represents an instruction with a source operand of reorder queue identification number "3," inst_10(#3) represents another instruction with a source operand of reorder queue identification number "3," inst_11(#4,5) represents an instruction with source operands of reorder queue identification numbers "4" and "5," inst_12(#11) represents an instruction with a source operand of reorder queue identification number "11," inst_13(#10) represents an instruction with a source operand of reorder queue identification number "10," inst_14(#13) represents an instruction with a source operand of reorder queue identification number "13," inst_15(#14) represents an instruction with a source operand of reorder queue identification number "14," and inst_6, inst_7, inst_8, and inst_9 represent other instructions. The reorder queue circuit 121 can record / write the reorder queue identification numbers (dependencies) of the source operands of the plurality of instructions shown in Table 1 to the source operand field, as shown in Table 1.

[0026] Table 1: One specific example of a dependency information table

[0027]

[0028] The reorder queue circuit 121 can issue the plurality of instructions shown in Table 1 to the execution circuit 122 in an out-of-order manner. The reorder queue circuit 121 can record the processing status of each instruction shown in Table 1 in a processing status table. The detailed structure of the processing status table can be determined according to the actual design. For example, Table 2 is a specific example of the processing status table. The processing status table shown in Table 2 includes an issue field, an execute field, an in-order field, and a reissue field. The instruction field shown in Table 2 is for the convenience of the reader, and the actual processing status table can not have the instruction field shown in Table 2. The issue field is used to record the issue status of the instruction, where "n" indicates that the instruction has not been issued to the execution circuit 122, and "y" indicates that the instruction has been issued to the execution circuit 122. The execute field is used to record the execution status of the instruction, where "n" indicates that the execution circuit 122 has not executed the instruction, and "y" indicates that the execution circuit 122 has executed the instruction. The in-order field is used to record the in-order status of the instruction, where "n" indicates that the execution order correctness of the instruction has not been confirmed, and "y" indicates that the execution order correctness of the instruction has been confirmed. The reissue field is used to record the reissue status of the instruction due to the occurrence of the load-store conflict.

[0029] Table 2: A specific example of a processing status table

[0030]

[0031] The example situation shown in Table 2 is that the store instructions st_mem(adr100) and st_mem(adr200) with reorder queue identification numbers "0" and "1" have not been issued to the execution circuit 122. After the store instructions st_mem(adr100) and st_mem(adr200) are issued to the execution circuit 122, the contents of the processing status table are as shown in Table 3. The embodiments shown in Tables 3-4 demonstrate Figure 2 One implementation example of the step S240 is shown. In this embodiment, the reorder queue circuit 121 can use the data of the dependency information table shown in Table 1 to search / retrieve the relevant instructions of the load instruction ld_mem(adr100) that has caused the load-store conflict from the plurality of previously issued issued instructions when the load-store conflict occurs. Then, the reorder queue circuit 121 can reissue / execute the conflicting instructions (the load instruction ld_mem(adr100) and its relevant instructions) to resolve the load-store conflict problem. In particular, when the currently issued store instruction ld_mem(adr100) causes a load-store conflict with the previously issued load instruction st_mem(adr100), the instructions unrelated to the load instruction ld_mem(adr100) are not reissued (re-executed).

[0032] Table 3: Table of processing status after emission of st_mem(adr100) and st_mem(adr200)

[0033]

[0034] The reordering queue circuit 121 can check whether the currently emitted store instruction st_mem(adr100), st_mem(adr200) and the previously emitted load instruction ld_mem(adr100), ld_mem(adr300) have a load-store conflict. In the example situation shown in Table 3, the currently emitted store instruction st_mem(adr100) has a load-store conflict with the previously emitted load instruction ld_mem(adr100). The reordering queue circuit 121 can record the load instruction ld_mem(adr100) that has the load-store conflict in the re-emit field of the table of processing status shown in Table 3 in order to be re-emitted. In the re-emit field shown in Table 3, "y" indicates that the instruction needs to be re-emitted. Accordingly, the reordering queue circuit 121 can change the contents of the emission field and the execution field of the load instruction ld_mem(adr100) that has the load-store conflict from "y" to "n", as shown in Table 3.

[0035] Based on the reorder queue identification number "2" of the load instruction ld_mem(adr100) that caused the load-store conflict, the reorder queue circuit 121 can search the dependency information table shown in Table 1 for the dependent instructions of the load instruction ld_mem(adr100). Since the operation instruction inst_4(#2) with the reorder queue identification number "4" uses the loaded data of the load instruction ld_mem(adr100) with the reorder queue identification number "2", the operation instruction inst_4(#2) is a dependent instruction of ld_mem(adr100). Since the operation instruction inst_11(#4, 5) with the reorder queue identification number "11" uses the operation result of the operation instruction inst_4(#2) with the reorder queue identification number "4", the operation instruction inst_11(#4, 5) is a dependent instruction of ld_mem(adr100). Since the operation instruction inst_12(#11) with the reorder queue identification number "12" uses the operation result of the operation instruction inst_11(#4, 5) with the reorder queue identification number "11", the operation instruction inst_12(#11) is a dependent instruction of ld_mem(adr100). Table 4 shows the content of the processing status table after searching the dependency information table. The reorder queue circuit 121 can record these dependent instructions found by searching the dependency information table in the reissue field of the processing status table for reissuing. In addition, the reorder queue circuit 121 can change the content of the issue field and the execution field of these dependent instructions inst_4(#2), inst_11(#4, 5), inst_12(#11) from "y" to "n", as shown in Table 4.

[0036] Table 4: Processing status table after searching the dependency information table

[0037]

[0038]

[0039] The above-described embodiments demonstrate Figure 2 However, the implementation of the step S240 shown in FIG. 2 should not be limited to the above-described embodiments. Figure 2 The implementation of the step S240 shown in FIG. 2 should not be limited to the above-described embodiments. Figure 2 The implementation of the step S240 shown in FIG. 2 can be determined according to actual design. For example, the following will illustrate Figure 2Another implementation example of step S240 is shown. In the following example, in addition to the dependency information table shown in Table 1 and the processing state table shown in Table 2, the reorder queue circuit 121 can be configured with a speculate hazard ID table. For example, Table 5 is one specific example of a speculate hazard ID table. The instruction fields shown in Table 5 are for the convenience of the reader, and an actual speculate hazard ID table can not have the instruction fields shown in Table 5. The speculate hazard ID table shown in Table 5 includes a plurality of speculate hazard ID fields, such as speculate hazard IDs "0", "1", "2", "3", "4", "5", and "6" shown in Table 5. The number of speculate hazard ID fields can be determined according to the actual design.

[0040] Table 5: One specific example of a speculate hazard ID table

[0041]

[0042] In the speculate hazard ID fields shown in Table 5, "y" means "this instruction has been assigned / inherited this speculate hazard ID". During the process of issuing different instructions, the reorder queue circuit 121 can cause a currently issued instruction to be selectively assigned / inherited with a speculate hazard ID based on the dependency between the currently issued instruction and a previously issued instruction, and record the dependency between the currently issued instruction and the speculate hazard ID in the speculate hazard ID table. Please refer to both Table 2 and Table 5. The example situation shown in Table 2 and Table 5 is that the instructions with reorder queue IDs "0", "1", "14", and "15" have not been issued to the execution circuit 122, and the instructions with reorder queue IDs "2" to "13" have been issued to the execution circuit 122. During the process of issuing the instructions with reorder queue IDs "2" to "13", the reorder queue circuit 121 can cause these instructions to be selectively assigned / inherited with a speculate hazard ID, and record the dependency between these instructions and the speculate hazard ID in the speculate hazard ID table shown in Table 5.

[0043] For example, as shown in Table 5, the reorder queue circuit 121 can assign the speculative risk identification number "0" to the issued load instruction ld_mem(adr 100), and assign the speculative risk identification number "1" to the issued load instruction ld_mem(adr 300). In a case where the source operand of the instruction inst_4(#2) is the loaded data of the load instruction ld_mem(adr 100), the reorder queue circuit 121 can cause the instruction inst_4(#2) to inherit the speculative risk identification number "0" of the load instruction ld_mem(adr 100). In a case where the source operands of the instructions inst_5(#3) and inst_10(#3) are the loaded data of the load instruction ld_mem(adr 300), the reorder queue circuit 121 can cause the instructions inst_5(#3) and inst_10(#3) to inherit the speculative risk identification number "1" of the load instruction ld_mem(adr 300). In a case where the source operand of the instruction inst_13(#10) is the result data (operation result) of the instruction inst_10(#3), the reorder queue circuit 121 can cause the instruction inst_13(#10) to inherit the speculative risk identification number "1" of the instruction inst_10(#3). In a case where the first source operand of the instruction inst_11(#4,5) is the result data (operation result) of the instruction inst_4(#2) and the second source operand of the instruction inst_11(#4,5) is the result data (operation result) of the instruction inst_5(#3), the reorder queue circuit 121 can cause the instruction inst_11(#4,5) to inherit the speculative risk identification number "0" of the instructions inst_4(#2) and ld_mem(adr 100) and the speculative risk identification number "1" of the instructions inst_5(#3) and ld_mem(adr 300).

[0044] The contents of the processing status table and the speculation risk identification number table after the store instruction st_mem(adr 100) and the store instruction st_mem(adr 200) are issued to the execution circuit 122 are shown in Table 4 and Table 6, respectively. In the case that the load instruction ld_mem(adr 100) causes a load-store conflict, the reordering queue circuit 121 can record all the instructions with the speculation risk identification number "0" in the reissue field of the processing status table at one time (in one cycle) for reissuing. Then, the reordering queue circuit 121 can reissue / execute the conflicting instructions (the load instruction ld_mem(adr 100) and its related instructions) to resolve the load-store conflict problem. In particular, when the currently issued store instruction ld_mem(adr 100) causes a load-store conflict with the previously issued load instruction st_mem(adr 100), the instructions unrelated to the load instruction ld_mem(adr 100) are not reissued (re-executed). After being recorded in the reissue field of the processing status table, all the speculation risk identification number "0" in the speculation risk identification number table can be cleared. In addition, because it is confirmed that the load instruction ld_mem(adr 300) does not cause a load-store conflict, all the speculation risk identification number "1" in the speculation risk identification number table can be cleared, as shown in Table 6.

[0045] Table 6: Speculation risk identification number table after st_mem(adr 100) and st_mem(adr 200) are issued

[0046]

[0047] In summary, in the case of a load-store conflict occurring in the load instruction ld_mem(adr100), the prior art re-issues (re-executes) the load instruction ld_mem(adr100) and all the issued instructions (e.g., the instructions ld_mem(adr300), inst_4(#2), inst_5(#3), inst_6, inst_7, inst_8, inst_9, inst_10(#3), inst_11(#4,5), inst_12(#11), and inst_13(#10)) that have been issued but not yet ordered. Re-issuing (re-executing) these instructions ld_mem(adr300), inst_5(#3), inst_6, inst_7, inst_8, inst_9, inst_10(#3), and inst_13(#10) that are not related to the load instruction ld_mem(adr100) is a waste of time and resources. In the present embodiment, the processing core 120 can retrieve one or more instructions from all the issued instructions that have been issued previously but not yet ordered as "conflicting instructions" (including the load instruction ld_mem(adr100) that causes the load-store conflict and the instructions inst_4(#2), inst_11(#4,5), and inst_12(#11) that are related to the load instruction ld_mem(adr100)) when the load-store conflict occurs, and then re-issue the "conflicting instructions" to resolve the load-store conflict. In particular, when the currently issued store instruction st_mem(adr100) causes a load-store conflict with the previously issued load instruction ld_mem(adr100), the instructions ld_mem(adr300), inst_5(#3), inst_6, inst_7, inst_8, inst_9, inst_10(#3), and inst_13(#10) that are not related to the load instruction ld_mem(adr100) are not re-issued (re-executed) to preserve the computational results of the instructions that do not need to be re-executed. Thus, the memory dependence management method can efficiently resolve the load-store conflict.

[0048] Finally, it should be noted that the above-described embodiments are merely intended to illustrate the technical solutions of the present application, not to limit the same. Even though the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still make modifications to the technical solutions described in the foregoing embodiments, or equivalently replace some or all of the technical features thereof; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory dependency management method of a computing device, the method comprising: The memory dependence management method comprises: checking whether a currently issued store instruction has a load-store conflict with a previously issued first load instruction; in the case that the currently issued store instruction has the load-store conflict with the previously issued first load instruction, retrieving at least one conflicting instruction dependent on the first load instruction from a plurality of previously issued instructions, wherein the at least one conflicting instruction comprises the first load instruction; and re-issuing the at least one conflicting instruction, wherein the operation of retrieving the at least one conflicting instruction dependent on the first load instruction from the plurality of previously issued instructions comprises: recording the first load instruction having the load-store conflict in a re-issue field of a processing state table for re-issuing; searching at least one related instruction dependent on the first load instruction from a dependency information table based on a re-order queue identification number of the first load instruction having the load-store conflict; and recording the at least one related instruction in the re-issue field of the processing state table for re-issuing, wherein the dependency information table comprises dependencies among a plurality of instructions, the dependency information table comprises the re-order queue identification number and a source operand field for recording a source operand of a re-order queue identification number of an instruction.

2. The memory dependence management method of claim 1, wherein, The load-store conflict is defined as a part or all of an address range of the currently issued store instruction overlapping a part or all of an address range of the previously issued first load instruction, and a re-order queue identification number of the store instruction is earlier than a re-order queue identification number of the first load instruction.

3. The memory dependence management method of claim 1, wherein, The at least one conflicting instruction further comprises at least one related instruction using loaded data of the first load instruction.

4. The memory dependence management method of claim 1, wherein, The memory dependence management method further comprises: filling dependencies among a plurality of instructions to a dependency information table by a re-order queue circuit of the computing device; issuing the plurality of instructions to an execution circuit of the computing device in an out-of-order manner by the re-order queue circuit; and recording a processing state of each of the plurality of instructions in a processing state table by the re-order queue circuit, wherein the processing state table comprises an issue field for recording an issue state of an instruction and a re-issue field for recording a re-issue state of an instruction caused by the load-store conflict.

5. The memory dependence management method of claim 4, wherein, The processing state table further comprises an execution field for recording an execution state of an instruction and an in-order field for recording an in-order state of an instruction.

6. The memory dependence management method of claim 1, wherein, The operation of retrieving the at least one conflicting instruction dependent on the first load instruction from the plurality of previously issued instructions comprises: allocating a first speculation risk identification number for the first load instruction being issued, inherited from the first load instruction in case a source operand of a first instruction of the plurality of issued instructions is loaded data of the first load instruction; and inherited from the first load instruction in case a source operand of a second instruction of the plurality of issued instructions is result data of the first instruction.

7. The memory dependence management method of claim 6, wherein, retrieving the at least one conflicting instruction dependent on the first load instruction from the plurality of previously issued instructions further comprises: allocating a second speculation risk identification number for a second issued load instruction; inherited from the second load instruction in case a source operand of a third instruction of the plurality of issued instructions is loaded data of the second load instruction; and inherited from the first load instruction in case a first source operand of a fourth instruction of the plurality of issued instructions is the result data of the first instruction and a second source operand of the fourth instruction is result data of the third instruction.

8. The memory dependence management method of claim 6, wherein, retrieving the at least one conflicting instruction dependent on the first load instruction from the plurality of previously issued instructions further comprises: in case the load store conflict occurs for the first load instruction, recording all instructions having the first speculation risk identification number in a reissue field of a processing state table for reissuing. 9.A machine readable storage medium for storing non-transitory machine readable instructions that, when executed by a computer, implement the memory dependence management method of any one of claims 1-8.

10. A computing device, comprising: The computing device comprises: a memory; and a core coupled to the memory, wherein the core checks whether a currently issued store instruction has a load store conflict with a previously issued first load instruction, wherein the store instruction is to store data to the memory and the first load instruction is to fetch data from the memory; in case the currently issued store instruction has the load store conflict with the previously issued first load instruction, the core retrieves at least one conflicting instruction dependent on the first load instruction from a plurality of previously issued instructions, wherein the at least one conflicting instruction comprises the first load instruction; and the core reissues the at least one conflicting instruction, wherein retrieving the at least one conflicting instruction dependent on the first load instruction from the plurality of previously issued instructions comprises: recording the first load instruction having the load store conflict in a reissue field of a processing state table for reissuing; and recording the at least one conflicting instruction in the reissue field of the processing state table for reissuing. identify at least one dependent instruction dependent on the first load instruction from a dependency table based on a reorder queue identification number of the first load instruction that caused the load-store conflict; and record the at least one dependent instruction in the reissue field of the processing state table for reissue, wherein the dependency table comprises dependencies among a plurality of instructions, the dependency table comprising the reorder queue identification number and a source operand field to record a source operand of an instruction with the reorder queue identification number of the source operand.

11. The computing device of claim 10, wherein, The load-store conflict is defined as a part or all of an access address range of a currently issued store instruction overlapping a part or all of an access address range of a previously issued first load instruction, and a reorder queue identification number of the store instruction being earlier than a reorder queue identification number of the first load instruction.

12. The computing device of claim 10, wherein, The at least one dependent instruction further comprises at least one dependent instruction that uses loaded data of the first load instruction.

13. The computing device of claim 10, wherein, The execution core comprises: an execution circuit; and a reorder queue circuit to fill dependencies among a plurality of instructions to a dependency table, wherein the reorder queue circuit issues the plurality of instructions to the execution circuit in an out-of-order manner, the reorder queue circuit records a processing state of each of the plurality of instructions in a processing state table, the processing state table comprising an issue field to record an issue state of an instruction and a reissue field to record a reissue state of an instruction caused by the load-store conflict.

14. The computing device of claim 13, wherein, The processing state table further comprises an execute field to record an execute state of an instruction and an in-order field to record an in-order state of an instruction.

15. The computing device of claim 10, wherein: the reorder queue circuit assigns a first speculation risk identification number to the first load instruction that has been issued; the reorder queue circuit causes a first instruction among the plurality of issued instructions to inherit the first speculation risk identification number of the first load instruction if a source operand of the first instruction is loaded data of the first load instruction; and the reorder queue circuit causes a second instruction among the plurality of issued instructions to inherit the first speculation risk identification number of the first instruction if a source operand of the second instruction is result data of the first instruction.

16. The computing device of claim 15, wherein: the reorder queue circuit assigns a second speculation risk identification number to a second load instruction that has been issued; the reorder queue circuit causes a third instruction among the plurality of issued instructions to inherit the second speculation risk identification number of the second load instruction if a source operand of the third instruction is loaded data of the second load instruction; and the reorder queue circuit causes a fourth instruction among the plurality of issued instructions to inherit the second speculation risk identification number of the second instruction if a source operand of the fourth instruction is result data of the third instruction. ​ In a case where a first source operand of a fourth instruction of the plurality of issued instructions is the result data of the first instruction and a second source operand of the fourth instruction is result data of the third instruction, the reorder queue circuitry causes the fourth instruction to inherit the first speculation risk identification number of the first instruction and the second speculation risk identification number of the third instruction.

17. The computing device of claim 15, wherein, In a case where the first load instruction causes the load-store conflict, the reorder queue circuitry records all instructions having the first speculation risk identification number in a reissue field of a processing state table for reissuing.

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