Preparation Method of Array Substrate, Array Substrate and Display Panel

Abstract

The present application relates to the technical field of display panels. The present application discloses a method for manufacturing an array substrate, the array substrate, and a display panel. The method includes successively forming a gate metal layer, a gate insulating layer, and a first semiconductor layer on a substrate. It is characterized in that the manufacturing method further includes the steps of: forming a photoresist layer on the first semiconductor layer, exposing and developing the photoresist layer through a mask to form a patterned photoresist layer, the patterned photoresist layer including a first photoresist layer module and a second photoresist layer module, successively forming a second semiconductor layer and a second metal layer, completely removing the first photoresist layer module, and retaining a part of the thickness of the second photoresist layer module as a buffer module to pattern the second semiconductor layer and the second metal layer, etching the patterned first semiconductor layer to form a first channel and a second channel. Compared with the prior art, the number of etching times is reduced, the processing process is simplified, the uniformity of the panel characteristics after etching is improved, and the quality of the panel is effectively improved.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and particularly to a method for manufacturing an array substrate, an array substrate, and a display panel. Background Art

[0002] A thin film transistor liquid crystal display (TFT-LCD) is formed by an array glass substrate (Array), a color filter glass substrate (CF), and a cell formed by the two. A conventional array substrate includes a gate signal line (GE) or a first metal layer (M1) (GE or M1), a gate insulating layer (GI), an amorphous silicon semiconductor layer (a-Si), a source / drain or a second metal layer (SD or M2), a passivation layer (PV), and a transparent electrode (ITO) formed on a substrate. The 4-mask process is often used to manufacture the array substrate, and the amorphous silicon semiconductor layer (a-Si layer) and the source / drain layer (SD layer) are combined into one layer. In the process of manufacturing a conventional array substrate, etching is often used to form the required patterned film layers. Except for the gate insulating layer (GI) that does not require patterning, other layers need to use a mask to form patterned film layers through a yellow light process. Due to the need for multiple etching processes, it is easy to cause poor uniformity of panel characteristics. Especially for larger-size products nowadays, problems with abnormal panel quality are more likely to occur. Summary of the Invention

[0003] In order to solve the technical problems of a large number of etching times and high control difficulty of the array substrate, the main purpose of the present application is to provide a method for manufacturing an array substrate, an array substrate, and a display panel that can reduce the number of etching times and simplify the process.

[0004] To achieve the above-mentioned invention purpose, the present application adopts the following technical solutions:

[0005] According to one aspect of the present application, there is provided a method for manufacturing an array substrate, including sequentially forming a gate metal layer, a gate insulating layer, and a first semiconductor layer on a substrate; the manufacturing method further includes the steps of:

[0006] Forming a photoresist layer on the first semiconductor layer;

[0007] Exposing and developing the photoresist layer through a mask to form a first photoresist layer module and a second photoresist layer module on the first semiconductor layer. There is an opening in contact with the first semiconductor layer between the first photoresist layer module and the second photoresist layer module, and the thickness of the second photoresist layer module is greater than that of the first photoresist layer module;

[0008] Sequentially forming a second semiconductor layer and a second metal layer;

[0009] Completely remove the first glue layer module, expose the first semiconductor layer corresponding to the first glue layer module, and retain a part of the thickness of the second glue layer module as a buffer module to pattern the second semiconductor layer and the second metal layer;

[0010] Etch and pattern the first semiconductor layer to form a first channel in contact with the gate insulating layer. At the same time, remove the buffer module to form a second channel in contact with the first semiconductor layer between the second metal layer and the second semiconductor layer corresponding to the adjacent opening.

[0011] According to an embodiment of the present application, after exposing and developing the photoresist layer through a mask, the method further includes the steps of:

[0012] Plasma bombardment is performed to sputter inorganic particles outward from the first semiconductor layer to form a discontinuous shelter layer on the surfaces of the first glue layer module and the second glue layer module;

[0013] Etch the shelter layer to perform flocking treatment on the shelter layer to form a stripping cavity in contact with the first glue layer module and the second glue layer module;

[0014] Form a second semiconductor layer and a second metal layer in sequence;

[0015] Immerse the stripping liquid into the stripping cavity to contact the first glue layer module and the second glue layer module to completely remove the first glue layer module, and retain a part of the thickness of the second glue layer module as the buffer module to pattern the second semiconductor layer and the second metal layer.

[0016] According to an embodiment of the present application, when etching the shelter layer to perform flocking on the shelter layer, after etching the shelter layer, a plurality of support columns are formed on the surface of the first glue layer module and the surface of the second glue layer module, and there is the stripping cavity between adjacent support columns.

[0017] According to an embodiment of the present application, wherein the thickness of the shelter layer is The height of the support column is The range of the maximum outer diameter of the support column is

[0018] According to an embodiment of the present application, wherein the stripping liquid is a mixed solution including amine-based basic organic substances and polar organic solvents, and the treatment time for stripping using the stripping liquid is 1S - 1200S.

[0019] According to an embodiment of the present application, the photoresist layer is exposed and developed through a mask. The mask is a semi-transmissive photomask. In the projection plane perpendicular to the substrate, the first photoresist layer module corresponds one-to-one with the secondary light-transmissive area of the mask, the second photoresist layer module corresponds one-to-one with the fully blocked area of the mask, and the opening corresponds one-to-one with the fully light-transmissive area of the mask.

[0020] According to an embodiment of the present application, the thickness of the first photoresist layer module is D1, and the thickness of the second photoresist layer module is D2, where and

[0021] According to an embodiment of the present application, the thickness of the buffer module is D3, and

[0022] According to another aspect of the present application, there is provided an array substrate, including:

[0023] A device structure prepared by the preparation method of the array substrate;

[0024] A passivation layer and a pixel electrode layer formed in sequence on the device structure.

[0025] According to another aspect of the present application, there is provided a display panel, including:

[0026] The above-mentioned array substrate;

[0027] A color filter substrate disposed in a cell arrangement with the array substrate;

[0028] A liquid crystal layer disposed between the array substrate and the color filter substrate.

[0029] It can be seen from the above technical solutions that the advantages and positive effects of a preparation method of an array substrate, an array substrate, and a display panel according to the present application are as follows:

[0030] By forming a photoresist layer on the first semiconductor, after exposing and developing the photoresist layer, the first layer module and the second photoresist layer module are retained, and an opening in contact with the first semiconductor layer is formed. Then, the second semiconductor layer and the second metal layer are sequentially formed. At the opening position, the second semiconductor layer contacts the first semiconductor layer. After completely removing the first photoresist layer module, the first semiconductor layer corresponding to the first photoresist layer module is exposed, and a part of the second photoresist layer module with a certain thickness is retained as a buffer module to pattern the second semiconductor layer and the second metal layer. After that, the first semiconductor layer is patterned through an etching process. At the position not covered by the buffer module, a first channel in contact with the gate insulating layer is formed. After etching and removing the buffer module, a second channel in contact with the first semiconductor layer is formed between the second metal layer and the second semiconductor layer corresponding to adjacent openings. Furthermore, through the preparation method of the present application, compared with the prior art, when patterning the second metal layer and the second semiconductor layer, there is no need for an etching process, reducing the number of etching times, simplifying the processing technology, improving the uniformity of the display panel characteristics, and effectively improving the quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application and used together with the specification to explain the principles of the present application.

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0033] Figure 1 It is a schematic flowchart of a preparation method of an array substrate according to an embodiment provided by an embodiment of the present application;

[0034] Figure 2 It is a schematic flowchart of a preparation method of an array substrate according to another embodiment provided by an embodiment of the present application;

[0035] Figure 3 It is a schematic cross-sectional structure diagram of an array substrate for forming a first semiconductor layer in a preparation method of an array substrate according to an embodiment provided by an embodiment of the present application;

[0036] Figure 4 It is a schematic cross-sectional structure diagram of an array substrate for forming a photoresist layer in a preparation method of an array substrate according to an embodiment provided by an embodiment of the present application;

[0037] Figure 5Schematic cross-sectional structure diagram of an array substrate during exposure of a photoresist layer in a method for manufacturing an array substrate provided by an embodiment of the present application;

[0038] Figure 6 Schematic cross-sectional structure diagram of an array substrate during development of a photoresist layer in a method for manufacturing an array substrate provided by an embodiment of the present application;

[0039] Figure 7 Schematic cross-sectional structure diagram of an array substrate after texturing treatment in a method for manufacturing an array substrate provided by an embodiment of the present application;

[0040] Figure 8 Schematic cross-sectional structure diagram of a first glue layer module (second glue layer module) after texturing treatment in a method for manufacturing an array substrate provided by an embodiment of the present application;

[0041] Figure 9 Schematic cross-sectional structure diagram of an array substrate after forming a second semiconductor layer in a method for manufacturing an array substrate provided by an embodiment of the present application;

[0042] Figure 10 Schematic cross-sectional structure diagram of an array substrate after forming a second metal layer in a method for manufacturing an array substrate provided by an embodiment of the present application;

[0043] Figure 11 Schematic cross-sectional structure diagram of an array substrate when completely removing the first glue layer module and forming a buffer module in a method for manufacturing an array substrate provided by an embodiment of the present application;

[0044] Figure 12 Schematic cross-sectional structure diagram of an array substrate after etching and patterning a first semiconductor layer in a method for manufacturing an array substrate provided by an embodiment of the present application;

[0045] Figure 13 Flow schematic diagram of a method for manufacturing an array substrate according to another embodiment provided by an embodiment of the present application.

[0046] Wherein:

[0047] 10. Substrate; 20. Gate metal layer; 30. Gate insulating layer; 40. First semiconductor layer;

[0048] 50. Photoresist layer; 51. First glue layer module; 52. Second glue layer module; 53. Opening; 54. Buffer module;

[0049] 60. Second semiconductor layer; 70. Second metal layer; 80. First channel; 90. Second channel; 100. Mask; 1. Bunker layer; 2. Stripping chamber; 3. Support pillar. Detailed implementation manners

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0051] In the prior art, during the preparation process of an array substrate, at least 4 etching processes are required to pattern the gate signal line (GE) or the first metal layer (M1) (GE or M1), amorphous silicon semiconductor layer (a-Si), source / drain or second metal layer (SD or M2), passivation layer (PV), and transparent electrode (ITO). Due to the high difficulty in controlling the etching process, after multiple etching processes, non-uniformity issues in the process characteristics of the formed display panel will occur. To solve the technical problems of a large number of etching processes for the array substrate and high difficulty in controlling the etching uniformity, the main objective of the present application is to provide a method for preparing an array substrate and an array substrate that can reduce the number of etching processes and improve the etching uniformity.

[0052] To achieve the above-mentioned invention objective, the present application adopts the following technical solutions:

[0053] According to one aspect of the present application, there is provided a method for preparing an array substrate, including:

[0054] S10: sequentially form a gate metal layer 20, a gate insulating layer 30, and a first semiconductor layer 40 on a substrate 10;

[0055] In one embodiment of the present application, a first metal layer is formed on a glass substrate 10 by physical vapor deposition (PVD), and then a patterned positive photoresist layer 50 (PR) is formed through a first photomask by a yellow light process (Photo), where the Photo process includes a photoresist coating, exposure, and development process;

[0056] Then, the metal not covered by the PR is removed through a wet etching (Wet) process to form a patterned gate signal line (GE) and an array common electrode (A_Com), and finally, the PR layer is peeled off by a stripping solution. When the first metal layer is completed, its thickness is

[0057] After that, a layer of gate insulating layer 30 (GI) and a first semiconductor layer 40 (a-si) are formed by chemical vapor deposition (CVD), where the thickness of the GI layer is Its composition is silicon nitride or silicon oxide or a combined layer of silicon nitride and silicon oxide, and the thickness of the first semiconductor layer 40 (a-si) layer is Its component is amorphous silicon.

[0058] The preparation method further includes the steps:

[0059] S20: Form a photoresist layer 50 on the first semiconductor layer 40;

[0060] S30: Expose and develop the photoresist layer 50 through a mask plate 100 to form a first photoresist layer module 51 and a second photoresist layer module 52 on the first semiconductor layer 40. There is an opening 53 in contact with the first semiconductor layer 40 between the first photoresist layer module 51 and the second photoresist layer module 52, and the thickness of the second photoresist layer module 52 is greater than that of the first photoresist layer module 51;

[0061] S40: Sequentially form a second semiconductor layer 60 and a second metal layer 70;

[0062] S50: Completely remove the first photoresist layer module 51 to expose the corresponding first semiconductor layer 40 of the first photoresist layer module 51, and retain a part of the thickness of the second photoresist layer module 52 as a buffer module 54 to pattern the second semiconductor layer 60 and the second metal layer 70;

[0063] S60: Etch and pattern the first semiconductor layer 40 to form a first channel 80 in contact with the gate insulating layer 30, and at the same time remove the buffer module 54 to form a second channel 90 in contact with the first semiconductor layer 40 between the second metal layer 70 and the second semiconductor layer 60 corresponding to the adjacent opening 53.

[0064] Reference Figures 1 - 6 , by forming a thick photoresist layer 50 on the first semiconductor, after exposing and developing the photoresist layer 50, retaining the first photoresist layer module and the second photoresist layer module 52, and forming an opening 53 in contact with the first semiconductor layer 40, and then sequentially forming a thick second semiconductor layer 60 and a second metal layer 70. At the position of the opening 53, the second semiconductor layer 60 is in contact with the first semiconductor layer 40. The opening 53 can reserve a position for accommodating the formation of the second semiconductor layer 60 and the second metal layer 70, so that the second semiconductor layer 60 is in contact with the first semiconductor layer 40, and it is convenient to pattern the second semiconductor layer 60 and the second metal layer 70.

[0065] In step S30, according to an embodiment of the present application, the photoresist layer 50 is exposed and developed through the mask 100. The mask 100 is a semi-transmissive reticle. In the projection plane perpendicular to the substrate 10, the first photoresist layer module 51 corresponds one-to-one with the sub-transmissive area of the mask 100, the second photoresist layer module 52 corresponds one-to-one with the fully blocked area of the mask 100, and the opening 53 corresponds one-to-one with the fully transmissive area of the mask 100. Furthermore, the thickness of the second photoresist layer module 52 can be made greater than the thickness of the first photoresist layer module 51.

[0066] In an example of the present application, a semi-transmissive reticle (Half-Tone Mask: HTM) is used to perform a yellow light process (photo) to fabricate the patterned positive photoresist layer 50 (PR). Among them, all the PR at the position where the subsequent second metal layer 70 (SD) needs to be retained (equivalent to the position of the opening 53) is removed, and the PR at the position where the subsequent SD layer needs to be removed (equivalent to the first photoresist layer module 51 and the second photoresist layer module 52) is retained. Further, the PR at the position of the thin film transistor (TFT) channel (equivalent to the second photoresist layer module 52) is fabricated using the non-transmissive part of the HTM, and the other retained PR (equivalent to the first photoresist layer module 51) is fabricated using the semi-transmissive part of the HTM. Therefore, the PR at the TFT channel position will be thicker than the PR retained at other positions.

[0067] In the present application, the thickness of the retained PR at other positions (equivalent to the first photoresist layer module 51) is The thickness of the PR at the TFT channel (equivalent to the second photoresist layer module 52) is usually thicker than the PR at other positions (equivalent to the first photoresist layer module 51)

[0068] That is, the thickness of the first photoresist layer module 51 is D1, and the thickness of the second photoresist layer module 52 is D2, where And Furthermore, a buffer module 54 with sufficient thickness is reserved to form the second channel 90 in step S60.

[0069] Refer to Figure 12 , after developing the photoresist layer 50, the photoresist layer 50 at the position of the opening 53 is removed, and the thickness of the second photoresist layer module 52 is made greater than the thickness of the first photoresist layer module 51, so that after completely removing the first photoresist layer module 51, the second photoresist layer module 52 still has a remaining thickness to form a buffer module 54. Through the buffer module 54, it is convenient to form a second channel 90 in contact with the first semiconductor layer 40 between the second metal layer 70 and the second semiconductor layer 60 corresponding to the adjacent two openings 53 after etching.

[0070] Moreover, after the treatment in step S50, the first semiconductor layer 40 corresponding to the first glue layer module 51 is exposed, and a part of the second glue layer module 52 with a certain thickness is reserved as the buffer module 54 to pattern the second semiconductor layer 60 and the second metal layer 70. After that, through the etching treatment in step S60 to pattern the first semiconductor layer 40, at the position not covered by the buffer module 54, the first channel 80 in contact with the gate insulating layer 30 is formed. After etching and removing the buffer module 54, furthermore, through the preparation method of the present application, compared with the prior art, when patterning the second metal layer 70 and the second semiconductor layer 60, there is no need for etching process treatment, the number of etching times is reduced, the treatment process is simplified, the uniformity of the panel characteristics after multiple etching is improved, and the product quality is effectively improved.

[0071] Compared with the existing 4-mask process TFT-LCD array substrate, the present process reduces 2 Wet processes and simplifies 1 Dry process compared with the prior art. At the same time, like the existing 5-mask process, it can reduce one mask and one yellow light process. Due to the reduction of the etching process, the problem of uneven panel process characteristics caused by multiple etching processes can be effectively improved, and further, the product quality problems caused by uneven process characteristics can be improved, such as the problem of uneven panel color caused by uneven film thickness in the GI process, and the problem of electrical reliability caused by uneven channel length and tail length of the semiconductor layer.

[0072] Reference Figure 2 and Figure 7 and Figure 8 As shown, according to an embodiment of the present application, after exposing and developing the photoresist layer 50 through the mask 100, that is, after the treatment step S30, the following steps are further included:

[0073] S100: Plasma bombardment to sputter inorganic particles outward from the first semiconductor layer 40 and form a discontinuous shielding layer 1 on the surfaces of the first glue layer module 51 and the second glue layer module 52;

[0074] S200: Etch the shielding layer 1 to perform texturing treatment on the shielding layer 1 and form a stripping cavity 2 in contact with the first glue layer module 51 and the second glue layer module 52;

[0075] S300(S40): Reference Figure 9 and Figure 10 As shown, the second semiconductor layer 60 and the second metal layer 70 are sequentially formed; as an example, a boron-doped amorphous silicon layer (N+a-Si layer) with a thickness of is formed by chemical vapor deposition, and a second metal layer 70 (SD layer) with a thickness of

[0076] S400(S50): Reference Figure 11 As shown, immerse the stripping liquid into the stripping chamber 2 to contact the first adhesive layer module 51 and the second adhesive layer module 52, so as to completely remove the first adhesive layer module 51, and retain a part of the thickness of the second adhesive layer module 52 as the buffer module 54, so as to pattern the second semiconductor layer 60 and the second metal layer 70.

[0077] After the S30 step, through the S100 processing step, a discontinuous inorganic particle shielding layer 1 is formed on the surfaces of the first adhesive layer module 51 and the second adhesive layer module 52. The inorganic particles are formed by plasma bombardment of the first semiconductor layer 40 and sputtering of the inorganic particles of the first semiconductor layer 40, and the discontinuous inorganic particle shielding layer 1 is formed.

[0078] Referring to the figure, in an embodiment of the present application, argon inert gas plasma (Plasma) is used to bombard the first semiconductor layer 40 (a-Si layer) not covered by the photoresist layer 50 (PR), and amorphous silicon (a-Si) is sputtered and transferred to the surface of the PR, that is, the surfaces of the first adhesive layer module 51 and the second adhesive layer module 52, to form a discontinuous inorganic amorphous silicon layer shielding body, and the thickness of the inorganic a-Si layer shielding layer 1 is

[0079] In an embodiment of the present application, after the S200 step, a stripping chamber 2 is formed to facilitate the immersion of the stripping liquid into the stripping chamber 2 to contact the first adhesive layer module 51 and the second adhesive layer module 52 in the subsequent S400. Referring to Figure 11 As shown, the first adhesive layer module 51 is completely removed, and a part of the thickness of the second adhesive layer module 52 is retained as the buffer module 54 to pattern the second semiconductor layer 60 and the second metal layer 70. Furthermore, after patterning the second semiconductor layer 60 and the second metal layer 70, the S60 step is performed. Referring to Figure 12 As shown, the first semiconductor layer 40 is etched and patterned to form a first channel 80 in contact with the gate insulating layer 30, and at the same time, the buffer module 54 is removed, and a second channel 90 in contact with the first semiconductor layer 40 is formed between the second metal layer 70 and the second semiconductor layer 60 corresponding to the adjacent opening 53.

[0080] Furthermore, through this step, the patterning process of the second metal layer 70 and the second semiconductor layer 60 can be completed without etching. Compared with the existing 4-mask process, two etching processes are reduced, and on the basis of simplifying the preparation process, the problem of uneven characteristics of the display panel caused by the large etching control difficulty is avoided.

[0081] According to an embodiment of the present application, the masking layer 1 is etched to texture the masking layer 1. After the masking layer 1 is etched, a plurality of support pillars 3 are formed on the surfaces of the first glue layer module 51 and the second glue layer module 52, and a stripping cavity 2 is provided between adjacent support pillars 3. Refer to Figure 8 As shown, the volume of the stripping cavity 2 is increased by the support pillars 3 to prevent the stripping cavity 2 from being blocked when the second semiconductor layer 60 and the second metal layer 70 are formed, increase the contact area between the stripping liquid and the first glue layer module 51 and the second glue layer module 52, improve the stripping efficiency of step S400, and improve the stripping accuracy of the first glue layer module 51 and the second glue layer module 52.

[0082] According to an embodiment of the present application, the thickness of the masking layer 1 is The height of the support pillar 3 is The range of the maximum outer diameter of the support pillar 3 is To further increase the volume of the stripping cavity 2, increase the contact area between the stripping liquid and the first glue layer module 51 and the second glue layer module 52, improve the stripping efficiency of step S400, and improve the stripping accuracy of the first glue layer module 51 and the second glue layer module 52.

[0083] According to an embodiment of the present application, the stripping liquid is a mixed solution including amine-based basic organic substances and polar organic solvents, and the treatment time for stripping using the stripping liquid is 1S - 1200S.

[0084] In step S400, the first glue layer module 51 and the second glue layer module 52 are stripped using a stripping liquid. The main components of the stripping liquid are amine-based basic organic substances and polar organic solvents. Among them, the amine-based basic organic substances are such as amides or alkanolamines, etc., and their content ratio is 30% - 90%; among them, the polar organic solvents are such as dimethyl sulfoxide or diethylene glycol monobutyl ether, etc., and their content ratio is 10% - 70%. The stripping process time is 1S - 1200S.

[0085] Correspondingly, the second glue layer module 52 in the second channel 90 (TFT channel) has a thicker photoresist remaining compared to the first glue layer module 51 corresponding to the first channel 80. After the stripping process, the first glue layer module 51 is completely stripped, and there is still a residue in the second glue layer module 52 in the second channel 90, forming a buffer module 54. The thickness of the buffer module 54 is

[0086] After step S400, step S60 is performed. The first semiconductor layer 40 (a-Si layer) at the position not covered by metal (corresponding to the position of the first channel 80) is removed through a dry etching process. At the same time, the residual PR (equivalent to the buffer module 54) in the second channel 90 (TFT channel) and a small part of the first semiconductor layer 40 (a-Si layer) in the second channel 90 (TFT channel) are removed. Furthermore, through the above process, the second mask process is used to pattern the first semiconductor layer 40 (a-Si layer) and the second metal layer 70 high (SD layer).

[0087] Reference Figure 13 As shown, according to an embodiment of the present application, after etching and patterning the first semiconductor layer 40, the following steps are further included:

[0088] A passivation base layer is formed, and the passivation base layer is patterned through a mask 100 to form a passivation layer;

[0089] A pixel electrode base layer is formed, and the pixel electrode base layer is patterned through a mask 100 to form a pixel electrode layer.

[0090] In an embodiment of the present application, a passivation layer (Passivation: PV) is coated by chemical vapor deposition. The 3rd mask is used for the yellow light process to form a patterned positive photoresist layer 50 (PR). The Photo process includes photoresist coating, exposure, and development processes; then the passivation layer not covered by PR is removed through a dry etching (Dry) process to form a patterned passivation layer, which can protect the second metal layer 70 and thin film transistors. Finally, the PR layer is peeled off with a stripping solution. The passivation layer is composed of silicon nitride or silicon oxide or a combined layer of silicon nitride and silicon oxide, and its thickness is

[0091] The pixel electrode layer is coated by physical vapor deposition. The 4th mask is used for the yellow light process to form a patterned positive photoresist layer 50 (PR). The Photo process includes photoresist coating, exposure, and development processes; then the pixel electrode layer not covered by PR is removed through a wet etching (Wet) process to form a patterned pixel electrode layer, and finally the PR layer is peeled off with a stripping solution. The current industry uses indium tin oxide for the pixel electrode layer, which can also be replaced by other transparent conductive materials such as PEDOT:PSS or silver nanowires, etc., all within the scope of the present invention. The thickness of the pixel electrode layer is

[0092] Reference Figures 1 - 12As shown, the present application proposes an array substrate manufacturing method. Similar to the existing 4-mask process, the a-Si layer and the SD layer are combined into one mask for manufacturing. After the a-Si coating is completed, the required pattern is made using HTM. The organic photoresist layer 50 (PR) layer at the positions where the subsequent SD layer metal needs to be retained is pre-removed in the yellow light process. The PR is retained at the positions where the SD metal layer needs to be removed subsequently, and the semi-transmissive part of HTM is used for manufacturing. However, at the TFT channel positions, the non-transmissive part of HTM is used to retain the PR, and the thickness of this part of the PR is thicker than that of other positions.

[0093] After S100 and S200, the retained PR layer is subjected to texturing treatment by bombarding with plasma;

[0094] Then, in step S300, boron-doped (P) a-Si layer (N+a-Si) coating and the second metal layer 70 (SD) coating are carried out;

[0095] Then, in S400, the PR layer is stripped using a stripping solution. Since there is a layer of fluffy nano-columnar PR layer on the surface of the retained PR, the N+a-Si and SD layers deposited on the fluffy PR are discontinuous dense film layers (equivalent to the shielding layer 1). Therefore, the stripping solution can penetrate through the upper covering film layer to contact the PR, and strip the PR layer together with the N+a-Si and SD layers covering the upper layer of the PR.

[0096] Since the PR in the TFT channel (equivalent to the second channel 90) formed by HTM is thicker (the second photoresist layer module 52), after being stripped by the stripping solution, the PR retained at other positions (the first photoresist layer module 51) is stripped, while a certain thickness of PR (equivalent to the buffer module 54) still remains in the TFT channel. Finally, the a-Si layer at the part not covered by metal is removed through the dry etching process, and at the same time, the residual PR (equivalent to the buffer module 54) at the channel can be removed.

[0097] Through the 4-mask process of the manufacturing method described in the present invention, 2 Wet processes are reduced compared with the existing process, and one Dry process is simplified. At the same time, like the existing 5-mask process, one mask can be reduced and one yellow light process can be reduced. Due to the reduction of the etching process, the problem of uneven panel manufacturing process characteristics caused by multiple etching processes can be effectively improved, and further, the product quality problems caused by uneven process characteristics can be improved, such as the problem of uneven panel color caused by uneven film thickness in the GI process, and the problem of electrical reliability caused by uneven channel length and uneven trailing length of the semiconductor layer.

[0098] According to another aspect of the present application, an array substrate is provided, including:

[0099] A device structure prepared by the preparation method of the array substrate;

[0100] A passivation layer and a pixel electrode layer formed sequentially on the device structure.

[0101] According to another aspect of the present application, a display panel is provided, including:

[0102] The aforementioned array substrate;

[0103] A color filter substrate, arranged in a facing manner with the array substrate;

[0104] A liquid crystal layer, arranged between the array substrate and the color filter substrate.

[0105] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including the said element.

[0106] The above are only specific embodiments of the present application, enabling those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but will conform to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for preparing an array substrate, comprising sequentially forming a gate metal layer (20), a gate insulating layer (30), and a first semiconductor layer (40) on a substrate (10); characterized in that, The preparation method further includes the steps of: forming a photoresist layer (50) on the first semiconductor layer (40); exposing and developing the photoresist layer (50) through a mask (100) to form a first photoresist layer module (51) and a second photoresist layer module (52) on the first semiconductor layer (40). There is an opening (53) in contact with the first semiconductor layer (40) between the first photoresist layer module (51) and the second photoresist layer module (52), and the thickness of the second photoresist layer module (52) is greater than that of the first photoresist layer module (51); successively forming a second semiconductor layer (60) and a second metal layer (70); completely removing the first photoresist layer module (51) to expose the corresponding first semiconductor layer (40) of the first photoresist layer module (51), and retaining a part of the thickness of the second photoresist layer module (52) as a buffer module (54) to pattern the second semiconductor layer (60) and the second metal layer (70); etching and patterning the first semiconductor layer (40) to form a first channel (80) in contact with the gate insulating layer (30), and at the same time removing the buffer module (54) to form a second channel (90) in contact with the first semiconductor layer (40) between the second metal layer (70) and the second semiconductor layer (60) corresponding to the adjacent opening (53).

2. The manufacturing method of the array substrate according to claim 1, wherein, After exposing and developing the photoresist layer (50) through the mask (100), it further includes the steps of: plasma bombardment to cause the first semiconductor layer (40) to sputter inorganic particles outward and form a discontinuous shelter layer (1) on the surfaces of the first photoresist layer module (51) and the second photoresist layer module (52); etching the shelter layer (1) to perform texturing treatment on the shelter layer (1) to form a stripping cavity (2) in contact with the first photoresist layer module (51) and the second photoresist layer module (52); successively forming a second semiconductor layer (60) and a second metal layer (70); immersing a stripping solution into the stripping cavity (2) to contact the first photoresist layer module (51) and the second photoresist layer module (52) to completely remove the first photoresist layer module (51), and retaining a part of the thickness of the second photoresist layer module (52) as the buffer module (54) to pattern the second semiconductor layer (60) and the second metal layer (70).

3. The manufacturing method of the array substrate according to claim 2, characterized in that, etching the shelter layer (1) to perform texturing on the shelter layer (1). After etching the shelter layer (1), a plurality of support columns (3) are formed on the surfaces of the first photoresist layer module (51) and the second photoresist layer module (52), and there is the stripping cavity (2) between adjacent support columns (3).

4. The method for preparing an array substrate according to claim 3, wherein The thickness of the bunker layer (1) is The height of the support column (3) is The range of the maximum outer diameter of the support column (3) is 5. The method for preparing an array substrate according to claim 2, wherein, The stripping solution is a mixed solution including amine-based basic organic substances and polar organic solvents, and the treatment time for stripping with the stripping solution is 1S - 1200S.

6. The manufacturing method of the array substrate according to claim 1, characterized in that, The photoresist layer (50) is exposed and developed through a mask (100), wherein the mask (100) is a semi-transmissive photomask. In the projection plane perpendicular to the substrate (10), the first photoresist layer module (51) corresponds to the secondary light-transmissive area of the mask (100) one by one, the second photoresist layer module (52) corresponds to the fully-occluding area of the mask (100) one by one, and the opening (53) corresponds to the fully light-transmissive area of the mask (100) one by one.

7. The manufacturing method of the array substrate according to claim 6, characterized in that, The thickness of the first adhesive layer module (51) is D1, and the thickness of the second adhesive layer module (52) is D2, where and 8. The method for manufacturing an array substrate according to claim 1, wherein, The thickness of the buffer module (54) is D3, and 9. An array substrate, characterized in that, Comprising: A device structure prepared by the method for preparing an array substrate according to any one of claims 1-8; A passivation layer and a pixel electrode layer sequentially formed on the device structure.

10. A display panel, characterized in that, Comprising: The array substrate according to claim 9; A color filter substrate disposed opposite to the array substrate; A liquid crystal layer disposed between the array substrate and the color filter substrate.

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