Multi-FPGA simulation verification cloud platform scheduling management method and system based on switching architecture

Abstract

The present invention discloses a multi-FPGA simulation verification cloud platform scheduling management method and system based on a switching architecture, including obtaining platform resource information, including FPGA location, interconnection relationship, port configuration, bandwidth configuration and FPGA internal resource information; allocating platform resources according to the resource requirements of user design to obtain user resource allocation; mapping the user design to the corresponding FPGA according to the user resource allocation, configuring the exchange-based communication port between the FPGAs allocated to the user to the communication bandwidth corresponding to the requirements by configuring a high-speed interconnection switching network, and configuring the bandwidth of the communication port between the FPGA allocated to the user and other FPGAs not allocated to the user to 0. The platform resources are scalable and the logical isolation between users is achieved, and the communication bandwidth between the ports is configured according to the communication requirements after the user design is mapped, and the bandwidth utilization rate of the high-speed interconnection switching network is optimized while meeting the user's requirements.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit microelectronics, and in particular to a multi-FPGA simulation verification cloud platform scheduling management method and system based on a switching architecture. Background Art

[0002] The traditional multi-FPGA hardware simulation platform is based on TDM (time division multiplexing) LVDS port interconnection, which is actually an end-to-end or point-to-point interconnection method, and the connection relationship between FPGAs is relatively fixed. This type of platform is not convenient for resource scheduling and management when performing cloud platform virtualization. When the user's design scale changes and a different number of FPGAs need to be applied for, the ports on the edge FPGA connected to the FPGA outside the allocated user resources will not be available, but these ports occupy the user's FPGA port resources, resulting in inevitable resource waste. One solution is for cloud staff to manually plug and unplug the connection cables of these ports and connect them to the FPGA resources that have been allocated to the user, which is actually a manual change of the FPGA network topology. This method is not realistic in cloud platform management.

[0003] To solve this problem, the present invention proposes a multi-FPGA simulation verification cloud platform scheduling management method based on a switching architecture. Summary of the invention

[0004] In view of the above technical problems, the present invention provides a multi-FPGA simulation verification cloud platform scheduling management method and system based on a switching architecture.

[0005] The technical solution adopted by the present invention to solve the technical problem is:

[0006] A multi-FPGA simulation verification cloud platform scheduling management method based on a switching architecture, the method comprising the following steps:

[0007] S100: Acquire platform resource information, wherein the platform resource information includes FPGA location, interconnection relationship, port configuration, bandwidth configuration, and FPGA internal resource information;

[0008] S200: Allocate platform resources according to the resource requirements designed by the user to obtain the user resource allocation situation;

[0009] S300: Map the user design to the corresponding FPGA according to the user resource allocation situation, configure the switch-based communication ports between the FPGAs allocated to the user to the communication bandwidth corresponding to the requirements by configuring the high-speed interconnection switching network, and configure the bandwidth of the communication port between the FPGA allocated to the user and other FPGAs not allocated to the user to 0.

[0010] Preferably, S200 includes:

[0011] S210: According to the resource requirements of the user design, the user design is comprehensively compiled, a netlist is output, and resource estimation of the user design is obtained according to the netlist;

[0012] S220: Evaluate the FPGA quantity and resources allocated to the user according to the resource estimation of the user design and the platform resource information to obtain the user resource allocation situation.

[0013] Preferably, configuring the switch-based communication ports between the FPGAs allocated to the user to the communication bandwidth corresponding to the requirements by configuring the high-speed interconnection switching network in S300 includes:

[0014] S310: Obtain a signal set mapped to a corresponding port, calculate the product of the frequency of the clock domain where each signal in the set is located, the signal bit width and the signal flip rate estimated by the user, obtain the communication bandwidth requirement of the signal, and calculate the sum of the communication bandwidth requirements of all signals in the set;

[0015] S320: configuring a high-speed interconnection switching network according to the sum of the communication bandwidth requirements of all signals in the set, and allocating communication bandwidth between FPGAs to users.

[0016] Multi-FPGA simulation verification cloud platform scheduling and management system based on switching architecture, including:

[0017] A platform resource information acquisition module is used to acquire platform resource information, wherein the platform resource information includes FPGA location, interconnection relationship, port configuration, bandwidth configuration and FPGA internal resource information;

[0018] The platform resource allocation module is used to allocate platform resource information according to the resource requirements of the user design and obtain the user resource allocation situation;

[0019] The mapping and configuration module is used to map the user design to the corresponding FPGA according to the user resource allocation situation, and configure the switch-based communication ports between the FPGAs allocated to the user to the communication bandwidth corresponding to the requirements by configuring the high-speed interconnection switching network, and configure the bandwidth of the communication port between the FPGA allocated to the user and other FPGAs not allocated to the user to 0.

[0020] The above-mentioned multi-FPGA simulation verification cloud platform scheduling management method and system based on switching architecture, in the switching-based FPGA hardware simulation cloud platform, realizes the scalability of platform resources and logical isolation between users by configuring a high-speed interconnected switching network, and configures the communication bandwidth between ports according to the communication requirements after user design mapping. While meeting user needs, it optimizes the bandwidth utilization of the high-speed interconnected switching network. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a flow chart of a multi-FPGA simulation verification cloud platform scheduling management method based on a switching architecture in one embodiment of the present invention;

[0022] Figure 2 It is a schematic diagram of the platform structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings.

[0024] In one embodiment, Figure 1 As shown, a multi-FPGA simulation verification cloud platform scheduling management method based on a switching architecture includes the following steps:

[0025] S100: Acquire platform resource information, wherein the platform resource information includes FPGA location, interconnection relationship, port configuration, bandwidth configuration and FPGA internal resource information.

[0026] Specifically, the management, scheduling and allocation of resources are performed through the management server. First, the platform resource information is obtained through the platform configuration information, including the FPGA location, interconnection relationship, port configuration, bandwidth configuration and FPGA internal resource information, among which the FPGA internal resource information includes LUT (Look-Up-Table), FF, DSP (arithmetic unit), IO, BRAM (storage resource BlockRAM) and so on in each FPGA.

[0027] S200: Allocate platform resource information according to the resource requirements designed by the user to obtain the user resource allocation situation.

[0028] In one embodiment, S200 includes:

[0029] S210: According to the resource requirements of the user design, the user design is comprehensively compiled, a netlist is output, and resource estimation of the user design is obtained according to the netlist;

[0030] S220: Evaluate the FPGA quantity and resources allocated to the user according to the resource estimation of the user design and the platform resource information to obtain the user resource allocation situation.

[0031] Specifically, according to the resource requirements of the user design, the available resources in the platform are allocated, mainly referring to the FPGA and its associated peripherals, communication ports and port bandwidth, etc.

[0032] After the user design is input, the user design is first compiled and the netlist is output to obtain the resource estimation of the user design, including the LUT, FF, DSP, I / O, BlockRAM, etc. used in the user design. Given the resources of each FPGA in the platform, the number of FPGAs allocated to the user is evaluated based on the user's design requirements. For a single FPGA, resource allocation can be achieved through FPGA resource virtualization technology. If resources allow, one FPGA can be allocated to multiple users at the same time.

[0033] S300: Map the user design to the corresponding FPGA according to the user resource allocation situation, configure the switch-based communication ports between the FPGAs allocated to the user to the communication bandwidth corresponding to the requirements by configuring the high-speed interconnection switching network, and configure the bandwidth of the communication port between the FPGA allocated to the user and other FPGAs not allocated to the user to 0.

[0034] Specifically, according to the user resource allocation, the communication bandwidth of the exchange-based communication port between the resources (FPGA) obtained by the user is retained or increased, and the bandwidth of the communication port between the resources (FPGA) obtained by the user and other FPGAs not allocated to the user is configured to 0, which is achieved by automatically configuring the switching network through software. The logical isolation of the designs between different users is achieved without affecting each other.

[0035] as follows Figure 2 As shown in the figure, it is an example of multiple users being isolated from each other through a high-speed interconnection switching network. Assume that the available resources of the cloud platform include multiple FPGAs of AH, of which ABC is allocated to user 1, FG is allocated to user 2, H is allocated to user 3, and DE is an unallocated resource. By configuring a high-speed interconnection switching network, ABC can be connected to each other, FG is connected to each other, and the FPGA resources of the three users are not connected. Although all FPGAs are physically connected through the high-speed interconnection switching network, the connectivity between each port can be controlled by configuring the high-speed interconnection switching network to achieve logical isolation between different user logics.

[0036] In one embodiment, configuring the switch-based communication ports between FPGAs allocated to the user to the communication bandwidth corresponding to the requirements by configuring the high-speed interconnection switch network in S300 includes:

[0037] S310: Obtain a signal set mapped to a corresponding port, calculate the product of the frequency of the clock domain where each signal in the set is located, the signal bit width and the signal flip rate estimated by the user, obtain the communication bandwidth requirement of the signal, and calculate the sum of the communication bandwidth requirements of all signals in the set;

[0038] S320: configuring a high-speed interconnection switching network according to the sum of the communication bandwidth requirements of all signals in the set, and allocating communication bandwidth between FPGAs to users.

[0039] Specifically, for a certain user, the partition mapping algorithm is completed to map the user design to the FPGA, and the communication bandwidth between FPGAs is adjusted according to the design requirements to achieve more efficient simulation. "Design requirements" refers to the signal communication bandwidth requirements between partition blocks (one partition block will be mapped to one FPGA) after partition mapping. This bandwidth is closely related to the user design and can be pre-evaluated by the user. It can be expressed as "the product of the clock frequency of the clock domain where the signal is located, the signal bit width and the user-estimated flip rate of the signal". The communication bandwidth is dynamically adjusted according to user requirements to optimize the bandwidth utilization of the high-speed interconnection switching network.

[0040] Still taking user 1 as an example, assume that user 1 is actually mapped to three FPGAs ABC, among which the logical connection between AB is closer, that is, the required communication bandwidth is higher, the required communication bandwidth is 80Gbps (assumed value), while the communication bandwidth between BC is relatively small, 20Gbps (assumed value), and there is no communication demand between AC. Assume that the maximum bandwidth between high-speed switching network ports is 50Gbps. At this time, the number of ports between AB is increased to 2 ports, and the bandwidth of each port is configured to 50Gbps. The total communication bandwidth between AB is 100Gbps, while the communication bandwidth between BC is configured to 25Gbps, and the communication bandwidth between AC is configured to 0.

[0041] The above-mentioned multi-FPGA simulation verification cloud platform scheduling management method based on switching architecture realizes dynamic expansion and dynamic adjustment of cloud platform resources and logical isolation between users through the configuration of high-speed interconnected switching network in the switching-based FPGA hardware simulation cloud platform; configures the communication bandwidth between ports according to the communication needs after user design mapping, and optimizes the bandwidth utilization of the high-speed interconnected switching network while meeting user needs.

[0042] Multi-FPGA simulation verification cloud platform scheduling and management system based on switching architecture, including:

[0043] A platform resource information acquisition module is used to acquire platform resource information, wherein the platform resource information includes FPGA location, interconnection relationship, port configuration, bandwidth configuration and FPGA internal resource information;

[0044] The platform resource allocation module is used to allocate platform resource information according to the resource requirements of the user design and obtain the user resource allocation situation;

[0045] The mapping and configuration module is used to map the user design to the corresponding FPGA according to the user resource allocation situation, and configure the switch-based communication ports between the FPGAs allocated to the user to the communication bandwidth corresponding to the requirements by configuring the high-speed interconnection switching network, and configure the bandwidth of the communication port between the FPGA allocated to the user and other FPGAs not allocated to the user to 0.

[0046] The specific limitations of the multi-FPGA simulation verification cloud platform scheduling and management system based on the switching architecture can refer to the multi-FPGA simulation verification cloud platform scheduling and management method based on the switching architecture, which will not be repeated here.

[0047] The above is a detailed introduction to the multi-FPGA simulation verification cloud platform scheduling management method and system based on the switching architecture provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A multi-FPGA simulation verification cloud platform scheduling management method based on a switching architecture, characterized in that: The method comprises the following steps: S100: Acquire platform resource information, wherein the platform resource information includes FPGA location, interconnection relationship, port configuration, bandwidth configuration and FPGA internal resource information; S200: Allocate platform resources according to the resource requirements designed by the user to obtain the user resource allocation situation; S300: Mapping the user design to the corresponding FPGA according to the user resource allocation situation, configuring the switch-based communication ports between the FPGAs allocated to the user to the communication bandwidth corresponding to the requirement by configuring the high-speed interconnection switch network, and configuring the bandwidth of the communication ports between the FPGA allocated to the user and other FPGAs not allocated to the user to 0; S200 includes: S210: compiling the user design according to the resource requirements of the user design, outputting a netlist, and obtaining resource estimation of the user design according to the netlist; S220: Evaluate the number of FPGAs and resources allocated to the user according to the resource estimation of the user design and the platform resource information to obtain the user resource allocation situation; In S300, configuring the switching-based communication ports between the FPGAs allocated to the user to the communication bandwidth corresponding to the requirements by configuring the high-speed interconnection switching network includes: S310: Obtain a signal set mapped to a corresponding port, calculate the product of the frequency of the clock domain where each signal in the set is located, the signal bit width, and the signal flip rate estimated by the user, obtain the communication bandwidth requirement of the signal, and calculate the sum of the communication bandwidth requirements of all signals in the set; S320: configuring a high-speed interconnection switching network according to the sum of the communication bandwidth requirements of all signals in the set, and allocating communication bandwidth between FPGAs to users.

2. A multi-FPGA simulation verification cloud platform scheduling and management system based on a switching architecture, characterized in that: include: A platform resource information acquisition module, used to acquire platform resource information, wherein the platform resource information includes FPGA location, interconnection relationship, port configuration, bandwidth configuration and FPGA internal resource information; A platform resource allocation module is used to allocate the platform resource information according to the resource requirements of the user design, and obtain the user resource allocation situation; A mapping and configuration module for mapping the user design to the corresponding FPGA according to the user resource allocation, configuring the exchange-based communication ports between the FPGAs allocated to the user to the communication bandwidth corresponding to the requirements by configuring the high-speed interconnection switching network, and configuring the bandwidth of the communication ports between the FPGA allocated to the user and other FPGAs not allocated to the user to 0; The platform resource allocation module includes: compiling the user design according to the resource requirements of the user design, outputting a netlist, and obtaining a resource estimation of the user design according to the netlist; evaluating the number of FPGAs and resources allocated to the user according to the resource estimation of the user design and the platform resource information to obtain the user resource allocation; In the mapping and configuration module, configuring the switching-based communication ports between FPGAs allocated to the user to the communication bandwidth corresponding to the requirements by configuring the high-speed interconnection switching network includes: obtaining a signal set mapped to the corresponding port, calculating the product of the frequency, signal bit width and the signal flip rate estimated by the user in the clock domain where each signal in the set is located, the signal bit width and the signal flip rate estimated by the user, obtaining the communication bandwidth requirement of the signal, and calculating the sum of the communication bandwidth requirements of all signals in the set; configuring the high-speed interconnection switching network according to the sum of the communication bandwidth requirements of all signals in the set, and allocating the communication bandwidth between FPGAs to the user.

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