A mask optimization method and storage medium

Abstract

The present invention relates to the technical field of integrated circuit mask design, and in particular to a mask optimization method and storage medium. The mask optimization method of the present invention comprises the following steps: obtaining an initial chip design layout; obtaining a critical path graph of the initial chip design layout; interrupting the initial chip design layout; placing evaluation points on the interrupted design layout, and obtaining key evaluation points using the critical path graph and the evaluation point positions; and optimizing the mask by reducing the correction error of the key evaluation points. The present invention reduces the correction error of the critical path graph by reducing the correction error of the key evaluation points, so that the manufacturing error of the graph on the critical path is low and meets the circuit timing requirements, while for the graph on the non-critical path, part of its correction error can be sacrificed to ensure the chip yield. The present invention also provides a storage medium having the same beneficial effects as the above-mentioned mask optimization method.

Description

[Technical field]

[0001] The invention relates to the field of integrated circuit mask design, and in particular to a mask optimization method and a storage medium. [Background technology]

[0002] The chip production process can be divided into two major steps, design and manufacturing. In the design stage, the system requirements of the device will be clarified first, including the functions, performance requirements, physical dimensions and manufacturing processes that the device needs to achieve. The operating frequency is a major performance indicator of the chip, which determines the chip's data processing speed. Afterwards, based on the system function design, the unit model library and logic components are used to construct the functional logic design diagram of the device, and it is repeatedly simulated, verified and optimized, and then the logic design diagram is converted into the corresponding circuit design. After that, the physical design stage of the device is entered. This process is very complicated and time-consuming. It is necessary to use EDA (electronic design automation) tools to convert each component in the circuit design diagram (including transistors, resistors, capacitors, inductors, etc.) and the connections between them into the layout information required for circuit manufacturing, that is, a multi-layer circuit design layout represented by geometric figures. The obtained circuit design layout needs to meet the timing constraints between each component. The so-called circuit timing constraint is the time T required for a signal to go from one output terminal to another signal input terminal. actual Need to be less than the given time requirement T required , the difference T slack ≡T required -T actual is called relaxation time. Under a given circuit design layout, T actual Generally, it can be calculated by static timing analysis methods. Physical design requires that under a given limited physical size, while meeting the design rule constraints required by process manufacturing, millions of timing constraints in the device are met, that is, all relaxation times T slack are all positive numbers, and a certain design margin is reserved to ensure the quality of chip manufacturing. This often requires repeated iterations to adjust the layout, which requires a long design cycle. Even so, it is often not possible to make all T slack Get enough margin. For signal transmission T slack The path with a small margin is called the critical path, which determines whether the entire chip can work properly at a given operating frequency. When entering the chip manufacturing stage, the mask optimization will be performed on each circuit board layer of the chip. The purpose is to make the chip manufacturing graphics close to the design layout, while obtaining the largest possible manufacturing process window, that is, to reduce the sensitivity of the chip manufacturing results to the exposure dose, focus deviation and mask manufacturing errors, and improve the chip yield. From the above design process analysis, it can be seen that not all graphics have the same impact on chip performance. For T slackThe graphics on the larger path have larger allowable manufacturing deviations, and for T slack The patterns on the smaller paths (critical paths) have smaller allowable manufacturing deviations.

[0003] In the currently disclosed technologies, mask optimization in chip design and manufacturing processes are two relatively independent processes. The design layout output by chip design is used as the input of mask optimization, and then indiscriminate mask optimization is performed to make the graphics obtained by manufacturing consistent with the chip design graphics. However, during the mask optimization process, each graphic affects each other, especially for graphics that are close to each other. Sometimes it is very difficult to obtain a small correction error for adjacent graphics. Engineers often reduce the correction error requirements for some graphics that are close to each other based on experience. However, this does not necessarily fully meet the chip performance requirements, thereby affecting the chip yield. [Summary of the invention]

[0004] In order to ensure chip yield, the present invention provides a mask optimization method and a storage medium.

[0005] The solution to the technical problem of the present invention is to provide a mask optimization method, comprising the following steps:

[0006] Obtain initial chip design layout;

[0007] Obtain critical path graphs for initial chip design layout;

[0008] Perform edge interruption on the initial chip design layout;

[0009] Place evaluation points on the interrupted design layout, and obtain key evaluation points using critical path graphs and evaluation point locations;

[0010] The mask is optimized by reducing the correction errors at key evaluation points.

[0011] Preferably, a relaxation time report of each signal transmission path on the initial chip design layout is obtained;

[0012] Screen critical paths based on relaxation time reports;

[0013] The graph on the critical path is output to obtain a critical path graph.

[0014] Preferably, the relaxation time report is obtained using a static timing analysis tool.

[0015] Preferably, the screening method for screening critical paths based on the relaxation time report is: preset a percentage value, and screen out paths with a preset percentage value as critical paths; or preset a relaxation time value, and screen out paths with a relaxation time less than the preset relaxation time value as critical paths.

[0016] Preferably, the initial chip design layout includes a plurality of design board layers, and all critical path graphics on each design board layer are output on the design board layer where the critical path graphics themselves are located.

[0017] Preferably, placing evaluation points on the interrupted design layout and obtaining key evaluation points using the critical path graph and the evaluation point positions comprises the following steps:

[0018] Place evaluation points on the interrupted edges;

[0019] Determine whether the interrupted edge is on the critical path graph. If the interrupted edge is on the critical path graph, the evaluation point on the interrupted edge is a critical evaluation point, otherwise it is a non-critical evaluation point.

[0020] Preferably, placing evaluation points on the interrupted edges comprises the following steps:

[0021] Get a broken edge;

[0022] Determine whether the previous edge and the next edge of the interrupted edge are both in the same straight line with the interrupted edge; if so, place an evaluation point on the interrupted edge; if not, find a circle tangent to the interrupted edge and the previous edge or the next edge that is not parallel to the interrupted edge within a preset radius, and place an evaluation point on the tangent circular arc segment.

[0023] Preferably, the correction error of the key evaluation point is reduced by increasing the weight of the key evaluation point to the error function.

[0024] Preferably, the error function is set to:

[0025] cost=∑ l c l (∑ i w i γ i ·(EPE l,i ) p )+cost(MRC)+cost(sidelobe)+etc.

[0026] Among them, l represents the lth process condition, c l is the weight of the process condition error on cost, i represents the i-th evaluation point, w i is the weight of the i-th point; EPE l,i is the edge placement error of the evaluation point at the lth process condition, p is an exponent; γ iIt is a coefficient related to whether the evaluation point is a critical evaluation point. If the evaluation point is a non-critical evaluation point, its value is 1. If the evaluation point is a critical evaluation point, its value is a value set by the user that is greater than 1; cost(MRC) is the quantitative representation of the line segments that violate the mask manufacturing rules in the cost; cost(sidelobe) is the representation of the contour formed by the sub-resolution auxiliary graphics in the cost; etc represents other error terms.

[0027] In order to solve the above technical problem, the present invention further provides a storage medium on which a computer program is stored. When the computer program is executed by a processor, the above mask optimization method is implemented.

[0028] Compared with the prior art, a mask optimization method and storage medium of the present invention have the following advantages:

[0029] 1. The mask optimization method of the present invention comprises the following steps: obtaining the initial chip design layout; obtaining the critical path graph of the initial chip design layout; interrupting the initial chip design layout; placing evaluation points on the interrupted design layout, obtaining the key evaluation points using the critical path graph and the evaluation point positions; optimizing the mask by reducing the correction error of the key evaluation points. The mask optimization method proposed by the present invention applies the critical path information obtained in the chip layout design process to the mask optimization process, and reduces the mask optimization correction error of the critical path graph by reducing the correction error of the key evaluation points, so that the manufacturing error of the graph on the critical path is low, meeting the circuit timing requirements, and for the graph on the non-critical path, part of its correction error can be sacrificed to ensure the chip yield. In addition, the mask optimization method of the present invention can also reduce the relaxation time margin requirements for physical design in the chip design process, speed up the design cycle, improve the degree of automation of mask optimization, reduce the need for human interference, improve the quality of mask optimization, reduce the manufacturing error of the critical path graph, and improve the chip manufacturing yield.

[0030] 2. The mask optimization method of the present invention includes the following steps to obtain the critical path graph of the initial chip design layout: obtain the relaxation time report of each signal transmission path on the initial chip design layout; filter the critical path based on the relaxation time report; and output the graph on the critical path to obtain the critical path graph. The relaxation time report is obtained using a static timing analysis tool. Static timing analysis does not require input vectors to exhaust all paths, runs very fast, occupies less memory, and can not only perform a comprehensive timing function check on the chip design, but also use the results of timing analysis to optimize the design.

[0031] 3. In the mask optimization method of the present invention, the screening method for critical paths based on relaxation time reports is: preset percentage value, and screen out the paths ranked in the front preset percentage value as critical paths; or, preset relaxation time value, and screen out the paths whose relaxation time is less than the preset relaxation time value as critical paths. Using different screening methods according to different needs is conducive to ensuring the accuracy of the screened critical paths.

[0032] 4. In the mask optimization method of the present invention, the initial chip design layout includes several design board layers, and all key path graphics on each design board layer are output on the design board layer where the key path graphics themselves are located, so as to facilitate the subsequent acquisition of key evaluation points of each design board layer and improve the optimization efficiency.

[0033] 5. In the mask optimization method of the present invention, evaluation points are placed on the interrupted design layout, and the key evaluation points are obtained by using the critical path graph and the evaluation point position, which includes the following steps: placing evaluation points on the interrupted edge; judging whether the interrupted edge is located on the critical path graph, if the interrupted edge is on the critical path graph, the evaluation point on the interrupted edge is a key evaluation point, otherwise it is a non-key evaluation point. By placing evaluation points on the interrupted edge, each evaluation point corresponds to an interrupted edge, and then only the evaluation point on the interrupted edge on the critical path graph is the key evaluation point, which is easy to implement, simple to operate, and efficient.

[0034] 6. In the mask optimization method of the present invention, the correction error of the key evaluation point is reduced by increasing the weight of the key evaluation point to the error function. It can be understood that the goal of mask optimization is to make the error function smaller and smaller. After increasing the weight of the key evaluation point, the error function must be small enough, which will reduce the weight of other evaluation points. Therefore, the mask optimization correction error of the key path graph is reduced, sacrificing part of the correction error of the non-key path graph, and the mask optimization error of the key path graph is reduced while meeting the circuit timing requirements, thereby improving the quality of mask optimization and ensuring the chip yield.

[0035] 7. The present invention also provides a storage medium, including a computer program, which implements the steps of the above mask method when executed by a processor. It has the same beneficial effects as the above mask optimization method, which will not be described in detail here.

Brief Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0037] Figure 1 It is a step flow chart of a mask optimization method provided by the first embodiment of the present invention.

[0038] Figure 2 This is an example of a mask optimization method provided by the first embodiment of the present invention. Figure 1 .

[0039] Figure 3 This is an example of a mask optimization method provided by the first embodiment of the present invention. Figure 2 .

[0040] Figure 4 This is an example of a mask optimization method provided by the first embodiment of the present invention. Figure 3 .

[0041] Figure 5 This is an example of a mask optimization method provided by the first embodiment of the present invention. Figure 4 .

[0042] Description of the accompanying drawings:

[0043] 1. Initial chip design layout; 2. First optimization result; 3. Second optimization result; 4. Comparison example area;

[0044] 10. Evaluation points; 11. Critical path diagram. [Specific implementation method]

[0045] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and implementation examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0046] See also Figure 1 A first embodiment of the present invention provides a mask optimization method, comprising the following steps:

[0047] S1. Obtain the initial chip design layout;

[0048] S2, obtaining a critical path graph of the initial chip design layout;

[0049] S3, edge interruption of the initial chip design layout;

[0050] S4, placing evaluation points on the interrupted design layout, and obtaining key evaluation points using the critical path graph and the evaluation point positions;

[0051] S5. Reduce the correction error of the key evaluation points to optimize the mask.

[0052] It can be understood that the present invention reduces the correction error of the critical path graph by reducing the correction error of the key evaluation point.

[0053] It can be understood that the critical path graph is a graph on the critical path. In the design stage of the chip, for the graph on the path with a larger relaxation time, the allowed manufacturing deviation is larger, while for the graph on the path with a smaller relaxation time, that is, the graph on the critical path, the allowed manufacturing deviation is small. Based on this, the present invention applies the critical path information obtained in the circuit design to the mask optimization process, focusing on reducing the correction error of the graph on the critical path of the circuit design, meeting the circuit timing requirements, and sacrificing part of the correction error of the graph on the non-critical path, thereby improving the production qualification rate of the chip. Without the need for engineers to operate subjectively based on experience, the degree of automation of mask optimization is also improved while improving the quality of mask optimization, reducing the need for human interference. In addition, the mask optimization method of the present invention can also reduce the relaxation time margin requirements for physical design in the chip design process, and speed up the design cycle.

[0054] It can be understood that the mask optimization method provided in the first embodiment of the present invention implements mask optimization by applying critical path information to conventional mask optimization methods in the art, and then reducing mask optimization correction errors of critical path graphics.

[0055] Furthermore, the specific steps of step S2 include:

[0056] S21, obtaining a relaxation time report of each signal transmission path on the initial chip design layout;

[0057] S22. Screening critical paths based on relaxation time reports;

[0058] S23. Output the graph on the critical path to obtain a critical path graph.

[0059] Specifically, in step S21 , a relaxation time report is obtained using a static timing analysis tool.

[0060] Furthermore, the method of screening the critical paths is: preset a percentage value (x%), and screen out the paths ranked in the top preset percentage value (top x%) as the critical paths; or preset a relaxation time value, and screen out the paths whose relaxation time is less than the preset relaxation time value as the critical paths.

[0061] It can be understood that different screening methods can be selected for different initial chip design layouts to ensure the accuracy of critical path screening; the preset percentage value or preset relaxation time value depends on the actual initial chip design layout.

[0062] It can be understood that the initial chip design layout is a multi-layer circuit design layout represented by geometric figures, so the initial chip design layout includes several design board layers. Since a certain critical path of the initial chip design layout usually spans multiple design board layers, that is, the circuit diagram of a certain critical path exists in multiple design board layers, therefore, in the mask optimization method provided in the first embodiment of the present invention, when screening critical paths, the critical paths on each design board layer are simultaneously screened to screen out all critical paths on the entire initial chip design layout. Specifically, the first embodiment of the present invention only describes the mask optimization method for one of the design board layers of the initial chip design layout, and the remaining design board layers are optimized using the same method.

[0063] Furthermore, in step S3 of interrupting the initial chip design layout, the critical path graph will not be interrupted.

[0064] Please combine Figure 2 and Figure 3 Furthermore, after filtering out the critical paths, the critical path graphics can be filtered out, and the filtered critical path graphics are stored in accordance with the layers they originally belonged to. That is, all the critical path graphics on each design board layer are output on the design board layer where the critical path graphics themselves are located. For example, all the critical path graphics on the first board layer are output on the first board layer, and all the critical path graphics on the second board layer are output on the second board layer. Therefore, for each design board layer of the initial chip design layout, the design graphics of the design board layer can be obtained (such as Figure 2 ) and the critical path graph on the design board layer (as shown Figure 3 As shown). It can be understood that the key path graph obtained on each design board layer is the graph on all the key paths on the design board layer.

[0065] For further information, see Figure 4 , Figure 4 is an example diagram of key evaluation points. The specific steps of step S4 include:

[0066] S41, placing evaluation point 10 on the interrupted edge;

[0067] S42, judging whether the interrupted edge is located on the critical path graph 11, if the interrupted edge is on the critical path graph 11, then the evaluation point 10 on the interrupted edge is a critical evaluation point, otherwise it is a non-critical evaluation point.

[0068] Understandably, Figure 4 The evaluation point 10 shown is on the critical path graph 11, therefore, Figure 4 The evaluation point 10 shown is a key evaluation point.

[0069] Furthermore, the specific steps of step S42 include:

[0070] S421, obtaining a broken edge;

[0071] S422, determine whether the previous edge and the next edge of the interrupted edge are both on the same straight line with the interrupted edge; if so, place an evaluation point on the interrupted edge; if not, find a circle tangent to the interrupted edge and the previous edge or the next edge that is non-parallel to the interrupted edge within a preset radius, and place an evaluation point on the tangent circular arc segment.

[0072] It can be understood that after the evaluation points are placed, each evaluation point corresponds to a broken edge.

[0073] Specifically, if the previous edge and the next edge of the interrupted edge are both on the same straight line as the interrupted edge, the evaluation point is generally placed on the center point of the interrupted edge.

[0074] Furthermore, the tangent circular arc segments in step S422 include circular arc segments tangent to the interrupted edge and circular arc segments tangent to the non-parallel previous edge or next edge. For example, if the previous edge of an interrupted edge is non-parallel to it, a circle tangent to the interrupted edge and the previous edge within a preset radius is found, and the evaluation point can be placed at the tangent point between the circle and the interrupted edge and the tangent point between the circle and the previous edge. It can be understood that if the next edge of an interrupted edge is non-parallel to it, a similar method is used to place the evaluation point.

[0075] Furthermore, the preset radius in step S422 is generally nanometer-sized, and the user defines the specific value according to actual needs.

[0076] It can be understood that the key evaluation points on each design board layer can be obtained simultaneously or layer by layer.

[0077] Furthermore, in the embodiment of the present invention, the correction error of the key evaluation point is reduced by increasing the weight of the key evaluation point to the error function.

[0078] It can be understood that the goal of mask optimization is to make the error function smaller and smaller. Therefore, when increasing the weight of the key evaluation point to the error function, in order to make the error function small enough, the weight of other non-critical evaluation points will be reduced. Therefore, the correction error of the critical path graph is reduced, sacrificing part of the correction error of the non-critical path graph, thereby reducing human interference and improving the quality of mask optimization.

[0079] Furthermore, the error function is composed of multiple error terms, and the optimization result can be adjusted by adjusting the proportion of each error term to the total error through the weight coefficient. The present invention reduces the correction error of the critical path graph by increasing the weight of the error placed at the key evaluation point to the error function cost function. Specifically, the error function is set as: cost = ∑ l c l (∑ i w i γ i ·(EPE l,i ) p )+cost(MRC)+cost(sidelobe)+etc., where l represents the lth process condition, c l is the weight of the process condition error on cost; i represents the i-th evaluation point, w i is the weight of the i-th point; EPE l,i is the edge placement error of the evaluation point under the lth process condition; γ i It is a coefficient related to whether the evaluation point is a critical evaluation point. If the evaluation point is not a critical evaluation point, its value is 1. If the evaluation point is a critical evaluation point, its value is a value set by the user that is greater than 1, such as 10; p is an exponent, such as the square. cost(MRC) is to quantitatively represent the line segments in the figure that violate the MRC (mask manufacturing rule) in the cost. If cost(MRC) is 0, it means that the figure meets the MRC rule. cost(sidelobe) is to represent the contour formed by the sub-resolution auxiliary graphics in the cost. It can be understood that sometimes other sub-resolution auxiliary graphics will be added to the mask optimization. These graphics will form contours after exposure. If a contour is formed, it is a sidelobe. We do not want this type of graphics to form a contour. Therefore, by adding cost(sidelobe) to the error function, it is to reduce the side lobe formed by the sub-resolution auxiliary graphics. etc represents other error terms, i.e. other costs, such as pinch brige. For example, if the contours of some graphics are connected, but we do not want them to be connected, or if the contours of some graphics are disconnected, but we do not want them to be disconnected, we add cost (pinchbrige). It can be understood that other necessary error terms can be added to the error function according to actual needs.

[0080] It can be understood that by adjusting the parameters of the error function cost, the weight of the placement error at the key evaluation point to the error function can be changed. By increasing the weight of the placement error at the key evaluation point to the error function, the placement error at the key evaluation point in the final optimization result can be reduced, and the correction error of the key path graph can be reduced, which can improve the quality of mask optimization and the degree of automation of mask optimization, reduce the need for human intervention, and thus reduce the manufacturing error of the key path graph and improve the chip manufacturing yield.

[0081] It can be understood that, in addition to increasing the weight at the key evaluation point, other methods for reducing the correction error at the evaluation point can also be used to reduce the correction error at the key evaluation point.

[0082] For example, see Figure 5 , Figure 5 This is an example of the result of mask optimization. Figure 5 Demonstrating the initial chip design Figure 1 The first optimization result 2 and the second optimization result 3. It can be understood that the initial chip design version Figure 1 yes Figure 5 The first optimization result 2 is the mask optimization printout when the critical path graph is considered and the weight of the key evaluation point is increased by 50 times; the second optimization result 3 is the image printed by the mask optimization when the critical path graph is not considered. Obviously, the image printed by the first optimization result 2 is different from the initial chip design version. Figure 1 The closer, the better the optimization effect. Especially in Figure 5 In the comparative example area 4 shown, the correction error of the first optimization result 2 in the comparative example area 4 is reduced from 7.7nm to 0.2nm compared with the second optimization result 3, and the correction error of the first optimization result 2 is significantly reduced. Therefore, considering the critical path graph during mask optimization can greatly reduce the correction error. Lower correction errors help to obtain timing that is more consistent with the circuit design, which is particularly important for critical path graphs. In addition, lower correction errors also help to improve the quality of mask optimization, reduce the manufacturing errors of critical path graphs, and improve the manufacturing yield of chips.

[0083] Furthermore, the second embodiment of the present invention provides a storage medium having a computer program stored thereon, and the computer program, when executed by a processor, implements the mask optimization method provided by the first embodiment of the present invention. The storage medium provided by the second embodiment of the present invention has the same beneficial effects as the mask optimization method provided by the first embodiment of the present invention, and will not be described in detail herein.

[0084] It is understandable that, according to the embodiments disclosed in the present invention, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present invention include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part, and / or installed from a removable medium. When the computer program is executed by the central processing unit (CPU), the above functions defined in the method of the present application are executed. It should be noted that the computer-readable medium described in the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. Computer-readable storage media, for example, include but are not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection with one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, an apparatus or a device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in combination with an instruction execution system, an apparatus or a device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0085] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0086] In the embodiments provided by the present invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0087] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. Those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0088] In various embodiments of the present invention, it should be understood that the size of the serial numbers of the above-mentioned processes does not mean the necessary order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0089] The flow chart and block diagram in the accompanying drawings of the present invention illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which is determined based on the functions involved. It should be particularly noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs a specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0090] Compared with the prior art, a mask optimization method and storage medium of the present invention have the following advantages:

[0091] 1. The mask optimization method of the present invention comprises the following steps: obtaining the initial chip design layout; obtaining the critical path graph of the initial chip design layout; interrupting the initial chip design layout; placing evaluation points on the interrupted design layout, obtaining the key evaluation points using the critical path graph and the evaluation point positions; optimizing the mask by reducing the correction error of the key evaluation points. The mask optimization method proposed by the present invention applies the critical path information obtained in the chip layout design process to the mask optimization process, and reduces the mask optimization correction error of the critical path graph by reducing the correction error of the key evaluation points, so that the manufacturing error of the graph on the critical path is low, meeting the circuit timing requirements, and for the graph on the non-critical path, part of its correction error can be sacrificed to ensure the chip yield. In addition, the mask optimization method of the present invention can also reduce the relaxation time margin requirements for physical design in the chip design process, speed up the design cycle, improve the degree of automation of mask optimization, reduce the need for human interference, improve the quality of mask optimization, reduce the manufacturing error of the critical path graph, and improve the chip manufacturing yield.

[0092] 2. The mask optimization method of the present invention includes the following steps to obtain the critical path graph of the initial chip design layout: obtain the relaxation time report of each signal transmission path on the initial chip design layout; filter the critical path based on the relaxation time report; and output the graph on the critical path to obtain the critical path graph. The relaxation time report is obtained using a static timing analysis tool. Static timing analysis does not require input vectors to exhaust all paths, runs very fast, occupies less memory, and can not only perform a comprehensive timing function check on the chip design, but also use the results of timing analysis to optimize the design.

[0093] 3. In the mask optimization method of the present invention, the screening method for critical paths based on relaxation time reports is: preset percentage value, and screen out the paths ranked in the front preset percentage value as critical paths; or, preset relaxation time value, and screen out the paths whose relaxation time is less than the preset relaxation time value as critical paths. Using different screening methods according to different needs is conducive to ensuring the accuracy of the screened critical paths.

[0094] 4. In the mask optimization method of the present invention, the initial chip design layout includes several design board layers, and all key path graphics on each design board layer are output on the design board layer where the key path graphics themselves are located, so as to facilitate the subsequent acquisition of key evaluation points of each design board layer and improve the optimization efficiency.

[0095] 5. In the mask optimization method of the present invention, evaluation points are placed on the interrupted design layout, and the key evaluation points are obtained by using the critical path graph and the evaluation point position, which includes the following steps: placing evaluation points on the interrupted edge; judging whether the interrupted edge is located on the critical path graph, if the interrupted edge is on the critical path graph, the evaluation point on the interrupted edge is a key evaluation point, otherwise it is a non-key evaluation point. By placing evaluation points on the interrupted edge, each evaluation point corresponds to an interrupted edge, and then only the evaluation point on the interrupted edge on the critical path graph is the key evaluation point, which is easy to implement, simple to operate, and efficient.

[0096] 6. In the mask optimization method of the present invention, the correction error of the key evaluation point is reduced by increasing the weight of the key evaluation point to the error function. It can be understood that the goal of mask optimization is to make the error function smaller and smaller. After increasing the weight of the key evaluation point, the error function must be small enough, which will reduce the weight of other evaluation points. Therefore, the mask optimization correction error of the key path graph is reduced, sacrificing part of the correction error of the non-key path graph, and the mask optimization error of the key path graph is reduced while meeting the circuit timing requirements, thereby improving the quality of mask optimization and ensuring the chip yield.

[0097] 7. The present invention also provides a storage medium, including a computer program, which implements the steps of the above mask method when executed by a processor. It has the same beneficial effects as the above mask optimization method, which will not be described in detail here.

[0098] The above is a detailed introduction to a mask optimization method and storage medium disclosed in an embodiment of the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention. Any modifications, equivalent substitutions and improvements made within the principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A mask optimization method, characterized in that: The following steps are involved: Obtain initial chip design layout; Obtain critical path graphs for initial chip design layout; Perform edge interruption on the initial chip design layout; Place evaluation points on the interrupted edges; Determine whether the interrupted edge is on the critical path graph. If the interrupted edge is on the critical path graph, the evaluation point on the interrupted edge is a critical evaluation point, otherwise it is a non-critical evaluation point. The mask is optimized by increasing the weight of the key evaluation points on the error function to reduce the correction error of the key evaluation points.

2. The mask optimization method according to claim 1, characterized in that: Obtaining the critical path graph for the initial chip design layout includes the following steps: Obtain a relaxation time report for each signal transmission path on the initial chip design layout; Screen critical paths based on relaxation time reports; The graph on the critical path is output to obtain a critical path graph.

3. The mask optimization method according to claim 2, wherein: The relaxation time report is obtained using a static timing analysis tool.

4. The mask optimization method according to claim 2, wherein: The method of screening the critical path based on the relaxation time report is: preset percentage value, and select the path with the preset percentage value as the critical path; Alternatively, a relaxation time value is preset, and a path whose relaxation time is less than the preset relaxation time value is screened out as a critical path.

5. The mask optimization method according to claim 2, wherein: The initial chip design layout includes a plurality of design board layers, and all key path graphics on each design board layer are output on the design board layer where the key path graphics themselves are located.

6. The mask optimization method according to claim 1, wherein: Placing evaluation points on broken edges involves the following steps: Get a broken edge; Determine whether the previous edge and the next edge of the interrupted edge are both in the same straight line with the interrupted edge; if so, place an evaluation point on the interrupted edge; if not, find a circle tangent to the interrupted edge and the previous edge or the next edge that is not parallel to the interrupted edge within a preset radius, and place an evaluation point on the tangent circular arc segment.

7. The mask optimization method according to claim 1, wherein: The error function is set to: cost=∑ l c l (∑ i w i ·γ i ·(EPE l,i ) p )+cost(MRC)+ cost(sidelobe)+etc. Among them, l represents the lth process condition, c l is the weight of the process condition error on cost, i represents the i-th evaluation point, w i is the weight of the i-th point; EPE l,i is the edge placement error of the evaluation point at the lth process condition, p is an exponent; γ i It is a coefficient related to whether the evaluation point is a critical evaluation point. If the evaluation point is a non-critical evaluation point, its value is 1. If the evaluation point is a critical evaluation point, its value is a value set by the user that is greater than 1; cost (MRC) is the quantitative representation of the line segments that violate the mask manufacturing rules in the cost; cost (sid elob e) is the representation of the contour formed by the sub-resolution auxiliary graphics in the cost; etc represents other error terms.

8. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the mask optimization method according to any one of claims 1 to 7 is implemented.

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