Pipeline forward error correction method and device for vector signaling code channel

Abstract

The present invention discloses a pipeline forward error correction method and device for a vector signaling code channel. The error correction method comprises: receiving a plurality of data symbols in sequence, and storing each data symbol as a group of bits in a corresponding deserialization buffer position defined by a unique symbol position index value; generating a first symptom value of a bit error correction mask corresponding to a data symbol with a code error; generating a second symptom value of a bit error correction mask corresponding to the data symbol with the code error modulo multiplication of the unique symbol position index value; calculating the symbol position index value of the data symbol with the code error by dividing the second symptom value by the bit error correction mask; and generating a group of error-corrected output bits by applying the bit error correction mask to a group of bits stored in a deserialization buffer position identified by the symbol position index value of the data symbol with the code error.

Description

[0001] This application is a divisional application of the patent application with application number 201880038840.3, application date April 16, 2018, and invention name “Pipelined forward error correction for vector signaling code channels”. Technical Field

[0002] Embodiments of the present invention generally relate to communication system circuits, and more particularly to communication error reduction of a high-speed multi-wire interface used for inter-chip communication. Background Art

[0003] In modern digital systems, digital information is processed in an efficient and reliable manner. In this context, digital information is understood as information contained in discrete values ​​(i.e. non-continuous values). Digital information can be represented not only by bits and sets of bits, but also by numbers in a finite set.

[0004] To increase the overall bandwidth, most chip-to-chip or device-to-device communication systems use multiple lines for communication. Each or a pair of these lines can be called a channel or link, and multiple channels make up the communication bus between electronic components. At the physical circuit level, the bus in the chip-to-chip communication system is usually composed of packaged electrical conductors between the chip and the motherboard, packaged electrical conductors on the printed circuit board (PCB), or packaged electrical conductors in cables and connectors between PCBs. In addition, microstrip or strip PCB traces can also be used in high-frequency applications.

[0005] Common bus line signal transmission methods include single-ended signaling and differential signaling. In applications requiring high-speed communication, these methods can also be further optimized in terms of power consumption and pin utilization (especially these aspects in high-speed communication). The recently proposed vector signaling method can achieve a more optimized trade-off in terms of power consumption, pin utilization and noise robustness of chip-to-chip communication systems. This type of vector signaling system converts digital information into another representation space in the form of vector codewords at the transmitting end. The vector codewords are weighed and selected based on the characteristics of the transmission channel and the design constraints of the communication system to achieve a better trade-off between power consumption, pin utilization and speed. This process is referred to as "encoding" in this application. The encoded codewords are transmitted from the transmitter to one or more receivers as a set of signals. At the receiving end, the received signal corresponding to the codeword is inverted to the original digital information representation space. This process is referred to as "decoding" in this application. Summary of the invention

[0006] In the existing bit serial communication system, the data codewords provided by the sending process or the source process are first serialized (in an exemplary embodiment, serialized by a digital shift register) into an ordered bit stream, and then at the receiving end, the corresponding device deserializes the bits detected in sequence, so that the receiving process or the target process can provide a complete data codeword equivalent to the data codeword provided by the sender. The operation of the vector signaling code communication system is similar to this, but in such operations, the serialization process is often used to decompose the data codeword into multiple groups of symbols (for example, in the CNRZ-5 system, decomposed into 5 bit codewords), and the corresponding deserialization process is used to recover the data codeword by combining the received groups of symbols (such as still taking the above CNRZ-5 system as an example, 5 bits are combined).

[0007] Existing forward error correction (FEC) methods introduce redundancy into the transmitted data stream as part of the checksum used to detect errors and facilitate error correction. For communication links with inherently low BER (e.g., 1×10 -9 ~1×10 -10 ) and the target BER is 1×10 -15 ~1×10 -20 In the case of orders of magnitude, a new scheme described in this paper can be calculated during the serialization process of the transmitted value and verified during the deserialization process after reception, thereby introducing little or no additional delay into the transmission path in the error-free case.

[0008] In some embodiments, a method includes: decoding a preset number of vector signaling codewords received in sequence with a vector signaling code receiver to obtain sequential groups of data bits, wherein the code elements of each vector signaling codeword are received in parallel via multiple lines; progressively updating multiple error correction syndrome values ​​according to each sequential group of data bits and in accordance with a check matrix using an FEC check circuit; and after decoding the last vector signaling codeword among the preset number of received vector signaling codewords, finally progressively updating the multiple error correction syndrome values, and modifying the data bits in the sequential groups of data bits accordingly by selecting a group of data bits from the sequential groups of data bits according to symbol position index values ​​determined by the multiple error correction syndrome values ​​and modifying the selected group of data bits according to a bit correction mask determined by a first error correction syndrome value among the multiple error correction syndrome values. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 1 is a block diagram of a prior art communication system for transmitting data S from a transmitter 110 to a receiver 130 for outputting received data R via a set of lines 125 that together constitute a communication medium 120 .

[0010] Figure 2 Shown is one transmitter implementation that provides forward error correction functionality within a data path that employs multiple processing stages.

[0011] Figure 3 A receiver implementation is shown that provides forward error correction functionality within a data path using multiple processing stages.

[0012] FIG. 4A to FIG. 4C is a block diagram of CRC codeword calculation according to some embodiments.

[0013] Figure 5A and Figure 5B is a block diagram of error correction circuit components according to some embodiments.

[0014] Figure 6 FIG. 1 is a block diagram of erroneous data codeword location identification according to some embodiments.

[0015] Figure 7 is a flow chart of a method according to some embodiments.

[0016] Figure 8 A flow chart of a method for iteratively updating error correction syndrome values ​​according to some embodiments. DETAILED DESCRIPTION

[0017] As described in Cronie I, Cronie II, and Shokrollahi II, vector signaling codes can form a very high bandwidth data communication link, for example, between two integrated circuit devices within a system. Figure 1 In the embodiment shown, the data communication channel 120 composed of multiple lines 125 carries symbols of the vector signaling code, which work together to transmit the codewords of the vector signaling code. Depending on the specific vector signaling code used, the number of channels containing communication links can vary from two to eight or more, and one or more clock signals can also be transmitted through additional communication channels, or such clock signals can be transmitted as sub-channel components of the vector signaling code. Figure 1 In the example, the communication link 120 is shown as being comprised of eight lines 125 that are used to collectively transmit five data values ​​100 and a clock 105 between a transmitter 110 and a receiver 130. Such communication links are further described in Shokrollahi II.

[0018] Individual symbols, such as those transmitted in any single communication channel, may use a variety of different signal levels, typically three or more signal levels. When channel rates exceed 10 Gbps, the reception operation may be further complicated by the need for deeply pipelined or parallelized signal processing. The embodiments described in this application may also be used for existing permutation and combination sorting methods that are not covered by the Shokrollahi II vector processing method. More generally, such embodiments may be used for any communication or storage method that requires coordination between multiple channels or multiple channel elements to produce a logical overall result.

[0019] Given the fact that the transmission of multiple symbols is essentially parallel, vector signaling codes are generally considered to transmit data in the form of multiple groups of symbols, for example, in the CNRZ-5 code (also known as the Glasswing code) described in "Shokrollahi II", the transmission is progressively transmitted in increments of five bits. Accordingly, in the following, the transmission mode may be described as K×n bit progressive transmission, where n is the code symbol group size or payload size. However, the document further points out that the coding subchannels for transmitting each bit are mathematically different from each other, and in some embodiments, independent transmission channels can be used.

[0020] Serialization and Deserialization

[0021] In the existing bit serial communication system, the data codewords provided by the sending process or the source process are first serialized (in an exemplary embodiment, serialized by a digital shift register) into an ordered bit stream. At the receiving end, the corresponding device deserializes the bits detected in sequence, so that a complete data codeword equivalent to the data codeword provided by the sender can be provided to the receiving process or the target process. The operation of the vector signaling code communication system is similar to this, but in such operations, the serialization process is often used to decompose the data codeword into multiple groups of symbols (for example, in the CNRZ-5 system, decomposed into 5 bit symbols), and the corresponding deserialization process is used to recover the data codeword by combining the received groups of symbols (such as still taking the above-mentioned CNRZ-5 system as an example, 5 bits are combined).

[0022] Obviously, serialization and deserialization introduces delay in the transmission channel, and since the entire codeword can only be obtained after the last transmitted codeword has been received and the received codeword has been fully reassembled, the amount of delay depends on the number of transmitted codewords formed by serializing a given data codeword.

[0023] In some high-speed communication systems, serialization and deserialization may further include multiple processing stages, which are substantially performed in parallel to provide additional processing time for each stage and / or reduce power consumption by allowing processing operations to use a lower clock rate. In a representative embodiment, the data codewords provided by the transmission process or the source process are decomposed into codewords in succession, and each codeword is assigned to a processing stage that is selected in sequence and used to implement necessary encoding, formatting and other operations. When each processing stage completes its operation, the processing result is sent to the output driver for transmission in the communication medium. Therefore, when four processing stages are used, each stage will have approximately four transmission unit time intervals to perform the necessary operations. The receiver may also adopt a similar multi-stage processing method, that is, the codewords received in succession are detected by the processing stages assigned in sequence and recombined into output codewords.

[0024] In this application, embodiments involving multiple processing stages are used as descriptive examples to achieve the broadest and most complete description of features and characteristics. Other embodiments may also use more or fewer processing stages (including a single stage), and may include larger or smaller transmit and / or receive processing workloads in these substantially parallel processing stages, but the invention is not limited thereto.

[0025] Link Error Correction

[0026] Although communication systems are designed with error-free data transmission in mind, noise and other signal interference factors are still inevitable. The error probability of a transmission path is expressed by the bit error rate (BER), which is the ratio of the number of received bit errors to the total number of transmitted bits.

[0027] Known bit error detection methods in the art include cyclic check codes, parity checks, and redundant transmission. Among the known error correction methods, the most noteworthy is the closed-loop retransmission method in the TCP / IP protocol suite. In this method, when the receiver detects an error, it first requests the transmitter to retransmit through the reverse channel, and then explicitly inserts the corrected data into its output code stream. In addition, the art term "cyclic redundancy check (CRC)" used in this application refers to any set of calculated bits that can achieve error identification and error correction by expanding the data stream.

[0028] Forward Error Correction

[0029] When the reverse channel cannot be used or the round-trip latency caused by retransmission is not allowed, the existing forward error correction (FEC) method can be used. This method introduces redundancy in the transmitted data stream as part of the checksum used to detect errors and facilitate error correction. The greater the redundancy introduced in the transmission data stream (for example, the longer the FEC sequence used), the higher the FEC bit error correction capability obtained, but at the same time the protocol overhead is also greater, that is, the effective data transmission rate is lower.

[0030] As described in Bhoja et al., several FEC techniques have been proposed for high-speed communication links, including KR4 and KP4 codes for 802.3bj, and BCH codes (e.g., length 2864 and dimension 2570). Other such techniques include, for example, Reed-Solomon codes described in Shokrollahi I and Hamming, Hadamard, Reed-Muller, Golay, and low-density parity-check (LDPC) codes described in Cronie II. Since such error correction methods deal with relatively high BERs (1×10 -5 1×10 -3 The communication link has a bit error rate of 1×10- 15 The error correction delay caused by such methods is on the order of tens of nanoseconds (e.g., 100 ns according to Bhoja et al.), and the corresponding computational power consumption is relatively high.

[0031] When the inherent pre-error correction BER of the communication link is low (e.g. 1×10 -9 1×10 -10 ) and the target BER is 1×10 -15 ~1×10 -20 When the latency is in the order of magnitude higher, other methods can be chosen to significantly reduce the latency for chip-to-chip links within a package that use vector signaling codes, such as Glasswing codes or CNRZ-5 codes described in Shokrollahi II.

[0032] For a vector signaling code that sends n bits on m lines each time, since a bit error in the communication link may cause all n bits to be erroneous, it is preferred to use a vector signaling code that works over a finite field GF(2 n ) within the FEC.

[0033] Pipeline error correction processing

[0034] A link-optimized forward error correction implementation achieves minimization of perceived error correction delay by sequentially transmitting data codewords with a transmission-level vector signaling code. In such an implementation, n-bit groups consisting of n bits are transmitted on m lines with a vector signaling code. Therefore, N consecutive bit groups can transmit N×n bits consisting of K×n data bits and R×n CRC bits for error correction. At the transmitting end, the K×n data bits are provided by a data source, typically in the form of multiple transmissions, via a wide parallel interface. At the receiving end, the received K×n data bits are delivered to the data recipient by a similar interface.

[0035] In a non-limiting specific example, consider the following: CNRZ-5 code; n = 5 and m = 6; typical message length N = 32. This situation can be interpreted as equivalent to sending 5 bit streams simultaneously, each bit stream containing 32 bits sent one after the other. GF(2 n ) The forward error correction code can correct a single bit error. Assuming the input BER is p, and the unit interval errors of all bit streams are random and independent errors (but the errors between the 5 bits that make up the codeword in each unit interval are not independent of each other), the decoded output BER is at most:

[0036]

[0037] Where q = 1-(1-p) 5 And N = 32.8 × 10 -10 The input BERp is sufficient to achieve 1×10 -15 The output BER of the code is 15 / 16=93.75%, and the rate loss rate is 6.25%. In such an embodiment, at a baud rate of 26.66G, the interface can send 5×26.66×0.9375=125Gbps of data via 6 lines.

[0038] FEC transmission

[0039] At the sending end, this implementation performs the following operations:

[0040] The five bits to be transmitted in each unit interval (UI) are considered as elements of the finite field GF(32). For example, if n0, n1, n2, n3, n4 represent the five bits, where n0 is the least significant bit of n and n4 is the most significant bit, then n corresponds to the following element:

[0041] n0+n1*x+n2*x 2 +n3*x 3 +n4*x 4 mod f(x) (Equation 2)

[0042] And f(x) is a polynomial x 5 +x 3 +1.

[0043] The GF(32) element uses a check matrix with 2 rows and 30 columns. In one embodiment, the jth column of the matrix is ​​1 and a j , where the element a of GF(32) j is the binary expansion of the integer j, that is, a j Expressed as a binary vector [j0j1j2 j3 j4], where j0+2×j1+4×j2+8×j3+16×j4=j. Although other implementations may also use different check matrices, efficient calculation of the error locating vector can be achieved by using a check matrix that uses the binary expansion of the integer j as the second row element. The error locating vector is used to find received symbols containing errors. Specifically, this avoids the use of the Berlekamp-Massey algorithm (including the corresponding ChienSearch). In addition, by directly calculating the bit error correction mask with the full "1" row of the check matrix, it is possible to avoid determining the error amplitude according to the Fomey formula. Formula 3 for calculating r0 and r1 using the above check matrix is ​​as follows:

[0044]

[0045] In formula 3, by including two rows of constants (one row is all "1" and the other row is a0~a 29 ) is multiplied by the vector containing 30 data symbols m0~m29 to generate the CRC code words r0 and r1.

[0046] When the input 30 five-bit data codewords (whose bits are transmitted in five CNRZ-5 subchannels substantially simultaneously) are denoted as m0, m1, ..., m29, the two five-bit CRC codewords r0 and r1 are Where a·b represents the product of a and b in the finite field GF(32), Therefore, r1 can be generated by incrementally updating the previous stored value of r1 by performing a bit-by-bit XOR operation on the previous stored value of r1 and the modular multiplication result of aj·mj in the jth unit interval, and the final value of r1 is generated at the last incremental update.

[0047] The message data m0, m1, ..., m29 corresponds to the five-bit codewords at time points 0, 1, ..., 29. Therefore, the CRC codewords r0, r1 can be calculated in an incremental manner as the data gradually becomes available. The corresponding pseudocode for this calculation is:

[0048]

[0049] Figure 4A The present invention includes a schematic diagram of a method for calculating the value of r0 according to some embodiments. As shown in the figure, the given value of r0 is updated by performing an XOR operation 403 on the previous stored value 402 of r0 and the corresponding bit at the corresponding position of the data codeword mj. For example, r0[0] can be XORed with mj[0], r0[1] can be XORed with mj[1], and so on. Therefore, for an index value i of 0≤i≤4, Such an implementation may be performed recursively, for example, as individual bits mj[i] gradually become available. In such an implementation, each data bit mj[i] may be provided, for example, by a shift register. Alternatively, when all data codewords are available, the calculation may also be performed, for example, by Figure 4B The logical XOR tree structure is shown.

[0050] As mentioned above, the calculation of r1 includes: transforming the GF(32) matrix a j The element is multiplied by the corresponding data codeword mj; and the obtained result is XORed. In some embodiments, Figure 4B The XOR tree structure 404 shown may be formed by the FEC encoder. Such XOR tree structures may be formed by known logical combinations, such as the logical combinations used to calculate r0 and r1 in Appendix A. Such implementations may obtain all data bits (150 in the above examples) before performing calculations with the XOR tree structure. Figure 4B A specific example of the calculation of r1[0] is shown. In such an embodiment, the input value 405 may be a preset value selected according to the bit used to update r1[0] according to Appendix A.

[0051] Figure 4C FIG. 1 is another schematic diagram of a logic circuit for gradually updating a given bit r1[0] as part of a CRC codeword r1 according to some embodiments. Figure 4C In the schematic diagram, the r1 value can be progressively updated according to the CRC calculation formula corresponding to the modular multiplication of a set of data bits of a given symbol and the symbol index value of the check matrix. In such an implementation, the update can be implemented as the bits in each set of data bits of symbols m0 to m29 gradually become available, thereby reducing the delay. As shown in the figure, Figure 4CA storage unit 407 is included for holding the current value of r1[0]. The current value r1[0] is XORed 410 with a sequence of K×n data bits determined by the CRC calculation formula, wherein the i-th bit among the FEC data bits is represented as inp[i]. The index mark sequence inp[i] represents the input data currently being processed, wherein, in the above embodiment with a total of K=30 groups of n=5 data bits, inp[0...4] is 5 bits of the data codeword m0, inp[5...9] is 5 bits of the data codeword m1, ..., inp[145...149] is 5 bits of the symbol m29.

[0052] In this case, the current value of r1[0] does not need to be updated for each of the K×n data bits, but the current value of r1[0] is selectively updated by the corresponding enable signal EN according to a set of preset bits (see Appendix A). As shown in the figure, in some embodiments (not shown), the shift register 415 can obtain the K×n data bits from the data buffer 210 of the transmitter and serially input these data bits into the XOR operation unit 410.

[0053] In a receiver implementation for calculating r1′, if Figure 4C As shown, the shift register 415 can be connected to each processing stage 330. Alternatively, each stage can have a corresponding shift register, and all of these shift registers can be multiplexed (not shown). In some embodiments, the shift register 415 can be loaded in parallel. In such embodiments, the shift register 415 can include a plurality of D flip-flops, which can be loaded in parallel and serially shifted and output to the XOR operation unit 410. Box 417 represents a storage unit of the shift register 415 according to some embodiments. As shown, the storage unit 417 is connected to the MIC0 output terminal p0[0]~p3[0] of each of the four processing stages 330. In addition, the stage of the storage unit 417 to be loaded is selected by the stage selection signal phase_sel. In some embodiments, the selected stage can be provided to the elements represented by the above blocks by a multiplexer for receiving each stage, and the selection signal can take the form of a two-bit clock counter for selecting the stage of the register to be loaded. Although only the storage unit 417 for receiving the MIC0 output of each processing stage is described above, each other storage unit of the shift register 415 can receive the corresponding MIC output of the multiple processing stages in a similar manner. For example, the storage unit 419 can receive the MIC1 output of each processing stage.

[0054] Figure 4CFurther comprising a counting circuit, the circuit is used to generate partial enable signals including partial enable signals 4, 5, 7, which can be combined to form a corresponding global enable signal EN of bit r1[0]. As shown in the figure, the counting circuit includes a counter 420 and a plurality of AND logic gates 422a, 422b, 422c. In some embodiments, the counter is used to count from i=0 to i=K×n-1, where i is an index value associated with the corresponding data bit inp[i] in the above K×n data bits. The current output value i of the counter 420 can be represented as a set of bits ( Figure 4C , X, Y, Z in the figure). AND logic gates 422a-422c are used to receive bits X, Y, Z, and each AND gate 422a-422c has an inverting input terminal and a non-inverting input terminal combined in a corresponding manner, so that for each count value i, only one signal corresponding to the given count value among the partial enable signals is logic "1", and the rest are logic "0". In some embodiments, the corresponding global enable signal EN for each bit in the CRC codeword r1 is formed by performing an OR operation 425 on the partial enable signals corresponding to each bit index value i of the above-mentioned set of preset known bits. Figure 4C In the illustrative example, r1[0] is updated with only two bits, inp[4] and inp[7]. Therefore, the global enable signal EN is formed by ORing the partial enable signals 4 and 7, and when the count value i=4 and 7, r1[0] is updated with bits inp[4] and inp[7], respectively. Although the counter 420 is illustrated as having only three bits X, Y, Z for forming the binary count value i, this illustration is for illustrative purposes only, and it should be noted that the counter 420 may include any number of bits. For example, in the examples given above and in Appendix A, the counter may form a count value i having 8 bits, i.e., counting from i=0 to i=149 (reset at i=149) to update the bits in the CRC codeword r1.

[0055] FIG. 4A to FIG. 4C The illustrated embodiments are only a few examples of logic circuits that can be hardwired to perform calculations on each bit in the CRC codewords r0 and r1. The calculations can be performed by various other logic circuit designs. For example, in other embodiments, the above variables can be calculated by a processor running a software application.

[0056] After completing the input data processing, the CRC codewords r0 and r1 can be sent as the last two codewords, which are recorded as m30 and m31 in this application. In another embodiment, the transmitter can first calculate r0 and r1 based on the available buffered transmit data, and then send five bits of r0 and five bits of r1 with the first and second vector signaling codewords. In this embodiment, the decoder can then conveniently initialize the decoding circuit (FEC check circuit for calculating the symptom value) with the two check values.

[0057] Since the elements a0, a1, ..., a29 are known in advance, and m0, m1, ..., m29 are variables, each multiplication operation in GF(32) can be performed by a series of XOR operations on 5 bits. As known to those skilled in the art, this approach is called the "canonical representation of the finite field GF(32)". In this representation, each element in a0, a1, ..., a29 is represented as a 5×5 bit matrix, and accordingly, the multiplication operation a[j]·m[j] corresponds to the multiplication operation between this matrix and the representation vector of m[j].

[0058] As an implementation of the above series of operations, a specific GF(32) canonical form is given in Appendix A, but the present invention is not limited thereto. Many other representations can also be used to obtain similar results.

[0059] Preferably, the calculation at the transmitting end is performed simultaneously with the above-mentioned serialization step, that is, each group of data becomes gradually available and becomes available for transmission in an asymptotic manner. This "pipelined vFEC calculation method avoids the additional delay problems often encountered in forward error correction technology. In an embodiment in which multiple substantially parallel processing stages are used in the transmission process, each processing stage can complete various parts of the r0, r1 calculation. In some embodiments, at least one of the processing stages includes XOR logic for facilitating at least a portion of the above-mentioned calculation.

[0060] Figure 2The figure shows a transmitter implementation using the CNRZ-5 code described in Shokrollahi II. The data buffer 210 receives the transmission data. Generally, the data source preferably transmits data in the form of a codeword of 16, 32 or 64 bits, for example but not limited to. After receiving the input codeword transmitted in the above form, the data buffer 210 outputs symbols m0, m1, ..., m29 corresponding to each group of data bits (in this example, each symbol corresponds to a five-data bit group consisting of five data bits). The symbols that follow one another are assigned 215 to the processing stages of phase 0, phase 1, phase 2, phase 3, etc. in all processing stages 220 in a cyclic order. Each processing stage 220 simultaneously performs CNRZ-5 encoding 222 and the above-mentioned FEC calculation 221 on a five-data bit group. Under the control of the clock generator 250, the multiplexer 230 selects the results generated by each processing stage to provide the line driver 240 with the output symbols 235 to be sent via the communication channel consisting of lines W0 to W7. As described in Shokrollahi II, clock generator 250 also generates transmit clock 255, and Figure 2 In the example, the transmit clock is transmitted as part of the transmit output by line driver 240 via lines W6 and W7.

[0061] In the process of processing the first 30 output codewords using the data obtained from the data buffer 210, the multiple FEC calculation instances 221 can update the CRC codewords r0, r1 by accessing a set of common registers or storage units. Subsequently, the FEC processing unit in a certain processing stage outputs r0 as the 31st output codeword to be encoded by the vector signal encoder 222, and the FEC processing unit in the next selected processing stage outputs r1 as the 32nd output codeword to be encoded by the encoder 222.

[0062] Receiving and Error Correction

[0063] At the receiving end, a corresponding implementation implements a similar set of CRC calculations. Among them, 32 five-bit codewords are received in sequence - the arrival time of the first five-bit codeword m0 is 0, and the arrival time of the 32nd five-bit codeword m31 is (UI×31), where UI is the symbol transmission unit time interval. In such an implementation, local CRC codewords r0′ and r1′ are generated, and the final error correction syndrome values ​​r0″ and r1″ are generated by comparing the local CRC codewords r0′ and r1′ with the received CRC codewords r0 and r1. Alternatively, the FEC check circuit 332 can be first initialized by receiving CRC codewords r0 and r1 from the transmitter, and then the multiple error correction syndrome values ​​initialized by the received CRC codewords r0 and r1 are progressively updated according to the groups of data bits received in sequence.

[0064] In the first step of receiving error correction, the operations in Appendix A are performed, preferably synchronously with the deserialization step of the first 30 data codewords, to progressively calculate the values ​​of the local CRC codewords r0′ and r1′. Similar to the transmitter case, each step of the progressive calculation is performed only for the received five-bit codeword value, thereby achieving progressive calculation of each value. In addition, similar to the transmitter case, in one embodiment, at least one processing stage among the multiple receiving processing stages includes XOR logic for performing at least a portion of the above calculations. In some embodiments, the same FIG. 4A to FIG. 4C Similar circuits are shown to calculate r0' and r1' values. In some embodiments, local CRC codewords r0' and r1' may be calculated as bits of data codewords m0-m29 become available, while in other embodiments, r0' and r1' may be calculated once all data codewords have been received.

[0065] After multiple error correction syndrome values ​​are progressively updated (preferably in the deserialization step) by processing the first 30 groups of received data bits, r0′ and the received CRC codeword m30 (r0) are XORed, and r1′ and the received CRC codeword m31 (r1) are XORed to generate error correction syndrome values ​​r0″ and r1″, respectively. For illustrative purposes, r0″ and r1″ may be referred to as error correction syndrome values ​​(after the final progressive update) or as syndrome codewords. Among them, r0″ and r1″ contain the so-called "symptoms" of the forward error correction code. If r0″ or r1″ is zero, it means that the groups of data bits m0,..., m29 sent are error-free and no further processing is required. Among them, although there may still be errors in these codewords that are not diagnosed in the progressive update of the error correction syndrome values, the incidence of such missed errors is within the above BER range after error correction. At least one embodiment employs multiple receive processing stages, each receive processing stage including logic for performing at least a portion of the operations in Appendix A or their logical equivalents and for performing the above-described FEC symptom diagnostic XOR operation.

[0066] In some embodiments, multiple error correction syndrome values ​​of the receiver FEC circuit can be initialized by receiving CRC codewords r0 and r1 in the first two unit intervals from the transmitter, so that r0″ and r1″ can be directly calculated by progressively updating with each group of data bits obtained in sequence. In some embodiments, the FEC check circuit can be used as follows Figure 4C However, other embodiments may also use a preset combinational logic circuit based on a logical expression (such as the logical expression listed in Appendix A) to update the error correction syndrome value using one or more data bits in the set of decoded data bits. Such a circuit may be similar to Figure 4B The combinatorial logic circuit shown. However, since in this case, the receiver can only use it once when all data bits are obtained, the combinatorial logic circuit can update the error correction syndrome value by hard coding using bits selected according to the index number of a group of currently received data bits in the currently received symbol. For example, the error correction syndrome value r1[1] can be updated with one bit in symbol m0 (inp[1] in Appendix A), and then the error correction syndrome value r1[1] can be updated with three bits in symbol m1 (inp[5], inp[6], inp[7]). Among them, the control logic for implementing the above-mentioned progressive update according to Appendix A can be hard coded, and the control logic for implementing the binary modulo operation according to the r1 calculation algorithm in the above-mentioned pseudo code can also be coded.

[0067] If the error correction syndrome values ​​r0″ and r1″ are both non-zero, the received data bits need to be corrected - r0″ is used as a five-bit error correction mask, and the symbol position index value of the error-containing symbol is determined based on the vector r1″ / r0″, where the division is a division in the finite field GF(32). The error correction operation of calculating the error index value r1″ / r0″ and the XOR operation of applying the error correction mask to the codeword mt can be implemented after the deserialization step. Among them, the symbol position index value t=pos-1, where pos is an integer form of r1″ / r0″. In one embodiment as a non-limiting example, after calculating pos=r1″ / r0″, the barrel shifter performs a bit-by-bit XOR operation function by applying the bit error correction mask r0″ to the value of a selected group of data bits mt.

[0068] More specifically, the above decoding operation can be described by the following pseudo code:

[0069]

[0070] As described above, the symbol position index value (expressed as b in the following equation 4) is obtained by dividing r1″ by r0″:

[0071]

[0072] Figure 5A FIG. 5 is a block diagram of an embodiment of an error correction circuit 560 connected to the FEC check circuit 510 according to some embodiments. In some embodiments, the error correction circuit 560 may correspond to Figure 3 360 in the "error correction". As shown in the figure, the FEC check circuit 510 obtains 150 data bits of the 30 decoded five-bit data codewords and 10 bits of the received CRC codewords r0 and r1 in turn. Subsequently, the FEC check circuit 510 progressively updates multiple error correction syndrome values. In some embodiments, the FEC check circuit first initializes each error correction syndrome value in it to a static value (all zeros), then generates local CRC codewords r0', r1' based on the received data bits, and in the final progressive update, performs and These two XOR operations generate error correction syndrome values ​​r0″ and r1″ respectively. Alternatively, as described above, CRC codewords r0 and r1 may be received from the transmitter in the initial unit interval, and then the error correction syndrome values ​​may be initialized with the received CRC codewords. Subsequently, the FEC check circuit 510 may progressively update the error correction syndrome values, and directly obtain the error correction syndrome values ​​r0″ and r1″ at the final progressive update, without the need to implement the additional XOR operation step in the previous embodiment. In some embodiments, the FEC check circuit 510 may be FIG. 4A to FIG. 4CThe CRC codeword generator shown operates in a similar manner and has the additional function of generating error correction syndrome values ​​r0″ and r1″. Subsequently, the error correction circuit 560 can determine whether there is a code error based on the final error correction syndrome value. As described above, if r0″ or r1″ is zero, the error correction circuit does not need to perform an error correction operation. If the error correction mask r0″ is "00000", the XOR operation on the selected symbol remains unchanged; and if r1″ is "00000", it means that there is a code error in the received CRC codeword r0 or r1, so the error correction circuit can ignore this situation and not correct the data bits. If the error correction syndrome values ​​r0″ and r1″ are not zero, the five-bit symbol position index values ​​x[0]~x[4] used to find the position of the symbol containing the code error are identified by implementing the above-mentioned r1″ / r0″, thereby determining the position of a group of data bits of the symbol containing the code error. Figure 5A By finding the bit form of the reciprocal of r0″, we can calculate Thus, r1″ / r0″ is obtained. In some embodiments, the above conversion 520 can be completed using a lookup table. After completing the conversion, r1″ and r0″ can be converted using a shrinking technique. Multiply by 525 to find the symbol position index values ​​x[0] to x[4] of the erroneous data codeword. As mentioned above, the decimal form of the symbol position index values ​​x[0] to x[4] may be denoted as pos below, and in the above example, 1≤pos=30.

[0073] The bits x[0] to x[4] of the symbol position index value, the bit error correction mask r0″ and the groups of data bits received in sequence can be provided to a group of registers 565 for implementing error correction by modifying a selected group of data bits. Figure 5B A group of registers 565 according to some embodiments is shown. As shown in the figure, the register 565 includes: a first register 530, which contains groups of data bits corresponding to the received data in sequence; a second register 535, which contains a bit error correction mask r0″ for correcting a group of data bits in the received data at positions determined by the symbol position index value bits x[0]~x[4] to prevent other bits in the received data from being changed. The first and second registers can be subjected to a unit-by-unit XOR operation to generate a group of error-corrected data in the third register 540, which can then be output by the system. Figure 5B In the example, a group of data bits corresponding to the symbol m14 is determined by the symbol position index value as a group of data bits that need to be corrected, and accordingly, an XOR operation is performed on the group of bits corresponding to the symbol m14 and the corresponding bit correction mask of the error correction syndrome value r0″.

[0074] As described above, first, the reciprocal of r0″ can be found through a lookup table. Appendix C provides an example lookup table for implementing this function. After obtaining the reciprocal of r0″, the reciprocal can be multiplied by r1″ to obtain the above-mentioned values ​​of x[0] to x[4]. In some embodiments, the multiplication can be implemented by the following logic circuit-based operation, where invr0″ represents the reciprocal of r0″ (or the multiplication inverse element) obtained through the lookup table in Appendix C, and the "&" symbol represents logical AND, Represents logical exclusive OR:

[0075]

[0076]

[0077]

[0078]

[0079]

[0080] The above calculation and the corresponding lookup table are only one possible implementation of the error correction circuit, and a variety of other logic functions can be used to achieve the same function. In some implementations of the error correction circuit, the above operation can be implemented using a physical logic circuit, while in other implementations, the above operation can also be implemented by software running in a processor.

[0081] After the error correction circuit obtains the position pos-1 of the error data codeword and the bit error correction mask r0″, the error correction circuit can align the error correction mask with the correct symbol of the received data 530 through a register, for example, and perform an XOR operation. Figure 5B The error correction of symbol m14 is shown. As shown in the figure, the bit error correction mask r0″ can be loaded into the error correction register 535 at a position determined by the symbol position index value corresponding to the symbol m14. In at least one embodiment, the starting bit of a group of selected data bits corresponding to the erroneous data codeword can be the product of the length "n" of each received data codeword and the symbol position index value (pos-1). Finally, an XOR operation can be performed on the data register 530 containing 150 bits of received data and the error correction register 535 containing the bit error correction mask r0″ and the rest of the data are logical zero values ​​to obtain a group of error-corrected data bits 540, which can then be output by the system.

[0082] Figure 6 A specific example of a logic circuit for performing the operation at the division block 515 of the error correction circuit 560 is shown. As shown in the figure, according to some embodiments, the logic circuit is used to calculate the x[k] part of the symbol position index value pos of the error data codeword. Figure 6 As shown, the logic circuit includes a storage unit 605 storing a current value (shown as x[0] in this example). The value of x[0] can be updated by performing an XOR operation 610 on the current value of x[0] and a selected bit combination of error correction syndrome values ​​r0″ and r1″. In some embodiments, the process is hard-coded by a multiplexer 615 connected to an AND gate network 620, and the bit combination of error correction syndrome values ​​r0″ and r1″ is progressively selected by a selection signal (e.g., a simple count value). In at least one embodiment, the sequence of logical combinations selected by the selection signal and provided to the XOR gate 610 to update x[0] can be predetermined according to the progressive processing process in Appendix B. In addition, for other bits of the index value x[k], a similar logic circuit can also be used to implement a corresponding preset update sequence. Figure 6 The logic circuit is only one example of a method for generating a given bit of x[k]. In addition, the above purpose can also be achieved by other circuit forms. Alternatively, the processing process of Appendix B can also be implemented by a processor running a software algorithm.

[0083] Since part of the error correction process occurs outside of deserialization, it is necessary to minimize the impact on perceived delay by shortening the total delay time caused by such operations as much as possible. Such design optimization can be achieved by design automation tools known in the art. However, such tools should preferably also have a suitable element-form search starting point to minimize the computational logic depth. A suitable implementation of this aspect is shown in Appendix B, in which the logic depth can be up to 7 when no further optimization is implemented. The above-described implementation can be used to correct errors caused by energy impact on the lines in a multi-line bus. For example, when one or more lines in a multi-line bus are subjected to electromagnetic energy impact, one or more bits in the decoded data codeword may be erroneous. Such errors can be identified by a bit error correction mask at the output. Among them, the bit error correction mask is used to correct one or more bit errors identified by the so-called error correction syndrome value in the selected erroneous data codeword.

[0084] Figure 3 The figure shows a typical CNRZ-5 vector signaling code receiver implementation, which uses a multi-input comparator 320 to detect five data results MIC0-MIC4 and a receiving clock CK. After being equalized by a continuous time linear equalizer (CTLE) 310, line signals W0-W5 are provided to a group of MIC320 described in Shokrollahi II to generate detection data values ​​MIC0-MIC4. In addition, CTLE310 (not shown) can also perform equalization processing on lines W6 and W7. Figure 3As shown, the group of MIC320 includes five comparator circuits, wherein each MIC corresponds to a linear amplifier circuit that performs linear combination operations only on line signals on lines W0 to W5, and each line signal corresponds to a vector signaling code word symbol of a vector signaling code. As described in Shokrollahi II, each MIC can implement a corresponding linear combination operation defined by a corresponding subchannel among a plurality of mutually orthogonal subchannels, and each subchannel can be defined by a receiver matrix. Figure 3 In the example, lines W6 and W7 are dedicated lines for carrying differential clock signals, and the receiving clock CK is generated by a differential comparator 340 running on lines W6 and W7. Other embodiments may not carry differential clock signals through dedicated lines W6 and W7, but send the clock (for example, as output signal MIC4) through a dedicated sub-channel among the above mutually orthogonal sub-channels. Alternatively, the clock signal may be extracted from the detected data outputs MIC0 to MIC4 using transition information (i.e., data inference clock recovery method).

[0085] The detected data values ​​MIC0-MIC4 are provided to four processing stages 330, each of which processes the received data for a unit time interval. The received clock signal is provided to a clock recovery unit 390 for generating four sequential clock phases ph000, ph090, ph180, ph270. These clock phases work together to coordinate the operation of each processing stage 330. In each processing stage, the comparator outputs MIC0-MIC4 are sampled 331 at the time determined by the clock of the stage to generate sequential five-bit codeword groups m0-m29 and received CRC codewords (r0 and r1), which are then provided to a buffer 370. Figure 3The receiver also includes an FEC check circuit 332, which is used to progressively update multiple error correction syndrome values ​​based on sequential groups of data bits. In some embodiments, the multiple error correction syndrome values ​​are initialized to logical zero values, and the FEC check circuit generates a set of n-bit local CRC codewords r0′, r1′ based on the received sequential groups of data bits, and after the last vector signaling codeword is decoded, the local CRC codewords r0′, r1′ are compared with the received CRC codewords r0, r1 to form n-bit error correction syndrome values ​​(r0″ and r1″). Based on the error correction syndrome values ​​r0″ and r1″, it can be determined whether there is a bit error. In other embodiments, the transmitter can first initialize the multiple error correction syndrome values ​​by sending CRC codewords r0 and r1, and then can send the multiple groups of data bits. In such embodiments, the multiple error correction syndrome values ​​r0″ and r1″ become final values ​​with the decoding of the last vector signaling codeword, so the above-mentioned final comparison step can be omitted. Consistent with the transmitter, the receiver's buffer 370 combines five-bit received data values ​​from each processing stage 330 into a data codeword (i.e., "received data output" in the figure). The receiver further includes an error correction circuit 360, which is used to modify the received bit errors in the buffer 370 in accordance with the error correction algorithm described in Appendix B. In some embodiments, when errors exist, the error correction circuit 360 generates a set of error-corrected data bits by correcting one or more errors in a set of selected data bits associated with the symbol position index value determined by the multiple error correction syndrome values, wherein the one or more errors are corrected with a bit correction mask determined by the first error correction syndrome value r0".

[0086] Figure 7 Flowchart of method 700 according to some embodiments. As shown, method 700 includes: in step 702, receiving a codeword sequence having m symbols; and in step 704, correspondingly forming a plurality of groups of n comparator outputs, wherein n is an integer greater than or equal to 3. In step 706, sampling each comparator output and detecting 706 a plurality of n-bit codewords, wherein the plurality of n-bit codewords include data codewords and cyclic redundancy check (CRC) codewords. In step 708, generating a set of n-bit local CRC codewords according to the received data codewords. In step 710, forming n-bit symptom codewords (such as the above-mentioned error correction symptom values) according to (1) a set of local CRC calculation values ​​determined according to the received plurality of n-bit data codewords and (2) the received CRC codewords, wherein the symptom codewords indicate whether there is a bit error. When errors exist, the method corrects 712 one or more errors within the erroneous data codewords whose index values ​​are determined by the combination of the n-bit syndrome codewords with a bit correction mask corresponding to one of the syndrome codewords.

[0087] In some embodiments, generating the local CRC codeword includes performing a logical exclusive OR operation on bits of the data codeword. In some embodiments, performing the logical exclusive OR operation includes generating bits within position index value i of the first local CRC codeword by performing an XOR operation on bits within position index value i of each data codeword, where 0≤i≤n-1. In some embodiments, generating at least one local CRC codeword includes: multiplying each data codeword by a corresponding index value of the data codeword; and recursively performing a logical exclusive OR operation on each data codeword obtained by the modular multiplication.

[0088] In some embodiments, the set of local CRC codewords are updated in a recursive manner as each data codeword is gradually received. Alternatively, the local CRC codewords may be generated after all data codewords are received.

[0089] In some implementations, when each syndrome codeword is non-zero, a bit error exists.

[0090] In some embodiments, determining the index value of the erroneous data codeword includes: forming a binary reciprocal of a bit error correction mask representing one of the symptom codewords; and multiplying it by a contraction of another symptom codeword. In some embodiments, the binary reciprocal can be obtained using a lookup table. In some embodiments, the error correction includes performing an exclusive-or operation between the erroneous data codeword and the bit error correction mask.

[0091] Figure 8 Flowchart of method 800 according to some embodiments. As shown in the figure, method 800 includes decoding 802 a preset number of vector signaling codewords received in sequence by a vector signaling code receiver to obtain sequential groups of data bits, wherein the code elements of each vector signaling codeword are received in parallel via multiple lines. Subsequently, a plurality of error correction syndrome values ​​are progressively updated 804 by an FEC check circuit according to each sequential group of data bits and in accordance with a check matrix. After decoding the last vector signaling codeword among the preset number of received vector signaling codewords and finally progressively updating the plurality of error correction syndrome values, the data bits in the sequential groups of data bits are modified by selecting 806 a group of data bits from the sequential groups of data bits according to a symbol position index value determined by the plurality of error correction syndrome values ​​and modifying 808 the selected group of data bits according to a bit correction mask determined by a first error correction syndrome value among the plurality of error correction syndrome values.

[0092] In some embodiments, progressively updating the multiple error correction syndrome values ​​includes: performing a logical exclusive OR operation on the error correction syndrome values ​​stored last time according to a given set of data bits. In some embodiments, the logical exclusive OR operation is performed by performing a bit-by-bit exclusive OR operation on the error correction syndrome values ​​stored last time with the given set of data bits. Such operation is applicable to the case where the error correction syndrome values ​​corresponding to r0″ are progressively updated. Alternatively, the logical exclusive OR operation is performed by performing a logical exclusive OR operation between the error correction syndrome values ​​stored last time and the bits determined by the CRC calculation result corresponding to the modular multiplication result of the binary expansion of the given set of data bits of the received data codeword mj and the symbol index integer value j. Such exclusive OR operation is applicable to the case where the error correction syndrome values ​​corresponding to r1″ are progressively updated. For example, the CRC calculation may include modular multiplication of the five-bit data codeword m13 with the five-bit binary expansion of the integer j=“13”. The result of the CRC calculation may then be XORed with the 5-bit error correction syndrome value r1 stored last time.

[0093] In some embodiments, the plurality of error correction syndrome values ​​are initialized to logic zero values, and the final progressive updating of the plurality of error correction syndrome values ​​comprises: comparing the plurality of error correction syndrome values ​​to a plurality of received CRC codewords. Alternatively, before the plurality of error correction syndrome values ​​are progressively updated, the plurality of error correction syndrome values ​​are initialized according to a plurality of received CRC codewords.

[0094] In some embodiments, the symbol position index value is determined by: forming a binary reciprocal of a first error correction syndrome value; and multiplying it by a second error correction syndrome value among the plurality of error correction syndrome values. In some embodiments, the binary reciprocal is formed by a lookup table (such as the lookup table in Appendix C).

[0095] In some embodiments, the first error correction syndrome is updated by performing a logical exclusive-OR operation on bits having a common bit position in each of the sequential groups of data bits.

[0096] In some embodiments, the selected set of data bits is modified by performing a bit-by-bit XOR operation on the selected set of data bits and the bit error correction mask to generate a set of error-corrected data bits. In some embodiments, the sequential sets of data bits are stored in a first register, the bit error correction mask is stored in a second register, and the set of error-corrected data bits is stored in a third register. In such embodiments, the symbol position index value may determine the storage location of the bit error correction mask in the second register.

[0097] It is easy for those skilled in the art to understand that the buffering and reformatting of data in the transmitter and receiver can be achieved by various methods known in the art, including random access memory storage, data latch group storage, or FIFO buffer unit storage. The conversion between the data codeword and the bit group of the transmission unit size can be facilitated by a digital multiplexer, shift register, barrel shifter, or dual-port storage structure as an independent unit or integrated with the above-mentioned storage unit. As mentioned above, although the above examples describe the data path width using CNRZ-5 transmission as an example, this example is only for illustrative purposes and does not constitute a limitation. Other data path widths and transmission media can also be used equally. Similarly, although the above is described as an example of a set of four processing stages used in both the transmitter and the receiver, the present invention is not limited to this. In other embodiments, more or fewer processing instances, including one, can also be used without restriction.

[0098] Appendix A: Asymptotic calculation of r0, r1

[0099] One implementation of the calculation of r0 and r1 is performed by executing the following sequence of operations, wherein the sequence of operations is organized so that the successive elements of the transmission data stream can be processed in the order of transmission and in a grouping manner, and the processing delay caused by these operations is pipelined or overlapped with the transmission.

[0100] In the following illustrative notation, r0[i] represents bit i of r0, and similarly, r1[i] represents bit i of r1. The index notation sequence inp[] represents the currently processed input data, where inp[0...4] are bits of m0, inp[5...9] are bits of m1, ..., inp[145...149] are bits of m29. Represents the Boolean exclusive OR operator.

[0101] r0=0; r1=0;

[0102]

[0103]

[0104]

[0105]

[0106]

[0107]

[0108]

[0109]

[0110] Appendix B - Error Correction

[0111] For a non-zero element r0″[0], ..., r0″[4] and another non-zero element r1″[0], ..., r1″[4] in a finite field GF(32) given in five-bit form, the following process is used to calculate the bit form of the element x=r1″ / r0″ in GF(32), i.e., bits x[0], ..., x[4]. In the following notation, represents the Boolean exclusive OR operator, and & represents the Boolean AND operator.

[0112] x[0] = r0"[0] & r1"[0];

[0113]

[0114]

[0115] x[1] = r0"[0] & r1"[1];

[0116]

[0117]

[0118]

[0119] x[2] = r0"[0] & r1"[3];

[0120]

[0121]

[0122] x[3] = r0"[0] & r1"[1];

[0123]

[0124]

[0125]

[0126] x[4] = r0"[0] & r1"[2];

[0127]

[0128]

[0129] Appendix C: Reciprocal Lookup Table

[0130] r0″ 1 / r0″ 00000 00000 00001 00001 00010 10010 00011 11100 00100 01001 00101 10111 00110 01110 00111 01100 01000 10110 01001 00100 01010 11001 01011 10000 01100 00111 01101 01111 01110 00110 01111 01101 10000 01011 10001 11000 10010 00010 10011 11101 10100 11110 10101 11010 10110 01000 10111 00101 11000 10001 11001 01010 11010 10101 11011 11111 11100 00011 11101 10011 11110 10100 11111 11011

Claims

1. A forward error correction method, characterized in that: include: sequentially receiving a plurality of data symbols and storing each data symbol as a group of bits in a corresponding register location; generating a first syndrome value by performing a bitwise exclusive-OR operation on the plurality of data symbols to generate a first pair of multi-bit check code words, the first syndrome value corresponding to a bit error correction mask of the data symbol having a bit error; The second syndrome value is generated by performing a bitwise XOR operation on the multiplied data symbols to generate a second pair of multi-bit check codewords, each data symbol being modulo-multiplied by a corresponding element a of the check matrix. j , the check matrix includes a finite field GF(2 n ) and consists of 2 rows, and the j-column elements of the check matrix are 1 and a j , where the element a j is a binary expansion of a symbol index integer value j, wherein the second syndrome value corresponds to a bit correction mask modulo multiplication of the data symbol having the bit error and a unique symbol position index value; Calculating the symbol position index value of the data symbol having the bit error by dividing the second syndrome value by the bit error correction mask; and A set of error-corrected output bits is generated by applying the bit error correction mask to a set of bits stored in a register location identified by the symbol position index value of the data symbol having the bit error.

2. The method according to claim 1, characterized in that Each syndrome value includes n bits, and the plurality of data symbols includes 2 n -2 data symbols.

3. The method according to claim 1, characterized in that Receiving the plurality of data symbols in sequence comprises receiving vector signaling codewords of a vector signaling code, wherein each of the vector signaling codewords is decoded by performing a corresponding linear combination operation of each of the vector signaling codewords defined by a corresponding subchannel among a plurality of mutually orthogonal subchannels.

4. The method according to claim 1, characterized in that Dividing the second syndrome value by the bit error correction mask includes forming a binary inverse of the bit error correction mask and modulo-multiplying the binary inverse of the bit error correction mask by the second syndrome value.

5. The method according to claim 4, characterized in that The binary inverse of the bit error correction mask is obtained from a lookup table.

6. The method according to claim 1, characterized in that The first and second pairs of multi-bit check codewords respectively include local multi-bit check codewords generated from the received plurality of data symbols.

7. The method according to claim 6, characterized in that The local multi-bit check codeword is progressively updated in response to each of the received plurality of data symbols.

8. The method according to claim 6, characterized in that The first and second pairs of multi-bit check codewords respectively include received multi-bit check codewords generated from a plurality of transmitted data symbols.

9. The method according to claim 8, characterized in that The first syndrome value is generated by comparing the local multi-bit check codeword of the first pair of multi-bit check codewords with the received multi-bit check codeword, and the second syndrome value is generated by comparing the local multi-bit check codeword of the second pair of multi-bit check codewords with the received multi-bit check codeword.

10. The method according to claim 1, characterized in that Applying the bit error correction mask to the set of bits in the register location includes performing a bitwise exclusive-OR operation on the set of bits in the register location with the bit error correction mask to generate the set of error-corrected output bits.

11. A forward error correction device, characterized in that: include: a register for sequentially receiving a plurality of data symbols and storing each data symbol as a group of bits in a corresponding register position; Forward Error Correction (FEC) circuitry for: generating a first syndrome value by performing a bitwise exclusive-OR operation on the plurality of data symbols to generate a first pair of multi-bit check code words, the first syndrome value corresponding to a bit error correction mask of the data symbol having a bit error; The second syndrome value is generated by performing a bitwise XOR operation on the multiplied data symbols to generate a second pair of multi-bit check codewords, each data symbol being modulo-multiplied by a corresponding element a of the check matrix. j , the check matrix includes a finite field GF(2 n ) and consists of 2 rows, and the j-column elements of the check matrix are 1 and a j , where the element a j is a binary expansion of a symbol index integer value j, wherein the second syndrome value corresponds to a bit correction mask modulo multiplication of the data symbol having the bit error and a unique symbol position index value; Calculating the symbol position index value of the data symbol having the bit error by dividing the second syndrome value by the bit error correction mask; and A set of error-corrected output bits is generated by applying the bit error correction mask to a set of bits stored in a register location identified by the symbol position index value of the data symbol having the bit error.

12. The device according to claim 11, characterized in that Each syndrome value includes n bits, and the plurality of data symbols includes 2 n -2 data symbols.

13. The device according to claim 11, characterized in that It includes a multi-input comparator for receiving vector signaling codewords of a vector signal code, and decoding each of the vector signaling codewords by implementing a corresponding linear combination operation of each vector signaling codeword defined by a corresponding subchannel among a plurality of mutually orthogonal subchannels.

14. The device according to claim 11, characterized in that The forward error correction circuit is configured to divide the second syndrome value by the bit error correction mask by forming a binary inverse of the bit error correction mask and modulo-multiplying the binary inverse of the bit error correction mask by the second syndrome value.

15. The device according to claim 14, characterized in that The forward error correction circuit includes a lookup table for receiving the bit error correction mask and outputting the binary inverse of the bit error correction mask.

16. The device according to claim 11, characterized in that The first and second pairs of multi-bit check codewords respectively include local multi-bit check codewords generated from the received plurality of data symbols.

17. The device according to claim 16, characterized in that The forward error correction circuit is used to progressively update the local multi-bit check codeword in response to receiving each data symbol of the plurality of data symbols.

18. The device according to claim 16, characterized in that The first and second pairs of multi-bit check codewords respectively include received multi-bit check codewords generated from a plurality of transmitted data symbols.

19. The device according to claim 18, characterized in that The forward error correction circuit is used to generate the first syndrome value by comparing the local multi-bit check codeword of the first pair of multi-bit check codewords with the received multi-bit check codeword, and to generate the second syndrome value by comparing the local multi-bit check codeword of the second pair of multi-bit check codewords with the received multi-bit check codeword.

20. The device according to claim 11, characterized in that The register being used to apply the bit error correction mask to a group of bits in the register position includes performing a bitwise exclusive-OR operation on the group of bits in the register position using the bit error correction mask to generate the group of error-corrected output bits.

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