A network on chip and data transmission method

Abstract

The present application discloses an on-chip network and a data transmission method. The on-chip network includes: a plurality of common nodes, forming a two-dimensional network, the common nodes are located at the intersection of grid lines in the two-dimensional network, and the common nodes are used for data forwarding; a plurality of load nodes are arranged on the grid lines or the extension lines of the grid lines in the two-dimensional network, and are used for data interaction with the connected loads. In this way, the uniformity of the load connected to the load nodes in the on-chip network can be improved, thereby improving the transmission efficiency of the on-chip network and improving the overall performance of the chip.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an on-chip network and a data transmission method. Background Art

[0002] The network-on-chip (NoC) is a new communication method for system-on-chip (SoC). It is a major component of multi-core technology. The NoC method brings a new on-chip communication method that significantly outperforms the performance of traditional bus systems. NoC-based systems can better adapt to the global asynchronous and local synchronous clock mechanism used in future complex multi-core SoC designs.

[0003] However, the structural uniformity of existing NoCs is poor. For example, the ports of the routers at the central nodes of existing NoCs are connected to the upper, lower, left, and right nodes and local devices respectively, and the structure is asymmetric, resulting in poor distribution uniformity of the NoC load. Summary of the invention

[0004] The main technical problem solved by the present application is to provide an on-chip network and a data transmission method to improve the uniformity of the load accessed by the on-chip network, thereby improving the on-chip network transmission efficiency and enhancing the overall performance of the chip.

[0005] In order to solve the above technical problems, a technical solution adopted by the present application is to provide a network on chip. The network on chip includes: a plurality of ordinary nodes, forming a two-dimensional network, the ordinary nodes are located at the intersection of grid lines in the two-dimensional network, and the ordinary nodes are used for data forwarding; a plurality of load nodes are arranged on the grid lines or the extension lines of the grid lines in the two-dimensional network, and are used for data interaction with the connected loads.

[0006] In a specific embodiment, both the common node and the load node include a router, and the router of the common node includes at least two first common ports, and the first common ports are connected to other common nodes or load nodes that are adjacently arranged.

[0007] In a specific embodiment, the router of the load node includes at least one second common port and at least one load port, the second common port is connected to the first common port of the adjacent common node or the load port of other load nodes, and the load port is connected to the load.

[0008] In a specific embodiment, the number of ports of the router is less than or equal to four.

[0009] In one embodiment, the grid of the two-dimensional network is a square grid.

[0010] In a specific embodiment, the number of first common ports of a common node is four.

[0011] In a specific embodiment, the number of second common ports of the load node located on the grid line is 2, and the number of load ports of the load node located on the grid line is 2; the number of second common ports of the load node located on the extension line is 1, and the number of load ports of the load node located on the extension line is 2.

[0012] In a specific embodiment, the number of second common ports of the load node located on the grid line is 2, and the number of load ports of the load node located on the grid line is 2; the number of second common ports of the load node located on the extension line is 1, and the number of load ports of the load node located on the extension line is 3.

[0013] In a specific embodiment, at least two load nodes are arranged in series between two common nodes.

[0014] In order to solve the above technical problems, another technical solution adopted by the present application is: to provide a data transmission method. The data transmission method is used for an on-chip network, and the on-chip network at least includes: a plurality of ordinary nodes and a plurality of load nodes, the plurality of ordinary nodes form a two-dimensional network, and are located at the intersection of grid lines in the two-dimensional network, and the plurality of load nodes are arranged on the grid lines in the two-dimensional network or on the extension lines of the grid lines, and the plurality of load nodes include a first load node and a second load node, and the data transmission method includes: a first load sends data to a first load node connected thereto; the first load node receives and parses the data to obtain a second load node for receiving the data; a data transmission path is generated between the first load node and the second load node; the data is transmitted to the second load node along the data transmission path; and the second load node distributes the received data to the second load connected thereto.

[0015] The beneficial effect of the present application is that, different from the prior art, the ordinary nodes used for data forwarding in the on-chip network of the present application are located at the intersection of grid lines, while the load nodes used for load data interaction are located on the grid lines or on the extension lines of the grid lines in the two-dimensional network formed by the ordinary nodes, so that the load nodes can be evenly distributed in and around the two-dimensional network to improve the uniformity of the load connected to the load nodes, thereby improving the transmission efficiency of the on-chip network and enhancing the overall performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 It is a structural diagram of an embodiment of an on-chip network of the present application;

[0018] Figure 2 yes Figure 1 A schematic diagram of the structure of the port structure of a router of a common node in an on-chip network of an embodiment;

[0019] Figure 3 yes Figure 1 A schematic diagram of the structure of the port structure of a router of a load node in a network on chip of an embodiment;

[0020] Figure 4 It is a structural diagram of an embodiment of an on-chip network of the present application;

[0021] Figure 5 It is a structural diagram of an embodiment of an on-chip network of the present application;

[0022] Figure 6 This is a flow chart of an embodiment of a data transmission method of the present application;

[0023] Figure 7 yes Figure 1 Embodiment Network on Chip based Figure 6 A schematic diagram of the state structure of the data transmission method of the embodiment. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0025] The terms "first" and "second" in this application are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically limited. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0026] This application first proposes a network on chip, such as Figures 1 to 3 As shown, Figure 1 It is a structural diagram of an embodiment of an on-chip network of the present application; Figure 2 yes Figure 1 A schematic diagram of the structure of the port structure of a router of a common node in an on-chip network of an embodiment; Figure 3 yes Figure 1 A schematic diagram of the structure of the port structure of the router of the load node in the on-chip network of the embodiment. The on-chip network 10 of the embodiment includes: a plurality of ordinary nodes a and a plurality of load nodes b; wherein the plurality of ordinary nodes a form a two-dimensional network, the ordinary nodes a are located at the intersection of the grid lines in the two-dimensional network, and the ordinary nodes a are used for data forwarding; and the plurality of load nodes b are arranged on the grid lines or the extension lines of the grid lines in the two-dimensional network, and are used for data interaction with the connected loads.

[0027] The load in this embodiment is a load IP (Internet Protocol), and the load IP refers to a load connected to the load node b through an IP address.

[0028] Different from the prior art, in this embodiment, the ordinary nodes used for data forwarding in the on-chip network 10 are located at the intersection of the grid lines, while the load nodes b used for load data interaction are located on the grid lines or on the extension lines of the grid lines in the two-dimensional network formed by the ordinary nodes a. This enables the load nodes b to be evenly distributed in and around the two-dimensional network to improve the uniformity of the load connected to the load nodes b, thereby improving the transmission efficiency of the on-chip network 10 and enhancing the overall performance of the chip.

[0029] Optionally, the ordinary node a and the load node b of this embodiment both include a router, and the router of the ordinary node a includes at least two first ordinary ports, and the first ordinary ports are connected to other ordinary nodes a or load nodes b arranged adjacent to it, so that the ordinary node a forwards data to other ordinary nodes a or load nodes b arranged adjacent to it.

[0030] The router of the common node a in this embodiment is provided with at least two first common ports to realize input and output during data forwarding.

[0031] Optionally, the router of load node b in this embodiment includes at least one second ordinary port and at least one load port, and the second ordinary port is connected to the first ordinary port of the adjacent ordinary node a or the load port of other load nodes b, wherein the load port of the router of load node b is connected to the load IP so as to exchange data between the load IP and the adjacent ordinary node a or other load nodes b.

[0032] In this embodiment, the load node b is provided with at least one first common port and at least one first load node to realize input and output during data interaction.

[0033] Optionally, the number of ports of the router of the common node a and the number of ports of the router of the load node b in this embodiment are both less than or equal to 4. However, the number of ports of the router of the central node of the traditional on-chip network is at least 5, which are respectively connected to the upper, lower, left, and right nodes and local devices, and the number of ports is large, and the node area is large. Therefore, the number of ports of the router of this embodiment is less than or equal to 4, which can reduce the number of ports of the router at the common node a and the load node b, and can reduce the area of ​​the node, thereby reducing the area of ​​the on-chip network, or can increase the reserved area to increase the capacity of the load IP.

[0034] Optionally, the grid of the two-dimensional network in this embodiment is a square grid, which can improve the symmetry of the on-chip network and the uniformity of node distribution, so as to improve the uniformity of the load accessed by the load nodes, thereby improving the transmission efficiency of the on-chip network 10 and improving the overall performance of the chip.

[0035] Specifically, the number of ports of the router of the common node a in this embodiment is 4, that is, the number of the first common ports is 4 (eg Figure 2 As shown), it is used to connect to four load nodes b arranged adjacent to it respectively; in this embodiment, the number of ports of the router of the load node b located on the grid line is 4, including two second common ports and two load ports (such as Figure 3 As shown), the two second ordinary ports are respectively connected to the two ordinary nodes a, and the two load ports are respectively connected to the two load IPs; in this embodiment, the number of ports of the router of the load node b located on the extension line is 3, including one second ordinary port and the number of two load ports is 2, one second ordinary port is connected to the ordinary node a, and the two load ports are respectively connected to the two load IPs.

[0036] From the above analysis, it can be seen that the structure of the router of each ordinary node a in the on-chip network of this embodiment is exactly the same, and the replication of the ordinary node a can be achieved; the structure of the router of each load node b located on the extension line of the grid line is exactly the same, and the replication of this type of load node b can be achieved; the structure of the router of each load node b located on the grid line is exactly the same, and the replication of this type of node can be achieved.

[0037] The upper, lower, left and right sides of the common node a in this embodiment are respectively connected to the load node b, and each load node b is connected to two load IPs, which can further improve the uniformity of the distribution of the load IPs accessed by the on-chip network 10, thereby improving the transmission efficiency of the on-chip network 10 and enhancing the overall performance of the chip.

[0038] Compared with the asymmetric structure of a traditional on-chip network, the on-chip network 10 of this embodiment has better structural symmetry, which can avoid the use of full manual design, thereby reducing the workload.

[0039] In another embodiment, if Figure 4 As shown, Figure 4 1 is a schematic diagram of the structure of the second embodiment of the on-chip network of the present application. The difference between the on-chip network 40 of the present embodiment and the on-chip network 10 of the above embodiment is that: in the on-chip network 40 of the present embodiment, the number of second common ports of the load node b located on the grid line is 2, and the number of load ports of the load node b located on the grid line is 2; while the number of second common ports of the load node b located on the extended line of the grid line is 1, and the number of load ports of the load node b located on the extended line of the grid line is 3.

[0040] This structure can increase the number of load ports of the load node b, increase the number of load IPs accessed by the on-chip network 40, and increase its load capacity.

[0041] In this embodiment, the number of ports of the router of the common node a and the router of the load node b are both 4; in other embodiments, the number of ports of the router of the common node and the router of the load node may be less than 4. For example, the router of the common node includes two first common ports, which are respectively connected to two load nodes adjacent to the left and right or adjacent to the top and bottom. The router of the load node includes two second common nodes and one common node, and so on.

[0042] In another embodiment, if Figure 5 As shown, Figure 5 The difference between the on-chip network 50 of this embodiment and the on-chip network 10 of the above embodiment is that two load nodes b are set in series between the two ordinary nodes a of this embodiment to increase the number of load IPs connected to the on-chip network 50 and increase its load capacity.

[0043] In other embodiments, multiple load nodes may be connected in series between two common nodes, and the specific configuration may be based on the load capacity of the on-chip network.

[0044] from Figure 5 It can be seen that the structure of the router of each ordinary node a in the on-chip network 50 of this embodiment is exactly the same, so the replication of the ordinary node a can be achieved; the structure of the router of each load node b located on the extension line of the grid line is exactly the same, so the replication of this type of load node b can be achieved; the structure of the router of each load node b located on the grid line is exactly the same, so the replication of this type of node can be achieved; therefore, the design workload of the on-chip network 50 can be reduced.

[0045] Each common node a and its adjacent load node b form a grid unit (such as Figure 5The structure of the common node a and the four load nodes b adjacent to it is the same, so the entire grid unit can be copied, which can further reduce the design workload of the on-chip network 50.

[0046] In the above embodiments of the present application, the number of ports of the router of the ordinary node and the number of ports of the router of the load node are both less than or equal to 4. Of course, in other embodiments, the number of ports of the router of the ordinary node may be greater than 4 and / or the number of ports of the router of the load node may be greater than 4.

[0047] In other embodiments, the grid of the two-dimensional network formed by the common nodes of the on-chip network of the present application may also be arranged in the shape of a regular hexagon or a regular triangle.

[0048] It should be pointed out that various other shapes of two-dimensional networks, other numbers of router ports at each node in the two-dimensional network, and other connection methods between ordinary nodes and load nodes in the two-dimensional network all fall within the protection scope of this application.

[0049] This application further proposes a data transmission method, such as Figure 6 As shown, Figure 6 It is a flow chart of an embodiment of the data transmission method of the present application. The data transmission method of this embodiment can be used for an on-chip network, which at least includes: a plurality of ordinary nodes and a plurality of load nodes, the plurality of ordinary nodes form a two-dimensional network, and are located at the intersection of grid lines in the two-dimensional network, a plurality of load nodes are arranged on the grid lines in the two-dimensional network or on the extension lines of the grid lines, and the plurality of load nodes include a first load node and a second load node; wherein the first load node is a source load node, that is, a load node connected to the source load IP; the second load node is a target load node, that is, a load node connected to the target load IP.

[0050] The on-chip network in this embodiment can refer to the on-chip network in the above embodiment, which will not be described in detail here.

[0051] The data transmission method of this embodiment specifically includes the following steps:

[0052] Step S61: The first load sends data to the first load node connected to it.

[0053] like Figure 7 As shown, in an application scenario, the first load IP1 sends data to the first load node b1 connected thereto.

[0054] Step S62: The first load node receives and parses the data to obtain a second load node for receiving the data.

[0055] The first load node b1 receives the data sent by the first load IP1, parses the data, and obtains information such as the address of the second load node b3 for receiving the data.

[0056] Step S63: Generate a data transmission path between the first load node and the second load node.

[0057] A data transmission path (such as a data transmission path between the first load node b1 and the second load node b3) is generated based on data information, nodes in the two-dimensional network, the current global link status and congestion information, etc. Figure 7 (shown by the dashed line).

[0058] Step S64: Transmit the data to the second load node along the data transmission path.

[0059] The data received by the first load node b1 is transmitted along the data transmission path through the common node a1, the load node b2, the common node a2 to the second load node b3.

[0060] Step S65: The second load node distributes the received data to the loads connected thereto.

[0061] The second load node b3 receives the data, parses the data, obtains information such as the address of the target load IP2, and distributes the data to the target load IP2 according to the address information.

[0062] Different from the prior art, the on-chip network of the present application includes: a plurality of ordinary nodes, forming a two-dimensional network, the ordinary nodes are located at the intersection of the grid lines in the two-dimensional network, and the ordinary nodes are used for data forwarding; a plurality of load nodes are arranged on the grid lines or the extension lines of the grid lines in the two-dimensional network, and are used for data interaction with the connected loads. In this way, the ordinary nodes used for data forwarding in the on-chip network of the present application are located at the intersection of the grid lines, and the load nodes used for data interaction with the loads are located on the grid lines or the extension lines of the grid lines in the two-dimensional network formed by the ordinary nodes, so that the load nodes can be evenly distributed in and around the two-dimensional network, so as to improve the uniformity of the loads connected to the load nodes, thereby improving the transmission efficiency of the on-chip network and improving the overall performance of the chip.

[0063] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A network on chip, characterized in that: include: A plurality of common nodes form a two-dimensional network, wherein the common nodes are located at intersections of grid lines in the two-dimensional network, and the common nodes are used for data forwarding; A plurality of load nodes are arranged on the grid lines or extension lines of the grid lines in the two-dimensional network, and are used for data exchange with connected loads.

2. The network on chip according to claim 1, characterized in that: The common node and the load node both include a router, and the router of the common node includes at least two first common ports, and the first common ports are connected to other common nodes or load nodes that are adjacently arranged.

3. The network on chip according to claim 2, characterized in that: The router of the load node includes at least one second common port and at least one load port, the second common port is connected to the first common port of the adjacent common node or the load port of other load nodes, and the load port is connected to the load.

4. The network on chip according to claim 3, characterized in that: The number of ports of the router is less than or equal to 4.

5. The network on chip according to claim 4, characterized in that: The grid of the two-dimensional network is a square grid.

6. The network on chip according to claim 5, characterized in that: The number of the first common ports of the common node is 4.

7. The network on chip according to claim 6, characterized in that: The number of the second common ports of the load node located on the grid line is 2, and the number of the load ports of the load node located on the grid line is 2; The number of the second common ports of the load node located on the extension line is 1, and the number of the load ports of the load node located on the extension line is 2.

8. The network on chip according to claim 6, characterized in that: The number of the second common ports of the load node located on the grid line is 2, and the number of the load ports of the load node located on the grid line is 2; The number of the second common ports of the load node located on the extension line is 1, and the number of the load ports of the load node located on the extension line is 3.

9. The network on chip according to any one of claims 1 to 8, characterized in that: At least two load nodes are arranged in series between two common nodes.

10. A data transmission method, characterized in that: For an on-chip network, the on-chip network at least includes: a plurality of common nodes and a plurality of load nodes, the plurality of common nodes form a two-dimensional network and are located at the intersection of grid lines in the two-dimensional network, a plurality of load nodes are arranged on the grid lines in the two-dimensional network or on the extension lines of the grid lines, the plurality of load nodes include a first load node and a second load node, and the data transmission method includes: The first load sends data to the first load node connected thereto; The first load node receives and parses the data to obtain a second load node for receiving the data; generating a data transmission path between the first load node and the second load node; transmitting the data to the second load node along the data transmission path; The second load node distributes the received data to the second load connected thereto.

Images