A display panel, a detection method thereof and a display device

Abstract

The present invention discloses a display panel, a detection method thereof and a display device. In a short-circuit bar structure in the display panel, a first circuit unit and a second circuit unit share a first transmission signal line, so as to transmit signals to the first circuit unit and the second circuit unit respectively through the first transmission signal line. And by setting the first transmission signal line between the first circuit unit and the second circuit unit, only one transmission signal line among a plurality of transmission signal lines, namely the first transmission signal line, is set between the first circuit unit and the second circuit unit. In this way, the difference between the resistance between the first circuit unit and the fan-out line and the resistance between the second circuit unit and the fan-out line is reduced, so that the difference in voltage input to the same color sub-pixels of different columns can be reduced, thereby improving the problem of vertical stripes appearing on pure color pictures and improving the display effect of pure color pictures.

Description

[0001] This application is a divisional application. The application number of the original application is 201911348638.3, and the original application date is December 24, 2019. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a display panel, a detection method thereof, and a display device. Background Art

[0003] With the continuous development of display technology, the application scope of display panels is becoming more and more extensive, and people's requirements for display panels are also getting higher and higher. In particular, the display quality of display panels has always been one of the important indicators for consumers and panel manufacturers to measure the quality of display panels. Therefore, how to test display panels is a technical problem that technicians in this field need to solve urgently. Summary of the invention

[0004] The embodiments of the present invention provide a display panel, a detection method thereof and a display device, so as to improve the display effect.

[0005] An embodiment of the present invention provides a display panel, comprising: a substrate having a display area and a non-display area; the non-display area comprises: a fan-out area and a binding area;

[0006] The fan-out area includes: a plurality of fan-out lines; and the fan-out area is arranged between the display area and the binding area;

[0007] The binding area includes: a shorting bar structure and a plurality of input terminals; wherein one of the input terminals is electrically connected to a fan-out line;

[0008] The shorting bar structure comprises: a plurality of transmission signal lines extending along a first direction, a plurality of output lines extending along a second direction, and a first circuit unit, a second circuit unit and a third circuit unit arranged along the second direction; wherein the first circuit unit, the second circuit unit and the third circuit unit are electrically connected to different output lines respectively; and one output line is electrically connected to one input terminal;

[0009] The plurality of transmission signal lines include: a first transmission signal line; wherein the first circuit unit and the second circuit unit share one first transmission signal line, and the first transmission signal line is arranged between the first circuit unit and the second circuit unit.

[0010] An embodiment of the present invention further provides a display device, comprising the above-mentioned display panel.

[0011] An embodiment of the present invention further provides a method for detecting a display panel, comprising:

[0012] When the display panel displays a pure color picture, lighting up the sub-pixels of the corresponding colors;

[0013] Wherein, a bright state signal is loaded on the first transmission signal line, a dark state signal is loaded on the second transmission signal line and the third transmission signal line respectively, and corresponding control signals are loaded on the first control signal line to the fifth control signal line respectively, so as to light up the first color sub-pixel or the third color sub-pixel;

[0014] A dark state signal is loaded onto the first transmission signal line and the second transmission signal line, a bright state signal is loaded onto the third transmission signal line, and corresponding control signals are loaded onto the first control signal line to the fifth control signal line, respectively, to light up the second color sub-pixel.

[0015] The beneficial effects of the present invention are as follows:

[0016] The display panel, the detection method and the display device provided by the embodiment of the present invention, the short-circuit bar structure in the display panel has a first circuit unit, a second circuit unit and a third circuit unit arranged in sequence along the second direction, and the first circuit unit and the second circuit unit share a first transmission signal line, so that the first transmission signal line can transmit signals to the first circuit unit and the second circuit unit respectively. And by setting the first transmission signal line between the first circuit unit and the second circuit unit, only one transmission signal line among multiple transmission signal lines, namely the first transmission signal line, can be set between the first circuit unit and the second circuit unit. In this way, the difference between the resistance between the first circuit unit and the fan-out line and the resistance between the second circuit unit and the fan-out line is reduced, and the difference between the RC loading between the first circuit unit and the fan-out line and the RC loading between the second circuit unit and the fan-out line is reduced, so that the difference in voltage input to the same color sub-pixels in different columns can be reduced, thereby improving the problem of vertical stripes in pure color pictures and improving the display effect of pure color pictures. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of the structure of a display panel in the related art;

[0018] Figure 2 is a schematic diagram of a specific structure of a display panel in the related art;

[0019] Figure 3 for Figure 2 The signal timing diagram corresponding to the display panel shown;

[0020] Figure 4 for Figure 2 The schematic diagram of the layout structure corresponding to the display panel shown;

[0021] Figure 5 is a schematic structural diagram of a display panel in an embodiment of the present invention;

[0022] Figure 6 is a schematic diagram of a specific structure of a display panel in an embodiment of the present invention;

[0023] Figure 7 is a schematic diagram of a specific structure of another display panel in an embodiment of the present invention;

[0024] Figure 8 is a schematic diagram of a specific structure of another display panel in an embodiment of the present invention;

[0025] Fig. 9 for Figure 8 The schematic diagram of the layout structure corresponding to the display panel shown;

[0026] Fig.10 is a schematic diagram of a specific structure of another display panel in an embodiment of the present invention;

[0027] Fig.11 is a flow chart of a method for detecting a display panel in an embodiment of the present invention;

[0028] Fig.12 is a signal timing diagram corresponding to the display panel in an embodiment of the present invention;

[0029] Fig.13 is a flow chart of another display panel detection method in an embodiment of the present invention;

[0030] Fig.14 is another signal timing diagram corresponding to the display panel in the embodiment of the present invention;

[0031] Fig.15 Schematic diagram of the structure of a display device in an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. And in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

[0033] Unless otherwise defined, the technical or scientific terms used in the present invention shall have the usual meanings understood by persons with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0034] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, but are only intended to illustrate the content of the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0035] After the display panel is prepared, a visual test (VT) is generally performed. During the VT test, a data signal is usually input to the display panel through a short-circuit bar structure to achieve the display of a pure color picture. Generally, the short-circuit bar structure can be set in the fan-out area of ​​the display panel. However, the wiring distribution in the fan-out area is very dense, so that the short-circuit bar structure will cause signal interference to the wiring of the fan-out line. In order to improve the interference of the short-circuit bar structure on the wiring in the fan-out area, the short-circuit bar structure can be set in the binding area of ​​the display panel.

[0036] Combination Figure 1 and Figure 2 As shown, the display panel may include a display area A1, a fan-out area A2, and a binding area A3; wherein the display area A1 may have a plurality of data lines 10, a plurality of gate lines GA, a plurality of red sub-pixels R, a plurality of green sub-pixels G, and a plurality of blue sub-pixels B. The fan-out area A2 may have a plurality of fan-out lines 20. The binding area A3 has a plurality of input terminals 30 and a shorting bar structure 40. wherein one data line 10 is electrically connected to one fan-out line 20, one fan-out line 20 is electrically connected to one input terminal 30, and the shorting bar structure 40 is electrically connected to each input terminal 30, respectively. That is, the shorting bar structure 40 is electrically connected to the data line 10 through the input terminal 30 and the fan-out line 20.

[0037] like Figure 2As shown, the shorting bar structure 40 may include: control lines CW1, CW2 and CW3, transmission lines CR-1, CR-2, CB-1, CB-2, CG, multiple transistors M01, multiple transistors M02, multiple transistors M03, multiple transistors M04, and multiple transistors M05. Among them, one transistor M01 and one transistor M02 are electrically connected to one data line 10, one transistor M03 is electrically connected to one data line 10, and one transistor M04 and one transistor M05 are electrically connected to one data line 10.

[0038] The gates of all transistors M01 and all transistors M04 are connected to a control line CW1 , the gates of all transistors M02 and all transistors M05 are connected to a control line CW2 , and the gates of all transistors M03 are connected to a control line CW3 .

[0039] A first electrode of each transistor M01 is electrically connected to the transmission line CR- 1 , and a second electrode of each transistor M01 is electrically connected to the corresponding data line 10 .

[0040] A first electrode of each transistor M02 is electrically connected to the transmission line CB- 1 , and a second electrode of each transistor M02 is electrically connected to the corresponding data line 10 .

[0041] A first electrode of each transistor M03 is electrically connected to the transmission line CG, and a second electrode of each transistor M03 is electrically connected to the corresponding data line 10 .

[0042] A first electrode of each transistor M04 is electrically connected to the transmission line CB- 2 , and a second electrode of each transistor M04 is electrically connected to the corresponding data line 10 .

[0043] A first electrode of each transistor M05 is electrically connected to the transmission line CR- 2 , and a second electrode of each transistor M05 is electrically connected to the corresponding data line 10 .

[0044] The transistors M01 - M05 may be N-type transistors.

[0045] Figure 2 The signal timing diagram corresponding to the shorting bar structure 40 in the display panel shown in FIG. Figure 3 As shown. Among them, Figure 3 In the figure, cw1 represents the signal transmitted on the control line CW1, cw2 represents the signal transmitted on the control line CW2, and the control line CW3 transmits a high-level signal with a fixed voltage. ga1 represents the signal transmitted on the gate line GA electrically connected to the first row of sub-pixels, and ga2 represents the signal transmitted on the gate line GA electrically connected to the second row of sub-pixels.

[0046] An example of using the shorting bar structure 40 to input a data signal to a display panel so that the display panel displays a red image is described.

[0047] In the t01 phase, the signal ga1 is a high-level signal, and the thin film transistors (TFTs) in the first row of sub-pixels are turned on. The signal ga2 is a low-level signal, and the thin film transistors in the second row of sub-pixels are turned off. Since the signal cw2 is a low-level signal, all transistors M02 and all transistors M05 are turned off. A dark state signal (e.g., 6V) is loaded on the transmission line CG, and a high-level signal with a fixed voltage is transmitted on the control line CW3, so that all transistors M03 are turned on to provide the dark state signal to the data line electrically connected to the green sub-pixel, so that the green sub-pixel in the first row inputs the dark state signal, thereby making the green sub-pixel non-luminous. Since the signal cw1 is a high-level signal, all transistors M01 and all transistors M04 are turned on. A dark state signal is loaded on the transmission line CB-2, and the dark state signal is provided to the corresponding data line through the turned-on transistor M04, so that the blue sub-pixel in the first row inputs the dark state signal, thereby making the blue sub-pixel non-luminous. A bright state signal (eg, a 3V bright state signal) is loaded onto the transmission line CR-1, and the bright state signal is provided to the corresponding data line through the turned-on transistor M01, so that the red sub-pixels in the first row are input with the bright state signal, thereby causing the red sub-pixels to emit light to display red.

[0048] In the t02 phase, the signal ga1 is a low-level signal, and the thin film transistors in the first row of sub-pixels are turned off. The signal ga2 is a high-level signal, and the thin film transistors in the second row of sub-pixels are turned on. Since the signal cw1 is a low-level signal, all transistors M01 and all transistors M04 are turned off. A dark state signal is loaded on the transmission line CG, and a high-level signal of a fixed voltage is transmitted on the control line CW3, so that all transistors M03 are turned on to provide the dark state signal to the data line electrically connected to the green sub-pixel, so that the green sub-pixel in the second row inputs the dark state signal, and then the green sub-pixel does not emit light. Since the signal cw2 is a high-level signal, all transistors M02 and all transistors M05 are turned on. A bright state signal (for example, a bright state signal of 3V) is loaded on the transmission line CR-2, and the bright state signal is provided to the corresponding data line through the turned-on transistor M04, so that the red sub-pixel in the second row inputs the bright state signal, and then the red sub-pixel emits light to display red. A dark state signal is loaded on the transmission line CB-1, and the dark state signal is provided to the corresponding data line through the turned-on transistor M02, so that the blue sub-pixels in the second row are input with the dark state signal, thereby making the blue sub-pixels non-luminescent.

[0049] Similarly, the remaining processes can be deduced by analogy, so that all red sub-pixels in the display panel emit light, while green sub-pixels and blue sub-pixels do not emit light, so that the display panel can display a pure red picture. It should be noted that the working process of making the display panel display green and blue pictures can also be deduced by analogy, which is not repeated here.

[0050] Figure 2 The schematic diagram of the layout of the shorting bar structure is shown in FIG. Figure 4 As shown. Combined Figure 1 and Figure 4 As shown, in the direction F2 from the fan-out area A2 to the binding area A3, the transmission line CR-2, the control line CW2-1, the control line CW1-1, the transmission line CB-2, the control line CW3, the transmission line CG, the transmission line CB-1, the control line CW2-2, the control line CW1-2, and the transmission line CR-1 are arranged in sequence. Among them, the control line CW2-1 and the control line CW2-2 are electrically connected to each other to form the control line CW2, and the control line CW1-1 and the control line CW1-2 are electrically connected to each other to form the control line CW1.

[0051] Furthermore, all transistors M05 are located between the transmission line CR-2 and the control line CW1-1, all transistors M04 are located between the transmission line CB-2 and the control line CW2-1, all transistors M03 are located between the transmission line CB-2 and the transmission line CG, all transistors M02 are located between the transmission line CB-1 and the control line CW1-2, and all transistors M01 are located between the transmission line CR-1 and the control line CW2-2.

[0052] pass Figure 4 It can be seen that a transmission line CR-2 is set between the transistor M05 and the fan-out line 20, and transmission lines: CR-2, CB-2, CG and CB-1 are set between the transistor M01 and the fan-out line 20, a total of four transmission lines, that is, transmission lines: CB-2, CG and CB-1 are set between the transistor M05 and the transistor M01, a total of three transmission lines. In practical applications, in order to facilitate signal transmission and reduce the resistance of the transmission line, the transmission line is generally set to be wider, so that the distance between the transistor M01 and the fan-out line 20 is longer than the distance between the transistor M05 and the fan-out line 20, resulting in the resistance between the transistor M01 and the fan-out line 20 being greater than the resistance between the transistor M05 and the fan-out line 20, which causes the load (RC Loading) between the transistor M01 and the fan-out line 20 to be greater than the load between the transistor M05 and the fan-out line 20, so that the voltage input to the red sub-pixel in the t01 stage may be less than the voltage input to the red sub-pixel in the t02 stage, which will cause the luminous brightness of the red sub-pixels in different columns to be different, thereby causing the problem of vertical stripes in the red picture.

[0053] It should be noted that when the display panel displays a blue image, the above-mentioned problem of displaying a red image will also occur. The principle is the same and will not be elaborated here.

[0054] Since the shorting bar structure enables the display panel to display a pure color image, it is generally used to detect the quality of the display panel during the VT test stage. If vertical stripes appear when the display panel displays a pure color image through the shorting bar structure during the VT test, the display panel will be classified as a defective product. However, if the display panel has no other defects and is only due to Figure 4 The short-circuit bar structure shown causes vertical stripes to appear in a solid color image, which results in a waste of resources and increased costs.

[0055] Based on this, an embodiment of the present invention provides a display panel that can improve the problem of vertical stripes appearing in a pure color picture due to a shorting bar structure.

[0056] An embodiment of the present invention provides a display panel, such as Figures 5 to 9 As shown, it may include: a substrate having a display area AA and a non-display area BB; the non-display area BB includes: a fan-out area B1 and a binding area B2;

[0057] The fan-out area B1 includes: a plurality of fan-out lines 120; and the fan-out area B1 is disposed between the display area AA and the binding area B2;

[0058] The binding area B2 includes: a shorting bar structure 140 and a plurality of input terminals 130; wherein one input terminal 130 is electrically connected to one fan-out line 120;

[0059] The shorting bar structure 140 includes: a plurality of transmission signal lines extending along a first direction F1, a plurality of output lines 150 extending along a second direction F2, and a first circuit unit 140-1, a second circuit unit 140-2, and a third circuit unit 140-3 arranged along the second direction F2; wherein the first circuit unit 140-1, the second circuit unit 140-2, and the third circuit unit 140-3 are electrically connected to different output lines 150 respectively; and one output line 150 is electrically connected to one input terminal 130;

[0060] The plurality of transmission signal lines include: a first transmission signal line S1; wherein the first circuit unit 140-1 and the second circuit unit 140-2 share one first transmission signal line S1, and the first transmission signal line S1 is disposed between the first circuit unit 140-1 and the second circuit unit 140-2.

[0061] The display panel provided by the embodiment of the present invention has a short-circuit bar structure in the display panel having a first circuit unit, a second circuit unit and a third circuit unit arranged in sequence along a second direction, and the first circuit unit and the second circuit unit share a first transmission signal line, so that signals can be transmitted to the first circuit unit and the second circuit unit respectively through the first transmission signal line. And by setting the first transmission signal line between the first circuit unit and the second circuit unit, only one transmission signal line among multiple transmission signal lines, namely the first transmission signal line, can be set between the first circuit unit and the second circuit unit. In this way, the difference between the resistance between the first circuit unit and the fan-out line and the resistance between the second circuit unit and the fan-out line is reduced, and the difference between the RC loading between the first circuit unit and the fan-out line and the RC loading between the second circuit unit and the fan-out line is reduced, so that the difference in voltage input to the same color sub-pixels in different columns can be reduced, thereby improving the problem of vertical stripes appearing in pure color pictures and improving the display effect of pure color pictures.

[0062] In the specific implementation, in the embodiment of the present invention, combined with Figures 5 to 8 As shown, the display area AA may also include a plurality of sub-pixels arranged in an array and a plurality of display drive signal lines extending along the second direction F2; a column of sub-pixels is electrically connected to a display drive signal line, and a fan-out line 120 is electrically connected to at least one display drive signal line. Exemplarily, the display drive signal line may include a data line 110 for transmitting a data signal; wherein a data line 110 is electrically connected to a column of sub-pixels. A data line 110 is electrically connected to an input terminal 130. Furthermore, the short-circuit bar structure 140 is electrically connected to a plurality of input terminals 130, respectively, an input terminal 130 is electrically connected to a fan-out line 120, and a fan-out line 120 is electrically connected to a data line 110. That is, the short-circuit bar structure 140 is electrically connected to a plurality of data lines 110, respectively.

[0063] Exemplarily, the above-mentioned sub-pixel may include a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light. Among them, the light-emitting device may include: 18, at least one of an organic light-emitting diode (OLED), and a quantum dot light-emitting diode (QLED). In addition, a general pixel driving circuit may include a plurality of transistors such as a driving transistor and a switching transistor, and a storage capacitor, and its specific structure and working principle may be the same as those in the related art, and will not be repeated here.

[0064] Exemplarily, the plurality of sub-pixels may include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The first color, the second color, and the third color may be selected from red, green, and blue, and are not limited thereto. For example, the first color may be set to red, the second color may be set to green, and the third color may be set to blue, so that the display panel may display a red pure color picture, a green pure color picture, and a blue pure color picture. Furthermore, when displaying a color image, the display panel may also display the image in a red, green, and blue color mixing manner.

[0065] In the specific implementation, in the embodiment of the present invention, as Figures 6 to 8 As shown, the 3n-2nd column sub-pixel and the 3nth column sub-pixel respectively include the first color sub-pixel and the third color sub-pixel arranged alternately, and the arrangement order of the first color sub-pixel and the third color sub-pixel in the 3n-2nd column sub-pixel and the 3nth column sub-pixel is opposite; and the 3n-1st column sub-pixel includes the second color sub-pixel arranged in sequence. Wherein, n is an integer. It should be noted that display panels with different resolutions have different requirements for the number of sub-pixels, so the specific value of n can be designed and determined according to the actual application environment, and is not limited here.

[0066] For example, in a specific implementation, in an embodiment of the present invention, Figures 6 to 8 As shown, in the 3n-2 column of sub-pixels, the odd-numbered rows can be set as the first color sub-pixels, and the even-numbered rows can be set as the third color sub-pixels. In the 3n column of sub-pixels, the odd-numbered rows are the third color sub-pixels, and the even-numbered rows are the first color sub-pixels. The following is an example of the first color sub-pixel being a red sub-pixel R, the second color sub-pixel being a green sub-pixel G, and the third color sub-pixel being a blue sub-pixel B. For example, Figures 6 to 8 As shown, taking n=1 and n=2 as examples, along the direction indicated by the arrow of the first direction F1, there are the 1st column of sub-pixels, the 2nd column of sub-pixels, the 3rd column of sub-pixels, the 4th column of sub-pixels, the 5th column of sub-pixels, and the 6th column of sub-pixels. The arrangement of sub-pixels in the 1st column of sub-pixels and the 4th column of sub-pixels is the same, the arrangement of sub-pixels in the 2nd column of sub-pixels and the 5th column of sub-pixels is the same, and the arrangement of sub-pixels in the 3rd column of sub-pixels and the 6th column of sub-pixels is the same. Among them, in the 1st column of sub-pixels, the odd-numbered rows of sub-pixels are red sub-pixels R, and the even-numbered rows of sub-pixels are blue sub-pixels B. Each sub-pixel in the 2nd column of sub-pixels is a green sub-pixel G. In the 3rd column of sub-pixels, the odd-numbered rows of sub-pixels are blue sub-pixels B, and the even-numbered rows of sub-pixels are red sub-pixels R. Of course, in actual applications, the arrangement of the above-mentioned sub-pixels of each color can also be designed and determined according to the actual application environment, which is not limited here.

[0067] In the specific implementation, in the embodiment of the present invention, as Figures 6 to 8As shown, the first circuit unit 140-1 is close to the display area AA, the third circuit unit 140-3 is located on the side of the first circuit unit 140-1 away from the display area AA, and the second circuit unit 140-2 is located between the first circuit unit 140-1 and the second circuit unit 140-2. In this way, the first circuit unit 140-1, the second circuit unit 140-2 and the third circuit unit 140-3 can be arranged in sequence along the direction indicated by the arrow of the first direction F1. In addition, the third circuit unit can correspond to a column of sub-pixels of the same color, so that it is not necessary to input a switching signal to the third transmission signal line. Since it does not need to input a switching signal, the third circuit unit can be set at the bottom of the display panel, so that space can be avoided, so that the first circuit unit and the second circuit unit can be reasonably set in the avoided space.

[0068] In specific implementation, in the embodiment of the present invention, as Figures 6 to 9 As shown, the plurality of transmission signal lines may further include: a second transmission signal line S2 and a third transmission signal line S3. The second transmission signal line S2 includes: a first sub-transmission signal line S2-1 and a second sub-transmission signal line S2-2; wherein the first sub-transmission signal line S2-1 is electrically connected to the first circuit unit 140-1, and the second sub-transmission signal line S2-2 is electrically connected to the second circuit unit 140-2; wherein the first sub-transmission signal line S2-1 is located on the side of the first circuit unit 140-1 away from the first transmission signal line S1, and the second sub-transmission signal line S2-2 is located between the second circuit unit 140-2 and the third circuit unit 140-3. In this way, data signals can be transmitted to the first circuit unit 140-1 through the first sub-transmission signal line S2-1, and data signals can also be transmitted to the second circuit unit 140-2 through the second sub-transmission signal line S2-2. Furthermore, by locating the first sub-transmission signal line S2-1 on the side of the first circuit unit 140-1 away from the first transmission signal line S1, and locating the second sub-transmission signal line S2-2 between the second circuit unit 140-2 and the third circuit unit 140-3, only one first transmission signal line S1 is set between the first circuit unit 140-1 and the second circuit unit 140-2, and no other transmission signal lines are set.

[0069] In specific implementation, in the embodiment of the present invention, as Figures 6 to 9 As shown, the third transmission signal line S3 may be electrically connected to the third circuit unit 140-3, so that the data signal may be transmitted to the third circuit unit 140-3 through the third transmission signal line S3.

[0070] For example, in a specific implementation, in an embodiment of the present invention, Figures 6 to 9As shown, the third transmission signal line S3 can be located at the side of the third circuit unit 140-3 away from the second circuit unit 140-2. In this way, the third circuit unit 140-3 can be kept away from the edge of the substrate, thereby avoiding damage to the third circuit unit 140-3 when the substrate is cut. In addition, the third transmission signal line S3 can be used as an electrode for shielding static electricity, thereby avoiding static electricity interference to the third circuit unit 140-3 caused by static electricity around the display panel.

[0071] For example, in a specific implementation, in the embodiment of the present invention, the third transmission signal line S3 may be located between the third circuit unit 140-3 and the second sub-transmission signal line S2-2. In this way, the third transmission signal line S3 and the second sub-transmission signal line S2-2 can be designed to be closer, which is beneficial to the wiring design and reduces the difficulty of process preparation.

[0072] For example, in a specific implementation, in an embodiment of the present invention, Figures 6 to 8 As shown, the first circuit unit 140-1 may include: a plurality of first sub-circuit units 141, a first control signal line SW1, and a second control signal line SW2; wherein one first sub-circuit unit 141 corresponds to a column of sub-pixels in the 3nth column of sub-pixels, and the output line 150 corresponding to the first sub-circuit unit 141 is electrically connected to the display drive signal line of the corresponding column of sub-pixels. Exemplarily, the 3rd column of sub-pixels corresponds to one first sub-circuit unit 141, and the output line 150 corresponding to the first sub-circuit unit 141 is electrically connected to the data line 110 corresponding to the 3rd column of sub-pixels. The 6th column of sub-pixels corresponds to one first sub-circuit unit 141, and the output line 150 corresponding to the first sub-circuit unit 141 is electrically connected to the data line 110 corresponding to the 6th column of sub-pixels.

[0073] For example, in a specific implementation, in an embodiment of the present invention, Figures 6 to 9 As shown, the first sub-circuit unit 141 may include: a first transistor M1 and a second transistor M2;

[0074] The gates of all first transistors M1 are electrically connected to the first control signal line SW1, the sources of all first transistors M1 are electrically connected to the first transmission signal line S1, the gates of all second transistors M2 are electrically connected to the second control signal line SW2, and the sources of all second transistors M2 are electrically connected to the first sub-transmission signal line S2-1; in the same first sub-circuit unit 141, the drain of the first transistor M1 and the drain of the second transistor M2 are electrically connected to the corresponding output line 150.

[0075] It should be noted that the drain of the first transistor M1 and the drain of the second transistor M2 are electrically connected to the input terminal 130 through the corresponding output line 150, so that the drain of the first transistor M1 and the drain of the second transistor M2 are electrically connected to the corresponding data line 110 through the corresponding output line 150, the input terminal 130, and the fan-out line 120 in sequence.

[0076] For example, in a specific implementation, the first transistor M1 can be in a conducting state under the control of the on signal on the first control signal line SW1, so that the signal on the first transmission signal line S1 can be provided to the corresponding data line 110. The first transistor M1 can be in a closed state under the control of the off signal on the first control signal line SW1. Further, the first transistor M1 can be an N-type transistor, or the first transistor M1 can also be a P-type transistor. Of course, in practical applications, the specific type of the first transistor M1 can be designed and determined according to the actual application environment, and is not limited here.

[0077] For example, in a specific implementation, the second transistor M2 can be in a conducting state under the control of the turn-on signal on the second control signal line SW2, so that the signal on the first sub-transmission signal line S2-1 can be provided to the corresponding data line 110. The second transistor M2 can be in a closed state under the control of the cut-off signal on the second control signal line SW2. Further, the second transistor M2 can be an N-type transistor, or the second transistor M2 can also be a P-type transistor. Of course, in actual applications, the specific type of the second transistor M2 can be designed and determined according to the actual application environment, and is not limited here.

[0078] For example, in a specific implementation, in an embodiment of the present invention, Figures 6 to 8 As shown, the second circuit unit 140-2 may include: a plurality of second sub-circuit units 142, a third control signal line SW3, and a fourth control signal line SW4; wherein one second sub-circuit unit 142 corresponds to a column of sub-pixels in the 3n-2 column of sub-pixels, and the output line 150 corresponding to the second sub-circuit unit 142 is electrically connected to the display drive signal line of the corresponding column of sub-pixels. Exemplarily, the first column of sub-pixels corresponds to one second sub-circuit unit 142, and the second sub-circuit unit 142 is electrically connected to the data line 110 corresponding to the first column of sub-pixels.

[0079] For example, in a specific implementation, in an embodiment of the present invention, Figures 6 to 8 As shown, the second sub-circuit unit 142 includes: a third transistor M3 and a fourth transistor M4;

[0080] The gates of all third transistors M3 are electrically connected to the third control signal line SW3, the sources of all third transistors M3 are electrically connected to the first transmission signal line S1, the gates of all fourth transistors M4 are electrically connected to the fourth control signal line SW4, and the sources of all fourth transistors M4 are electrically connected to the second sub-transmission signal line S2-2; in the same second sub-circuit unit 142, the drain of the third transistor M3 is electrically connected to the drain of the fourth transistor M4 and the corresponding output line 150.

[0081] It should be noted that the drain of the third transistor M3 and the drain of the fourth transistor M4 are electrically connected to the input terminal 130 through the corresponding output line 150, so that the drain of the third transistor M3 and the drain of the fourth transistor M4 are electrically connected to the corresponding data line 110 through the corresponding output line 150, the input terminal 130, and the fan-out line 120 in sequence.

[0082] For example, in a specific implementation, the third transistor M3 can be in a conducting state under the control of the turn-on signal on the third control signal line SW3, so that the signal on the first transmission signal line S1 can be provided to the corresponding data line 110. The third transistor M3 can be in a closed state under the control of the cut-off signal on the third control signal line SW3. Further, the third transistor M3 can be an N-type transistor, or the third transistor M3 can also be a P-type transistor. Of course, in actual applications, the specific type of the third transistor M3 can be designed and determined according to the actual application environment, and is not limited here.

[0083] For example, in a specific implementation, the fourth transistor M4 can be in a conducting state under the control of the on signal on the fourth control signal line SW4, so that the signal on the second sub-transmission signal line S2-2 can be provided to the corresponding data line 110. The fourth transistor M4 can be in a closed state under the control of the off signal on the fourth control signal line SW4. Further, the fourth transistor M4 can be an N-type transistor, or the fourth transistor M4 can also be a P-type transistor. Of course, in practical applications, the specific type of the fourth transistor M4 can be designed and determined according to the actual application environment, and is not limited here.

[0084] For example, in a specific implementation, in an embodiment of the present invention, Figures 6 to 8 As shown, the third circuit unit 140-3 can include: multiple fifth transistors M5 and a fifth control signal line SW5; wherein the gates of all fifth transistors M5 are electrically connected to the fifth control signal line SW5, the sources of all fifth transistors M5 are electrically connected to the third transmission signal line S3, and each fifth transistor M5 is electrically connected to a one-to-one corresponding output line 150.

[0085] For example, in a specific implementation, in an embodiment of the present invention, Figures 6 to 8 As shown, a fifth transistor M5 corresponds to a column of sub-pixels in the 3n-1th column of sub-pixels, and the output line 150 corresponding to the fifth transistor M5 is electrically connected to the display drive signal line of the corresponding column of sub-pixels. Exemplarily, the second column of sub-pixels corresponds to a fifth transistor M5, and the fifth transistor M5 is electrically connected to the data line 110 corresponding to the second column of sub-pixels.

[0086] It should be noted that the drain of the fifth transistor M5 is electrically connected to the input terminal 130 through the corresponding output line 150 , so that the drain of the fifth transistor M5 can be electrically connected to the corresponding data line 110 through the corresponding output line 150 , the input terminal 130 , and the fan-out line 120 in sequence.

[0087] For example, in a specific implementation, the fifth transistor M5 can be in a conducting state under the control of the turn-on signal on the fifth control signal line SW5, so that the signal on the third transmission signal line S3 can be provided to the corresponding data line 110. The fifth transistor M5 can be in a closed state under the control of the cut-off signal on the fifth control signal line SW5. Further, the fifth transistor M5 can be an N-type transistor, or the fifth transistor M5 can also be a P-type transistor. Of course, in practical applications, the specific type of the fifth transistor M5 can be designed and determined according to the actual application environment, and is not limited here.

[0088] It should be noted that, in the embodiment of the present invention, the above transistors may be thin film transistors (TFT) or metal oxide semiconductor field effect transistors (MOS), which are not limited here. In specific implementation, the source and drain of each of the above transistors may be interchanged according to the type of transistor and the signal of the gate, which is not specifically distinguished here.

[0089] For example, in a specific implementation, Figure 8 and Fig. 9 As shown, the first control signal line SW1 and the fourth control signal line SW4 can be electrically connected. In this way, only one input port can be set in the display panel, that is, in the VT test, the corresponding data signal can be input to the first control signal line SW1 and the fourth control signal line SW4. Thereby, the wiring space occupied and the wiring design difficulty can be reduced. In addition, this can also improve the uniformity of the signals loaded on the first control signal line SW1 and the fourth control signal line SW4, so as to improve the control uniformity of the first transistor M1 and the fourth transistor M4.

[0090] For example, in a specific implementation, Figure 8 and Fig. 9 As shown, the second control signal line SW2 and the third control signal line SW3 can be electrically connected. In this way, only one input port can be set in the display panel, that is, in the VT test, the corresponding data signal can be input to the second control signal line SW2 and the third control signal line SW3. Thereby, the wiring space occupied and the wiring design difficulty can be reduced. In addition, this can also improve the uniformity of the signal loaded on the second control signal line SW2 and the third control signal line SW3, so as to improve the control uniformity of the second transistor M2 and the third transistor M3.

[0091] For example, in a specific implementation, Fig.10 As shown, the output line 150 electrically connected to the second circuit unit 140-2 is connected in parallel with a resistor R0, and the resistor R0 of the output line 150 electrically connected to the second circuit unit 140-2 is the same as the resistor R0 of the output line 150 electrically connected to the first circuit unit 140-1. In this way, by connecting the resistor R0 in parallel to the output line 150 electrically connected to the second circuit unit 140-2, the total resistance R0 of the output line 150 electrically connected to the second circuit unit 140-2 can be reduced, so that the total resistance R0 of the output line 150 electrically connected to the second circuit unit 140-2 can be close to the total resistance R0 of the output line 150 electrically connected to the first circuit unit 140-1. Furthermore, by designing the resistance R0 value of the resistor R0 connected in parallel on the output line 150 electrically connected to the second circuit unit 140-2, the total resistance R0 of the output line 150 electrically connected to the second circuit unit 140-2 can be made substantially the same as the total resistance R0 of the output line 150 electrically connected to the first circuit unit 140-1, thereby making the voltages input to the same color sub-pixels in different columns substantially the same, making the brightness of the pure color picture substantially the same, and thereby improving the problem of vertical stripes appearing in the pure color picture.

[0092] It should be noted that in actual processes, due to limitations of process conditions or other factors, the similarities among the above-mentioned features may not be completely the same, and there may be some deviations. Therefore, as long as the similarities among the above-mentioned features roughly meet the above-mentioned conditions, they all belong to the protection scope of the present invention. For example, the above-mentioned similarities may be the same as allowed within the tolerance range.

[0093] Exemplarily, the output line 150 electrically connected to the second circuit unit 140-2 may be connected in parallel with a resistor R0 by increasing the width of the output line 150 electrically connected to the second circuit unit 140-2, so that the total resistance of the output line 150 electrically connected to the second circuit unit 140-2 is reduced. Alternatively, the output line 150 electrically connected to the second circuit unit 140-2 may be connected in parallel with a resistor R0 by providing a conductive layer on other film layers, and connecting the conductive layer in parallel with the output line 150 electrically connected to the second circuit unit 140-2, so that the total resistance of the output line 150 electrically connected to the second circuit unit 140-2 is reduced. Of course, in actual applications, the design and determination can be based on the actual application environment, and is not limited here.

[0094] Exemplarily, the first transmission signal line, the second transmission signal line, and the third transmission signal line can be arranged in the same layer and the same material as the data line. In this way, the first transmission signal line, the second transmission signal line, the third transmission signal line, and the data line can be formed by the same patterning process, thereby reducing the difficulty of the work, and generally the material of the data line is a metal material, so that the resistivity of the first transmission signal line, the second transmission signal line, and the third transmission signal line can also be reduced.

[0095] Exemplarily, the first to fifth transistors can be manufactured simultaneously with the transistors in the display area, which can improve the process consistency of these transistors and reduce the difficulty of process manufacturing.

[0096] Based on the same inventive concept, an embodiment of the present invention further provides a method for detecting the above display panel, which may include the following steps:

[0097] When the display panel displays a pure color picture, the sub-pixels of the corresponding colors are lit;

[0098] Wherein, a bright state signal is loaded on the first transmission signal line S1, a dark state signal is loaded on the second transmission signal line S2 and the third transmission signal line S3 respectively, and corresponding control signals are loaded on the first control signal line SW1 to the fifth control signal line SW5 respectively, so as to light up the first color sub-pixel or the third color sub-pixel;

[0099] A dark state signal is loaded to the first transmission signal line S1 and the second transmission signal line S2, a bright state signal is loaded to the third transmission signal line S3, and corresponding control signals are loaded to the first control signal line SW1 to the fifth control signal line SW5, respectively, to light up the second color sub-pixel.

[0100] The above detection method provided by the embodiment of the present invention lights up the second color sub-pixel to display the second color pure color picture by loading the dark state signal to the first transmission signal line and the second transmission signal line, loading the bright state signal to the third transmission signal line, and loading the corresponding control signals to the first control signal line to the fifth control signal line, respectively. In addition, by loading the bright state signal to the first transmission signal line, loading the dark state signal to the second transmission signal line and the third transmission signal line, respectively, and loading the corresponding control signals to the first control signal line to the fifth control signal line, the first color sub-pixel or the third color sub-pixel is lit to display the first color pure color picture or the third color pure color picture. Since the first transmission signal line is set between the first circuit unit and the second circuit unit, the RC loading between the output line electrically connected to the first circuit unit and the output line electrically connected to the second circuit unit can be reduced, thereby improving the problem of vertical stripes on the first color pure color picture or the third color pure color picture.

[0101] Exemplarily, in a specific implementation, in an embodiment of the present invention, the first color sub-pixel is lit, such as Fig.11 As shown, the following steps may be included:

[0102] S11, in the first stage, a bright state signal is loaded to the first transmission signal line S1, dark state signals are loaded to the second transmission signal line S2 and the third transmission signal line S3 respectively, an on signal is loaded to the second control signal line SW2 and the third control signal line SW3, an off signal is loaded to the first control signal line SW1 and the fourth control signal line SW4, and an on signal is loaded to the fifth control signal line SW5, so that the second circuit unit 140-2 outputs a bright state signal, and the first circuit unit 140-1 and the third circuit unit 140-3 output dark state signals;

[0103] S12, the second stage, a bright state signal is loaded to the first transmission signal line S1, a dark state signal is loaded to the second transmission signal line S2 and the third transmission signal line S3 respectively, an open signal is loaded to the first control signal line SW1 and the fourth control signal line SW4, an off signal is loaded to the second control signal line SW2 and the third control signal line SW3, and an open signal is loaded to the fifth control signal line SW5, so that the first circuit unit 140-1 outputs a bright state signal, and the second circuit unit 140-2 and the third circuit unit 140-3 output a dark state signal.

[0104] For example, taking the first color sub-pixel as a red sub-pixel R as an example, when the display panel displays a red pure color picture, the red sub-pixel R can be lit. Fig.10 As an example, the display panel shown in FIG. Fig.12 The signal timing diagram shown is used to illustrate the detection process of the display panel provided by the embodiment of the present invention.

[0105] Among them, sw1 represents the signal loaded on the first control signal line SW1 and the fourth control signal line SW4, sw2 represents the signal loaded on the second control signal line SW2 and the third control signal line SW3, ga1 represents the signal transmitted on the gate line GA electrically connected to the first row of sub-pixels, and ga2 represents the signal transmitted on the gate line GA electrically connected to the second row of sub-pixels. The fifth control signal line SW5 is always loaded with a start signal of a fixed voltage (for example, a low level signal).

[0106] In the t11 stage, the process of the above step S11 is implemented. Specifically, if the signal ga1 is a low-level signal, the thin film transistors in the first row of sub-pixels are turned on. If the signal ga2 is a high-level signal, the thin film transistors in the second row of sub-pixels are turned off. Since the signal sw1 is a high-level signal (i.e., a cut-off signal), all the first transistors M1 and all the fourth transistors M4 are turned off. A dark state signal (e.g., 6V) is loaded on the third transmission signal line S3, and a low-level signal (i.e., an on signal) of a fixed voltage is transmitted on the fifth control signal line SW5, so that all the fifth transistors M5 are turned on to provide the dark state signal to the data line 110 electrically connected to the green sub-pixel G, so that the green sub-pixel G in the first row inputs the dark state signal, thereby making the green sub-pixel G non-luminous. Since the signal sw2 is a low-level signal (i.e., an on signal), all the second transistors M2 and all the third transistors M3 are turned on. A dark state signal (for example, 6V) is loaded on the first sub-transmission signal line S2-1 and the second sub-transmission signal line S2-2, respectively, and the dark state signal is provided to the corresponding data line 110 through the turned-on second transistor M2, so that the blue sub-pixel B in the first row is input with the dark state signal, and then the blue sub-pixel B does not emit light. A bright state signal (for example, 3V) is loaded on the first transmission signal line S1, and the bright state signal is provided to the corresponding data line 110 through the turned-on third transistor M3, so that the red sub-pixel R in the first row is input with the bright state signal, and then the red sub-pixel R emits light to display red.

[0107] In the t12 stage, the process of the above step S12 is implemented. Specifically, if the signal ga1 is a high-level signal, the thin film transistors in the first row of sub-pixels are turned off. If the signal ga2 is a low-level signal, the thin film transistors in the second row of sub-pixels are turned on. Since the signal sw2 is a high-level signal (i.e., a cut-off signal), all the second transistors M2 and all the third transistors M3 are turned off. A dark state signal (e.g., 6V) is loaded on the third transmission signal line S3, and a low-level signal (i.e., an on signal) of a fixed voltage is transmitted on the fifth control signal line SW5, so that all the fifth transistors M5 are turned on to provide the dark state signal to the data line 110 electrically connected to the green sub-pixel G, so that the green sub-pixel G in the first row inputs the dark state signal, thereby making the green sub-pixel G non-luminous. Since the signal sw1 is a low-level signal (i.e., an on signal), all the first transistors M1 and all the fourth transistors M4 are turned on. A dark state signal (for example, 6V) is loaded on the first sub-transmission signal line S2-1 and the second sub-transmission signal line S2-2, respectively, and the dark state signal is provided to the corresponding data line 110 through the turned-on fourth transistor M4, so that the blue sub-pixel B in the second row is input with the dark state signal, and the blue sub-pixel B does not emit light. A bright state signal (for example, 3V) is loaded on the first transmission signal line S1, and the bright state signal is provided to the corresponding data line 110 through the turned-on first transistor M1, so that the red sub-pixel R in the second row is input with the bright state signal, and the red sub-pixel R emits light to display red.

[0108] The rest of the lines are processed in the same way, so that the display panel displays a pure red image. The specific process will not be described in detail here.

[0109] In the embodiment of the present invention, only one transmission signal line among the plurality of transmission signal lines, namely the first transmission signal line S1, is provided between the first circuit unit 140-1 and the second circuit unit 140-2. Furthermore, by connecting a resistor R0 in parallel to the output line 150 electrically connected to the second circuit unit 140-2, the resistor R0 of the output line 150 electrically connected to the second circuit unit 140-2 can be made substantially the same as the resistor R0 of the output line 150 electrically connected to the first circuit unit 140-1. In this way, when the display panel displays a pure red color image through the short-circuit bar structure 140, the problem of vertical stripes can be improved, thereby improving the display effect of the pure red color image.

[0110] Furthermore, the embodiment of the present invention can further reduce the difference in luminescence of red sub-pixels in different columns by setting the transmission signal line for inputting bright state signals to the red sub-pixels to one, namely the first transmission signal line, thereby further improving the display effect of red pure color images.

[0111] Exemplarily, in a specific implementation, in an embodiment of the present invention, the third color sub-pixel is lit, such as Fig.13As shown, the following steps may be included:

[0112] S21, in the first stage, a bright state signal is applied to the first transmission signal line S1, dark state signals are applied to the second transmission signal line S2 and the third transmission signal line S3 respectively, an on signal is applied to the first control signal line SW1 and the fourth control signal line SW4, an off signal is applied to the second control signal line SW2 and the third control signal line SW3, and an on signal is applied to the fifth control signal line SW5, so that the first circuit unit 140-1 outputs a bright state signal, and the second circuit unit 140-2 and the third circuit unit 140-3 output dark state signals;

[0113] S22, the second stage, a bright state signal is loaded to the first transmission signal line S1, a dark state signal is loaded to the second transmission signal line S2 and the third transmission signal line S3 respectively, an open signal is loaded to the second control signal line SW2 and the third control signal line SW3, an off signal is loaded to the first control signal line SW1 and the fourth control signal line SW4, and an open signal is loaded to the fifth control signal line SW5, so that the second circuit unit 140-2 outputs a bright state signal, and the first circuit unit 140-1 and the third circuit unit 140-3 output a dark state signal.

[0114] For example, taking the third color sub-pixel as a blue sub-pixel B as an example, when the display panel displays a blue pure color picture, the blue sub-pixel B can be lit. Fig.10 As an example, the display panel shown in FIG. Fig.14 The signal timing diagram shown is used to illustrate the detection process of the display panel provided by the embodiment of the present invention.

[0115] Among them, sw1 represents the signal loaded on the first control signal line SW1 and the fourth control signal line SW4, sw2 represents the signal loaded on the second control signal line SW2 and the third control signal line SW3, ga1 represents the signal transmitted on the gate line GA electrically connected to the first row of sub-pixels, and ga2 represents the signal transmitted on the gate line GA electrically connected to the second row of sub-pixels. The fifth control signal line SW5 is always loaded with a start signal of a fixed voltage (for example, a low level signal).

[0116] In the t21 stage, the process of the above step S21 is implemented. Specifically, if the signal ga1 is a low-level signal, the thin film transistors in the first row of sub-pixels are turned on. If the signal ga2 is a high-level signal, the thin film transistors in the second row of sub-pixels are turned off. Since the signal sw2 is a high-level signal (i.e., a cut-off signal), all the second transistors M2 and all the third transistors M3 are turned off. A dark state signal (e.g., 6V) is loaded on the third transmission signal line S3, and a low-level signal (i.e., an on signal) of a fixed voltage is transmitted on the fifth control signal line SW5, so that all the fifth transistors M5 are turned on to provide the dark state signal to the data line 110 electrically connected to the green sub-pixel G, so that the green sub-pixel G in the first row inputs the dark state signal, thereby making the green sub-pixel G non-luminous. Since the signal sw1 is a low-level signal (i.e., an on signal), all the first transistors M1 and all the fourth transistors M4 are turned on. A dark state signal (for example, 6V) is applied to the first sub-transmission signal line S2-1 and the second sub-transmission signal line S2-2, respectively, and the dark state signal is provided to the corresponding data line 110 through the turned-on fourth transistor M4, so that the red sub-pixel R in the first row is input with the dark state signal, and the red sub-pixel R does not emit light. A bright state signal (for example, 3V) is applied to the first transmission signal line S1, and the bright state signal is provided to the corresponding data line 110 through the turned-on first transistor M1, so that the blue sub-pixel B in the first row is input with the bright state signal, and the blue sub-pixel B emits light to display blue.

[0117] At stage t22, the process of step S22 is implemented. Specifically, if the signal ga1 is a high-level signal, the thin-film transistors in the first row of sub-pixels are turned off. If the signal ga2 is a low-level signal, the thin-film transistors in the second row of sub-pixels are turned on. Since the signal sw1 is a high-level signal (i.e., a cut-off signal), all first transistors M1 and all fourth transistors M4 are turned off. A dark state signal (e.g., 6V) is loaded on the third transmission signal line S3, and a low-level signal (i.e., an on signal) of a fixed voltage is transmitted on the fifth control signal line SW5, so that all fifth transistors M5 are turned on to provide the dark state signal to the data line 110 electrically connected to the green sub-pixel G, so that the green sub-pixel G in the first row inputs the dark state signal, thereby making the green sub-pixel G non-luminous. Since the signal sw2 is a low-level signal (i.e., an on signal), all second transistors M2 and all third transistors M3 are turned on. A dark state signal (for example, 6V) is loaded on the first sub-transmission signal line S2-1 and the second sub-transmission signal line S2-2, respectively, and the dark state signal is provided to the corresponding data line 110 through the turned-on second transistor M2, so that the red sub-pixel R in the second row is input with the dark state signal, and the red sub-pixel R does not emit light. A bright state signal (for example, 3V) is loaded on the first transmission signal line S1, and the bright state signal is provided to the corresponding data line 110 through the turned-on third transistor M3, so that the blue sub-pixel B in the second row is input with the bright state signal, and the blue sub-pixel B emits light to display blue.

[0118] The rest of the lines are processed in the same way, so that the display panel displays a pure blue picture. The specific process will not be described here.

[0119] In the embodiment of the present invention, only one transmission signal line among the plurality of transmission signal lines, namely the first transmission signal line S1, is provided between the first circuit unit 140-1 and the second circuit unit 140-2. Furthermore, by connecting a resistor R0 in parallel to the output line 150 electrically connected to the second circuit unit 140-2, the resistor R0 of the output line 150 electrically connected to the second circuit unit 140-2 can be made substantially the same as the resistor R0 of the output line 150 electrically connected to the first circuit unit 140-1. In this way, when the display panel displays a blue pure color picture through the short-circuit bar structure 140, the problem of vertical stripes can be improved, thereby improving the display effect of the blue pure color picture.

[0120] Moreover, compared with the luminous efficiency of the luminous devices in the red sub-pixels and the green sub-pixels, the luminous efficiency of the luminous devices in the blue sub-pixels is lower, so when they age, they require a larger current. Therefore, in the embodiment of the present invention, by setting the transmission signal line for inputting the bright state signal to the blue sub-pixels to one, i.e., the first transmission signal line, the difference in the luminescence of the blue sub-pixels in different columns can be further reduced, thereby further improving the display effect of the blue pure color picture.

[0121] In specific implementation, in an embodiment of the present invention, lighting up the second color sub-pixel may include: loading a dark state signal to the first transmission signal line S1 and the second transmission signal line S2, loading a bright state signal to the third transmission signal line S3, and loading an on signal to the first control signal line SW1 to the fifth control signal line SW5, so that the first circuit unit 140-1 and the second circuit unit 140-2 output a dark state signal, and the third circuit unit 140-3 outputs a bright state signal.

[0122] For example, taking the second color sub-pixel as a green sub-pixel G as an example, when the display panel displays a green pure color picture, the green sub-pixel G can be lit. Fig.10 Taking the display panel shown as an example, the detection process of the display panel provided by the embodiment of the present invention is described.

[0123] Specifically, if a low-level signal (i.e., a turn-on signal) is always applied to the first control signal line SW1 to the fifth control signal line SW5, all the first transistors M1 to the fifth transistors M5 are turned on. Furthermore, if a dark-state signal (e.g., 6V) is applied to the first transmission signal line S1, the first sub-transmission signal line S2-1, and the second sub-transmission signal line S2-2, respectively, the dark-state signal can be input to the red sub-pixel R and the blue sub-pixel B, thereby making the red sub-pixel R and the blue sub-pixel B non-luminous. If a bright-state signal (e.g., 3V) is output to the third circuit unit 140-3, the bright-state signal can be input to the green sub-pixel G, thereby making the green sub-pixel G luminous to display green.

[0124] It should be noted that since the areas where the fifth transistors M5 are located are all located between the second sub-transmission signal line S2-2 and the third transmission signal line S3, the RC loading of the output line 150 electrically connected to each fifth transistor M5 can be roughly the same, thereby avoiding the vertical stripe problem when displaying a green pure color picture.

[0125] Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the display panel provided by the embodiment of the present invention. The principle of solving the problem by the display device is similar to that of the display panel, so the implementation of the display device can refer to the implementation of the display panel, and the repeated parts will not be repeated here.

[0126] In a specific implementation, in an embodiment of the present invention, the display device may be: Fig.15 The full-screen mobile phone shown. Of course, the display device can also be: a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function. Other essential components of the display device should be understood by ordinary technicians in the field, and will not be described here, nor should they be used as limitations on the present invention.

[0127] The display panel, the detection method and the display device provided by the embodiment of the present invention, the short-circuit bar structure in the display panel has a first circuit unit, a second circuit unit and a third circuit unit arranged in sequence along the second direction, and the first circuit unit and the second circuit unit share a first transmission signal line, so that the first transmission signal line can transmit signals to the first circuit unit and the second circuit unit respectively. And by setting the first transmission signal line between the first circuit unit and the second circuit unit, only one transmission signal line among multiple transmission signal lines, namely the first transmission signal line, can be set between the first circuit unit and the second circuit unit. In this way, the difference between the resistance between the first circuit unit and the fan-out line and the resistance between the second circuit unit and the fan-out line is reduced, and the difference between the RC loading between the first circuit unit and the fan-out line and the RC loading between the second circuit unit and the fan-out line is reduced, so that the difference in voltage input to the same color sub-pixels in different columns can be reduced, thereby improving the problem of vertical stripes in pure color pictures and improving the display effect of pure color pictures.

[0128] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A display panel, characterized in that: include: A base substrate having a display area and a non-display area; The non-display area includes: a fan-out area and a binding area; the fan-out area includes: a plurality of fan-out lines; and the fan-out area is arranged between the display area and the binding area; The binding area includes: a shorting bar structure and a plurality of input terminals; wherein one of the input terminals is electrically connected to a fan-out line; The shorting bar structure comprises: a plurality of transmission signal lines extending along a first direction, a plurality of output lines extending along a second direction, and a first circuit unit, a second circuit unit and a third circuit unit arranged along the second direction; wherein the first circuit unit, the second circuit unit and the third circuit unit are electrically connected to different output lines respectively; The plurality of transmission signal lines include: a first transmission signal line; wherein the first circuit unit and the second circuit unit share the first transmission signal line, and the first transmission signal line is arranged between the first circuit unit and the second circuit unit; a second transmission signal line and a third transmission signal line; The second transmission signal line includes: a first sub-transmission signal line and a second sub-transmission signal line; wherein the first sub-transmission signal line is electrically connected to the first circuit unit, and the second sub-transmission signal line is electrically connected to the second circuit unit; wherein the first sub-transmission signal line is located at a side of the first circuit unit away from the first transmission signal line, and the second sub-transmission signal line is located at a side of the second circuit unit away from the first transmission signal line; The third transmission signal line is electrically connected to the third circuit unit.

2. The display panel according to claim 1, wherein: The display area also includes a plurality of sub-pixels arranged in an array; The plurality of sub-pixels include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; The display area includes a plurality of pixel columns, wherein the 3n-2 column of sub-pixels and the 3n column of sub-pixels respectively include first color sub-pixels and third color sub-pixels that are alternately arranged, and the arrangement order of the first color sub-pixels and the third color sub-pixels in the 3n-2 column of sub-pixels and the 3n column of sub-pixels is opposite; and the 3n-1 column of sub-pixels includes second color sub-pixels that are sequentially arranged, wherein n is a positive integer; The fan-out line corresponding to the sub-pixel in the 3nth column is connected to the first circuit unit; the fan-out line corresponding to the sub-pixel in the 3n-2th column is connected to the second circuit unit; and the fan-out line corresponding to the sub-pixel in the 3nth column is connected to the third circuit unit.

3. The display panel according to claim 1, wherein: The first circuit unit is directly adjacent to the second circuit unit, and no transistor is arranged between the first circuit unit and the second circuit unit.

4. The display panel according to claim 2, wherein: The third transmission signal line is located at a side of the third circuit unit away from the second circuit unit.

5. The display panel according to claim 2, wherein: The third transmission signal line is located between the third circuit unit and the second sub-transmission signal line.

6. The display panel according to claim 2, wherein: The first circuit unit includes: a plurality of first sub-circuit units, a first control signal line and a second control signal line; wherein the first sub-circuit unit includes: a first transistor and a second transistor; The gates of all the first transistors are electrically connected to the first control signal line, the sources of all the first transistors are electrically connected to the first transmission signal line, the gates of all the second transistors are electrically connected to the second control signal line, and the sources of all the second transistors are electrically connected to the first sub-transmission signal line; in the same first sub-circuit unit, the drain of the first transistor and the drain of the second transistor are electrically connected to the corresponding output line; The second circuit unit includes: a plurality of second sub-circuit units, a third control signal line and a fourth control signal line; wherein the second sub-circuit unit includes: a third transistor and a fourth transistor; The gates of all the third transistors are electrically connected to the third control signal line, the sources of all the third transistors are electrically connected to the first transmission signal line, the gates of all the fourth transistors are electrically connected to the fourth control signal line, and the sources of all the fourth transistors are electrically connected to the second sub-transmission signal line; in the same second sub-circuit unit, the drains of the third transistors and the drains of the fourth transistors are electrically connected to the corresponding output lines; The third circuit unit includes: multiple fifth transistors and fifth control signal lines; wherein, the gates of all the fifth transistors are electrically connected to the fifth control signal line, the sources of all the fifth transistors are electrically connected to the third transmission signal line, and each of the fifth transistors is electrically connected to a corresponding output line.

7. The display panel according to claim 6, wherein: The display area includes: a plurality of sub-pixels and a plurality of display drive signal lines extending along the second direction; a column of sub-pixels is electrically connected to one of the display drive signal lines, and one of the fan-out lines is electrically connected to at least one of the display drive signal lines; The first circuit unit is close to the display area, the third circuit unit is located at a side of the first circuit unit away from the display area, and the second circuit unit is located between the first circuit unit and the second circuit unit.

8. The display panel according to claim 7, wherein: One of the first sub-circuit units corresponds to a column of sub-pixels in the 3nth column of sub-pixels, and the output line corresponding to the first sub-circuit unit is electrically connected to the display driving signal line of the corresponding column of sub-pixels; One of the second sub-circuit units corresponds to a column of sub-pixels in the 3n-2th column of sub-pixels, and the output line corresponding to the second sub-circuit unit is electrically connected to the display driving signal line of the corresponding column of sub-pixels; One of the fifth transistors corresponds to a column of sub-pixels in the 3n-1th column of sub-pixels, and the output line corresponding to the fifth transistor is electrically connected to the display driving signal line of the corresponding column of sub-pixels.

9. The display panel according to claim 8, wherein: The first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.

10. The display panel according to claim 6, wherein: The first control signal line is electrically connected to the fourth control signal line, and the second control signal line is electrically connected to the third control signal line.

11. The display panel according to any one of claims 1 to 5, characterized in that: The output line electrically connected to the second circuit unit has a resistor connected in parallel, and the resistor of the output line electrically connected to the second circuit unit is the same as the resistor of the output line electrically connected to the first circuit unit.

12. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-11.

13. A method for detecting a display panel according to any one of claims 1 to 11, characterized in that: include: When the display panel displays a pure color picture, lighting up the sub-pixels of the corresponding colors; Wherein, a bright state signal is loaded on the first transmission signal line, a dark state signal is loaded on the second transmission signal line and the third transmission signal line respectively, and corresponding control signals are loaded on the first control signal line to the fifth control signal line respectively, so as to light up the first color sub-pixel or the third color sub-pixel; A dark state signal is loaded onto the first transmission signal line and the second transmission signal line, a bright state signal is loaded onto the third transmission signal line, and corresponding control signals are loaded onto the first control signal line to the fifth control signal line, respectively, to light up the second color sub-pixel.

14. The detection method according to claim 13, characterized in that: The display area includes a plurality of pixel columns, wherein the 3n-2 column of sub-pixels and the 3n column of sub-pixels respectively include first color sub-pixels and third color sub-pixels that are alternately arranged, and the arrangement order of the first color sub-pixels and the third color sub-pixels in the 3n-2 column of sub-pixels and the 3n column of sub-pixels is opposite; and the 3n-1 column of sub-pixels includes second color sub-pixels that are sequentially arranged, wherein n is a positive integer; In the 3n-2 th column of sub-pixels, odd-numbered rows have first color sub-pixels, and even-numbered rows have third color sub-pixels; The first circuit unit includes: a plurality of first sub-circuit units, a first control signal line and a second control signal line; The second circuit unit includes: a plurality of second sub-circuit units, a third control signal line and a fourth control signal line; The lighting up the first color sub-pixel comprises: In the first stage, the bright state signal is applied to the first transmission signal line, the dark state signal is applied to the second transmission signal line and the third transmission signal line respectively, the start signal is applied to the second control signal line and the third control signal line, the cut-off signal is applied to the first control signal line and the fourth control signal line, and the start signal is applied to the fifth control signal line, so that the second circuit unit outputs the bright state signal, and the first circuit unit and the third circuit unit output the dark state signal; In the second stage, a bright state signal is loaded onto the first transmission signal line, a dark state signal is loaded onto the second transmission signal line and the third transmission signal line respectively, an open signal is loaded onto the first control signal line and the fourth control signal line, an off signal is loaded onto the second control signal line and the third control signal line, and the open signal is loaded onto the fifth control signal line, so that the first circuit unit outputs the bright state signal, and the second circuit unit and the third circuit unit output the dark state signal.

15. The detection method according to claim 13, characterized in that: The display area includes a plurality of pixel columns, wherein the 3n-2 column of sub-pixels and the 3n column of sub-pixels respectively include first color sub-pixels and third color sub-pixels that are alternately arranged, and the arrangement order of the first color sub-pixels and the third color sub-pixels in the 3n-2 column of sub-pixels and the 3n column of sub-pixels is opposite; and the 3n-1 column of sub-pixels includes second color sub-pixels that are sequentially arranged, wherein n is a positive integer; In the 3n-2 th column of sub-pixels, odd-numbered rows have first color sub-pixels, and even-numbered rows have third color sub-pixels; The first circuit unit includes: a plurality of first sub-circuit units, a first control signal line and a second control signal line; The second circuit unit includes: a plurality of second sub-circuit units, a third control signal line and a fourth control signal line; The lighting up the third color sub-pixel comprises: In the first stage, a bright state signal is applied to the first transmission signal line, dark state signals are applied to the second transmission signal line and the third transmission signal line respectively, an on signal is applied to the first control signal line and the fourth control signal line, an off signal is applied to the second control signal line and the third control signal line, and the on signal is applied to the fifth control signal line, so that the first circuit unit outputs the bright state signal, and the second circuit unit and the third circuit unit output the dark state signal; In the second stage, the bright state signal is loaded onto the first transmission signal line, dark state signals are loaded onto the second transmission signal line and the third transmission signal line respectively, an on signal is loaded onto the second control signal line and the third control signal line, an off signal is loaded onto the first control signal line and the fourth control signal line, and an on signal is loaded onto the fifth control signal line, so that the second circuit unit outputs the bright state signal, and the first circuit unit and the third circuit unit output the dark state signal.

16. The detection method according to claim 14 or 15, characterized in that: The lighting up the second color sub-pixel comprises: A dark state signal is loaded onto the first transmission signal line and the second transmission signal line, a bright state signal is loaded onto the third transmission signal line, and the start signal is loaded onto the first control signal line to the fifth control signal line, so that the first circuit unit and the second circuit unit output the dark state signal, and the third circuit unit outputs the bright state signal.

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