Enable control circuit and semiconductor memory

Abstract

An embodiment of the present application provides an enabling control circuit and a semiconductor memory. The enabling control circuit includes: a counting module for counting the current clock cycle to determine a clock cycle count value; a selection module for determining a clock cycle count target value according to a first setting signal; a control module connected to the counting module and the selection module, configured to control the ODT path to be in an enabled state and start the counting module when the level state of the ODT pin signal flips; and when the clock cycle count value reaches the clock cycle count target value, control the ODT path to be switched from the enabled state to the off state. In this way, the enabling state of the ODT path is controlled according to whether the clock cycle count value reaches the clock cycle count target value, so that the ODT path is controlled to be turned off when it is not required to work, thereby avoiding current waste and achieving the purpose of power consumption saving.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular, to an enable control circuit and a semiconductor memory. Background Art

[0002] With the continuous development of semiconductor technology, when manufacturing and using devices such as computers, people have put forward higher and higher requirements for the data transmission speed. In order to obtain a faster data transmission speed, a series of devices such as memories that can transmit data at double data rate (DDR) have emerged.

[0003] In the design of double data rate transmission, regulations regarding on-die termination (ODT) are added. Briefly speaking, the value of the termination resistance (RTT) can be switched, and how to switch it needs to follow a certain timing. For example, the state of the ODT pin on the memory chip can control the value of the RTT.

[0004] However, in the current related technologies, the enable state of the on-die termination path (ODT path) cannot be accurately controlled, resulting in current waste and thus increasing power consumption. Summary of the Invention

[0005] This application provides an enable control circuit and a semiconductor memory, which can avoid current waste and thus achieve the purpose of saving power consumption.

[0006] The technical solution of this application is implemented as follows:

[0007] In a first aspect, an embodiment of this application provides an enable control circuit, which includes:

[0008] A counting module, configured to count the current clock cycle to determine the clock cycle count value;

[0009] A selection module, configured to determine the clock cycle count target value according to the first setting signal;

[0010] A control module, connected to the counting module and the selection module, configured to control the ODT path to be in an enabled state and start the counting module when the level state of the ODT pin signal flips; and when the clock cycle count value reaches the clock cycle count target value, control the ODT path to be switched from the enabled state to the closed state.

[0011] In some embodiments, the control module includes a first control sub-module and a second control sub-module; wherein,

[0012] The first control sub-module is configured to generate a first intermediate signal according to the ODT pin signal; wherein, the first intermediate signal includes: before the level state of the ODT pin signal flips, the first intermediate signal is at a first level; and within a preset time after the level state of the ODT pin signal flips, the first intermediate signal changes from the first level to a second level; and after the preset time, the first intermediate signal changes from the second level to the first level.

[0013] The second control sub-module is configured to perform a logic operation on the first intermediate signal to generate an ODT enable signal; wherein, the ODT enable signal includes: when the ODT enable signal is at a third level, controlling the ODT path to be in the enabled state; and when the ODT enable signal is at a fourth level, controlling the ODT path to be in the closed state.

[0014] In some embodiments, the first level is a low level, the second level is a high level, the third level is a high level, and the fourth level is a low level.

[0015] In some embodiments, the first control sub-module includes a delay module and an exclusive-OR gate module; wherein,

[0016] The delay module is configured to delay the ODT pin signal by the preset time to obtain an ODT delayed signal.

[0017] The exclusive-OR gate module is configured to perform an exclusive-OR operation on the ODT pin signal and the ODT delayed signal to obtain the first intermediate signal.

[0018] In some embodiments, the second control sub-module includes a first flip-flop and a first NOT gate module; wherein,

[0019] The first flip-flop is a D-type flip-flop. The clock terminal (CK) of the first flip-flop is connected to the output terminal of the first control sub-module and is configured to receive the first intermediate signal; the input terminal (D) of the first flip-flop is connected to the ground terminal, and the output terminal (Q) of the first flip-flop is configured to output a second intermediate signal.

[0020] The first NOT gate module is configured to receive the second intermediate signal and perform a NOT operation on the second intermediate signal to obtain the ODT enable signal.

[0021] In some embodiments, the first flip-flop further includes a set terminal (SET); wherein,

[0022] The set terminal is used to receive a first set signal, and when the first set signal is at a high level, the ODT enable signal is controlled to be at a low level by setting the first flip-flop.

[0023] In some embodiments, the control module further includes a two-input OR gate; wherein,

[0024] The selection module is further configured to generate a target achievement signal, and the target achievement signal is used to indicate that the clock cycle count value reaches the clock cycle count target value;

[0025] The two-input OR gate is configured to perform an OR operation on the target achievement signal and a second setting signal to obtain the first set signal; wherein, the second setting signal is generated according to the setting of a mode register, and the second setting signal includes: when the second setting signal is at a fifth level, it represents that the ODT function of the chip is turned off; when the second setting signal is at a sixth level, it represents that the ODT function of the chip is turned on.

[0026] In some embodiments, the fifth level is a high level and the sixth level is a low level.

[0027] In some embodiments, the control module further includes a three-input OR gate; wherein,

[0028] The three-input OR gate is configured to perform an OR operation on the second setting signal, the first intermediate signal, and the second intermediate signal to generate a count reset signal.

[0029] In some embodiments, the counting module includes an asynchronous binary counter, and the asynchronous binary counter includes a plurality of second flip-flops, and the plurality of second flip-flops are connected in sequence.

[0030] In some embodiments, the second flip-flop is a D-type flip-flop; wherein, the input terminal (D) of each second flip-flop is connected to its own second output terminal (Q bar), and the second output terminal (Q bar) of each second flip-flop is connected to the clock terminal (CK) of the next second flip-flop.

[0031] In some embodiments, the second flip-flop further includes a first output terminal (Q) and a reset terminal (RST); wherein,

[0032] The first output terminal of the second flip-flop is configured to output a count signal;

[0033] The reset terminal of the second flip-flop is used to receive the count reset signal, and when the count reset signal is at a high level, the count signal is controlled to be at a low level by resetting the second flip-flop.

[0034] In some embodiments, the counting module further includes a clock control module, wherein,

[0035] The clock control module is configured to receive the counting reset signal and the clock signal, and generate an internal clock signal; wherein, the internal clock signal is connected to the clock terminal (CK) of the first second flip-flop among the plurality of second flip-flops, and the internal clock signal includes: when the counting reset signal is at the seventh level, stopping outputting the internal clock signal; and when the counting reset signal is at the eighth level, outputting the internal clock signal.

[0036] In some embodiments, the seventh level is a high level, and the eighth level is a low level.

[0037] In some embodiments, the clock control module includes a second NOT gate module and a two-input AND gate; wherein,

[0038] The second NOT gate module is configured to receive the counting reset signal and perform a NOT operation on the counting reset signal to obtain a third intermediate signal;

[0039] The two-input AND gate is configured to receive the third intermediate signal and the clock signal, and perform an AND operation on the third intermediate signal and the clock signal to obtain the internal clock signal.

[0040] In some embodiments, the selection module is further configured to receive the first setting signal and at least two characterization signals, and select one of the at least two characterization signals as the target achievement signal according to the first setting signal; wherein, the at least two characterization signals respectively characterize that the clock cycle count value reaches different clock cycle count target values.

[0041] In some embodiments, the selection module is specifically configured to, when the first setting signal indicates that both the additional delay AL and the parity delay PL are not enabled, select the first characterization signal as the target achievement signal and determine the clock cycle count target value as a first value; wherein, the first value is a value greater than or equal to the column address write latency CWL minus 2; or,

[0042] The selection module is specifically configured to, when the first setting signal indicates that both the additional delay AL and the parity delay PL are enabled, select the second characterization signal as the target achievement signal and determine the clock cycle count target value as a second value; wherein, the second value is a value greater than or equal to the sum of the column address write latency CWL, the additional delay AL, and the parity delay PL minus 2; or,

[0043] The selection module is specifically configured to select the third characterization signal as the target achievement signal and determine the clock cycle count target value as a third value when the first setting signal indicates that the additional latency AL is enabled and the parity latency PL is not enabled; wherein, the third value is a value greater than or equal to the sum of the column address write latency CWL and the additional latency AL minus 2; or,

[0044] The selection module is specifically configured to select the fourth characterization signal as the target achievement signal and determine the clock cycle count target value as a fourth value when the first setting signal indicates that the parity latency PL is enabled and the additional latency AL is not enabled; wherein, the fourth value is a value greater than or equal to the sum of the column address write latency CWL and the parity latency PL minus 2;

[0045] Wherein, the first characterization signal characterizes that the clock cycle count value reaches the first value, the second characterization signal characterizes that the clock cycle count value reaches the second value, the third characterization signal characterizes that the clock cycle count value reaches the third value, and the fourth characterization signal characterizes that the clock cycle count value reaches the fourth value.

[0046] In some embodiments, the counting module includes six second flip-flops, and the six second flip-flops are connected in sequence; wherein,

[0047] The first output terminal of the i-th second flip-flop is used to output the i-th count signal, where i is an integer greater than zero and less than or equal to six;

[0048] The selection module is specifically configured to receive the first setting signal, the fifth count signal, and the sixth count signal, and select the fifth count signal and the sixth count signal according to the first setting signal to generate the target achievement signal; wherein, the two input terminals of the selection module are respectively connected to the first output terminal of the fifth second flip-flop and the first output terminal of the sixth second flip-flop.

[0049] In some embodiments, the selection module is further configured to determine the target achievement signal as the fifth count signal and determine the clock cycle count target value as the first value when the first setting signal indicates that neither the additional latency AL nor the parity latency PL is enabled; or,

[0050] The selection module is further configured to determine the target achievement signal as the sixth count signal and determine the clock cycle count target value as the second value when the first setting signal indicates that at least one of the additional latency AL and the parity latency PL is enabled.

[0051] In some embodiments, the first value is 32 and the second value is 64.

[0052] In a second aspect, an embodiment of the present application provides a semiconductor memory, which includes an enable control circuit as described in any one of the first aspects.

[0053] In some embodiments, the semiconductor memory is a dynamic random access memory (DRAM) chip.

[0054] In some embodiments, the dynamic random access memory (DRAM) chip complies with the DDR4 memory specification.

[0055] An embodiment of the present application provides an enable control circuit and a semiconductor memory. The enable control circuit includes a counting module, a selection module, and a control module. Among them, the counting module is used to count the current clock cycle to determine the clock cycle count value; the selection module is used to determine the clock cycle count target value according to the first setting signal; the control module is connected to the counting module and the selection module, and is used to control the ODT path to be in an enabled state and start the counting module when the level state of the ODT pin signal flips; and when the clock cycle count value reaches the clock cycle count target value, control the ODT path to switch from the enabled state to the closed state. In this way, the enable state of the ODT path is controlled according to whether the clock cycle count value reaches the clock cycle count target value, so that the ODT path can be controlled to be closed when it is not required to work, thereby avoiding current waste and achieving the purpose of saving power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 A schematic structural diagram of an ODT function circuit provided by the related art;

[0057] Figure 2 A timing diagram in a synchronous ODT mode provided by the related art;

[0058] Figure 3 A schematic framework diagram for controlling the operation of the ODT path provided by an embodiment of the present application;

[0059] Figure 4 A schematic composition diagram of an enable control circuit provided by an embodiment of the present application;

[0060] Figure 5 Another schematic composition diagram of an enable control circuit provided by an embodiment of the present application;

[0061] Figure 6 A timing diagram of an ODT pin signal, an ODT delay signal, and a first intermediate signal provided by an embodiment of the present application;

[0062] Figure 7 A schematic specific structure diagram of an enable control circuit provided by an embodiment of the present application;

[0063] Figure 8 A timing schematic diagram of an enabling control circuit provided by an embodiment of the present application;

[0064] Figure 9 A schematic diagram of the composition structure of a semiconductor memory provided by an embodiment of the present application. Detailed implementation manners

[0065] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the related application, rather than limiting the application. In addition, it should be noted that, for the sake of description, only the parts related to the related application are shown in the drawings.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application, and are not intended to limit this application.

[0067] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0068] It should be noted that the terms "first / second / third" involved in the embodiments of the present application are only used to distinguish similar objects, and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0069] Before further elaborating on the embodiments of the present application, the nouns and terms involved in the embodiments of the present application are described first. The nouns and terms involved in the embodiments of the present application are applicable to the following explanations:

[0070] Dynamic Random Access Memory (DRAM)

[0071] Double Data Rate (DDR)

[0072] 4th Generation DDR (DDR4)

[0073] On Die Termination (ODT)

[0074] Termination Resistance, RTT

[0075] Column Address Strobe Write Latency, CWL

[0076] CAS Latency, CL

[0077] Additive Latency, AL

[0078] Parity Latency, PL

[0079] Delay-Locked Loop, DLL

[0080] Mode Register, MR

[0081] Mode Register Set, MRS

[0082] With the rapid development of semiconductor processes, the transmission rate of signals is getting faster and faster, leading to increasingly prominent signal integrity problems. During the propagation of high-speed signals, in order to better improve the signal integrity of data, in DDR3 and DDR4 designs, an ODT resistor is added separately, that is, the impedance of the transmission line is matched with the ODT resistor, reducing the energy loss and reflection of the signal during transmission, thereby ensuring the integrity of the signal received at the receiving end.

[0083] Taking DDR4 DRAM as an example, DDR4 DRAM supports the ODT function, which can adjust the termination resistance of the DQ, DQS_t / c, DM_n, and TDQS_t / c ports of each device by controlling the ODT pin, write command, or setting the default resistance value in the mode register. In addition, the purpose of the ODT function is to reduce reflections and effectively improve the signal integrity on the memory interface by independently controlling the termination resistance of all or any one DRAM by the controller. As Figure 1 shown, it shows a schematic structural diagram of an ODT function circuit provided by the related art. In Figure 1Among them, the ODT functional circuit can at least include a switch S1, a termination resistor RTT, and a power supply VDDQ. One end of the switch S1 is connected to one end of the termination resistor RTT, the other end of the termination resistor RTT is connected to the power supply VDDQ, and the other end of the switch S1 is connected to other circuitry (To other circuity like), as well as the DQ, DQS, DM, and TDQS ports. It should be noted that DQS can be a pair of differential data strobe signals DQS_t and DQS_c, and TDQS can be a pair of differential data strobe signals TDQS_t and TDQS_c; in other words, DDR4 DRAM only supports differential data strobe signals and does not support single-ended data strobe signals.

[0084] In addition, Figure 1 the switch S1 in is controlled by the ODT control logic. The ODT control logic includes an external ODT pin input, mode register configuration, and other control information. The value of RTT is controlled by the configuration information in the mode register. In addition, if the ODT pin control is ignored after the RTT_NOM is disabled in the self-refresh mode or when MR1{A10,A9,A8}={0,0,0}.

[0085] Specifically, the ODT function of DDR4 DRAM has four states: termination resistor disabled, RTT_WR, RTT_NOM, and RTT_PARK. When the configuration bits such as MR1{A10,A9,A8} or MR2{A10:A9} or MR5{A8:A6} are not all zero, the ODT function is enabled. In this case, the actual value of the ODT resistor is determined by these configuration bits. After entering the self-refresh mode, DDR4 DRAM automatically disables the ODT function and sets all termination resistors to the high impedance (Hi-Z) state to discard all mode register settings.

[0086] It should also be noted that the embodiment of the present application provides a synchronous ODT mode. When the DLL is enabled and locked, the synchronous ODT mode can be selected. In the synchronous ODT mode, RTT_NOM will be enabled after DODTLon clock cycles after the ODT pin signal becomes high level and is sampled by the first clock rising edge. RTT_NOM will be disabled after DODTLoff clock cycles after the ODT pin signal becomes low level and is sampled by the first clock rising edge. The two parameters DODTLon and DODTLoff are related to WL (WL = CWL + AL + PL), DODTLon = WL - 2, DODTLoff = WL - 2.

[0087] In the synchronous ODT mode, the additional latency (AL) and the parity latency (PL) also directly affect the ODT latency (which can also be referred to as "delay"), as shown in Table 1 specifically.

[0088] Table 1

[0089]

[0090] Furthermore, in the synchronous ODT mode, the following timing parameters are all applicable: DODTLon, DODTLoff, tADCmin, tADC max, etc. When changing the ODT resistance value, for example, changing from RTT_PARK to RTT_NOM, the maximum and minimum values of the RTT change time jitter value at this time are: tADC max and tADC min; these parameters are applicable to the synchronous ODT mode and the data termination resistor disable mode. Taking Figure 2 as an example, it shows a timing schematic diagram in a synchronous ODT mode provided by the related technology. As Figure 2 shown, assuming CWL = 9, AL = 0, PL = 0, then DODTLon = WL - 2 = 7, DODTLoff = WL - 2 = 7. Additionally, Figure 2 the black part in

[0091] is the RTT change time jitter value.

[0092] It should be noted that the timings DODTLon and DODTLoff, that is, the ODT latency, are related to the values of CWL, AL, and PL. Therefore, a shift register needs to be set in the ODT path to shift several clock cycles, so as to meet the timing requirements related to CWL, AL, and PL. Additionally, the shift register requires a clock signal (represented by CLK).

[0093] As Figure 3As shown, it shows a schematic diagram of a framework for controlling the operation of an ODT path provided by an embodiment of the present application. In Figure 3 , it may include a Receiver, an ODT Enable Module, a Shift Register, a Latency Control Module, and an RTT control Module. Among them, the function of the Receiver is to receive the ODT pin signal and the clock signal, and the RTT control Module is to control the switching of the RTT resistance value. In addition, the entire ODT path is a very complex path, and in this ODT path, there are physical delays (independent of the clock cycle) and clock delays (the delay is an integer multiple of the clock cycle). Since in Figure 3 , the final required delay of the entire path is an integer multiple of the clock cycle, that is, DODTLon and DODTLoff. Therefore, the role of this delay control module is to use the DLL to synchronize the signal at the end of the ODT path (that is, Figure 1 the control signal of switch S1 in) with the clock signal. In this way, by compensating for the physical delay, the delay of the entire path is an integer multiple of the clock cycle, and the resistance value control of the RTT can be finally achieved.

[0094] In the related art, the ODT enable module mainly uses simple logic control. As shown in Table 2, it controls the enabling or disabling of the CLK used for the ODT path by identifying whether the synchronous ODT mode in the MRS setting is enabled. For example, if MR1 <a10:a8>If it is set to the Disabled state, then the signal level state at the ODT pin is ineffective at this time, and the ODT path and CLK are not required, so CLK can be disabled, and then the ODT path is also disabled, which can achieve the effect of power saving.

[0095] However, as shown in Table 2, there is currently a situation where the MRS setting is in the Enabled state, but the signal level state at the ODT pin has not changed; this situation also does not require the ODT path to work, but since CLK is not turned off, current waste is caused, increasing power consumption.

[0096] Table 2

[0097]

[0098] Based on this, the embodiment of the present application provides an enable control circuit, which can not only enable the ODT path within a certain time after detecting the change in the level state of the ODT pin, that is, the ODT path is in the enabled state; but also can close the ODT path after ensuring that the resistance value change of the RTT is completed, which can achieve the purpose of power saving.

[0099] The following will describe each embodiment of the present application in detail with reference to the drawings.

[0100] In an embodiment of the present application, refer to Figure 4 , which shows a schematic structural diagram of an enable control circuit 40 provided by the embodiment of the present application. As Figure 4 shown, the enable control circuit 40 may include a counting module 41, a selection module 42, and a control module 43; among them,

[0101] The counting module 41 is used to count the current clock cycle to determine the clock cycle count value;

[0102] The selection module 42 is used to determine the clock cycle count target value according to the first setting signal;

[0103] The control module 43 is connected to the counting module 41 and the selection module 42, and is used to control the ODT path to be in the enabled state and start the counting module 41 when the level state of the ODT pin signal flips; and when the clock cycle count value reaches the clock cycle count target value, control the ODT path to switch from the enabled state to the closed state.

[0104] It should be noted that the enable control circuit 40 of the embodiment of the present application is applied to Figure 3 The ODT enabling module in it. Here, if the signal level state at the ODT pin flips, for example, from low level to high level, or from high level to low level, then the resistance value of the RTT will change after a delay of DODTLon or DODTLoff clock cycles. During this process, it is necessary to control the ODT path to be in the enabled state; then after the resistance value change of the RTT is completed, in order to save power, at this time, the ODT path can also be controlled to change from the enabled state to the off state.

[0105] It should also be noted that, in order to ensure the completion of the resistance value change of the RTT, the embodiment of the present application can set a clock cycle count target value, and this clock cycle count target value is related to DODTLon or DODTLoff. Since both DODTLon and DODTLoff are related to CWL, AL, and PL, that is to say, the setting of the clock cycle count target value is related to CWL, AL, and PL. In the embodiment of the present application, the first setting signal is generated according to whether AL and / or PL is enabled, so that the selection module 42 can determine the clock cycle count target value according to whether AL and / or PL is enabled.

[0106] In this way, the counting module 41 can determine whether the clock cycle count value reaches the clock cycle count target value, and the selection module 42 can determine the clock cycle count target value. Then, through the control module 43, when the signal level state of the ODT pin flips, the ODT path can be controlled to be in the enabled state and the counting module can be started; and when the clock cycle count value reaches the clock cycle count target value, the ODT path can be controlled to change from the enabled state to the off state, so as to achieve the purpose of saving power.

[0107] In some embodiments, based on Figure 4 the enabling control circuit 40 shown, referring to Figure 5 , the control module 43 may include a first control sub-module 431 and a second control sub-module 432; where

[0108] The first control sub-module 431 is used to generate a first intermediate signal according to the ODT pin signal;

[0109] The second control sub-module 432 is used to perform a logical operation on the first intermediate signal to generate an ODT enabling signal.

[0110] Here, for the first intermediate signal, the first intermediate signal can be represented by NET01. Among them, the first intermediate signal can include: before the level state of the ODT pin signal flips, the first intermediate signal is at the first level; and within a preset time after the level state of the ODT pin signal flips, the first intermediate signal changes from the first level to the second level; and after the preset time, the first intermediate signal changes from the second level to the first level.

[0111] For the ODT enable signal, the ODT enable signal can be represented by ODT_CLK_EN. Among them, the ODT enable signal can include: when the ODT enable signal is at the third level, controlling the ODT path to be in the enabled state; and when the ODT enable signal is at the fourth level, controlling the ODT path to be in the closed state.

[0112] In a specific example, the first level can be a low level, the second level can be a high level, the third level can be a high level, and the fourth level can be a low level.

[0113] Furthermore, for the first control sub-module 431, in some embodiments, as Figure 5 shown, the first control sub-module 431 can include a delay module 4311 and an exclusive-OR gate module 4312; among them,

[0114] The delay module 4311 is used to delay the ODT pin signal by a preset time to obtain an ODT delay signal;

[0115] The exclusive-OR gate module 4312 is used to perform an exclusive-OR operation on the ODT pin signal and the ODT delay signal to obtain the first intermediate signal.

[0116] Here, the preset time is the time by which the ODT pin signal is delayed by the delay module 4311, and this preset time can also control the pulse width of the first intermediate signal. See Figure 6 , which shows a timing diagram of an ODT pin signal, an ODT delay signal, and a first intermediate signal provided by an embodiment of the present application. In Figure 6 , ODT represents the ODT pin signal, ODT_delay represents the ODT delay signal, and NET01 represents the first intermediate signal. According to Figure 6 it can be seen that before the level state of the ODT pin signal flips, the first intermediate signal is at a low level; and within a preset time after the level state of the ODT pin signal flips, the first intermediate signal changes from a low level to a high level; and after the preset time, the first intermediate signal changes from a high level to a low level.

[0117] It should be noted that due to the physical delay introduced by the exclusive-OR gate module 4312, the moment when the level state of the ODT pin signal flips is not aligned with the moment when the first intermediate signal changes from low level to high level on the time axis.

[0118] Furthermore, for the second control sub-module 432, in some embodiments, as Figure 5 shown, the second control sub-module 432 may include a first flip-flop 4321 and a first NOT gate module 4322; wherein,

[0119] The first flip-flop 4321 is a D-type flip-flop. Here, the first flip-flop 4321 may include a clock terminal (CK), an input terminal (D), and an output terminal (Q); wherein, the clock terminal (CK) of the first flip-flop 4321 is connected to the output terminal of the first control sub-module 431 for receiving the first intermediate signal; the input terminal (D) of the first flip-flop 4321 is connected to the ground terminal, and the output terminal (Q) of the first flip-flop 4321 is used to output a second intermediate signal;

[0120] The first NOT gate module 4322 is configured to receive the second intermediate signal and perform a NOT operation on the second intermediate signal to obtain an ODT enable signal.

[0121] It should be noted that for the first flip-flop 4321, the first flip-flop 4321 may further include a set terminal (SET); wherein,

[0122] The set terminal (SET) is configured to receive a first set signal, and when the first set signal is at a high level, control the ODT enable signal to be at a low level by setting the first flip-flop 4321.

[0123] Here, the ground terminal may be connected to a global ground signal, denoted by VSS!; and the first set signal may be denoted by SET.

[0124] It should also be noted that a D-type flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF) is an information storage device with a memory function and two stable states, and is the most basic logic unit for constructing various sequential circuits, and is also an important unit circuit in digital logic circuits. The D-type flip-flop has two stable states, namely "0" and "1", and can flip from one stable state to another under the action of certain external signals.

[0125] Specifically, the first flip-flop 4321 belongs to a type of D-type flip-flop. In the embodiments of the present application, the first flip-flop 4321 may include an input terminal (D), a clock terminal (CK), a set terminal (SET), and an output terminal (Q).

[0126] Further, for the first setting signal, in some embodiments, as Figure 5 shown, the control module 43 may further include a two-input OR gate 433; wherein,

[0127] The selection module 42 is further configured to generate a target achievement signal, which is used to indicate that the clock cycle count value reaches the clock cycle count target value;

[0128] The two-input OR gate 433 is configured to perform an OR operation on the target achievement signal and the second setting signal to obtain the first setting signal.

[0129] Here, the second setting signal is generated according to the setting of the mode register, and the second setting signal can be represented by MRS_DIST. Among them, the second setting signal may include: when the second setting signal is at the fifth level, it represents that the ODT function of the chip is turned off; when the second setting signal is at the sixth level, it represents that the ODT function of the chip is turned on.

[0130] In a specific example, the fifth level is a high level and the sixth level is a low level.

[0131] That is to say, if the second setting signal is at a high level, it means that the ODT function of the chip is turned off, and at this time, it is no longer necessary to execute the enabling control circuit 40 of the present application; if the second setting signal is at a low level, it means that the ODT function of the chip is turned on, and it is still necessary to further combine the ODT pin signal to determine whether to enable the ODT path.

[0132] It should also be noted that if the second setting signal is at a high level, it can be determined that the first setting signal is at a high level; in this way, when the first setting signal is at a high level, the first flip-flop can be set to control the ODT enable signal to be at a low level, so that the ODT path is in an enabled off state.

[0133] Further, in some embodiments, as Figure 5 shown, the control module 43 may further include a three-input OR gate 434; wherein,

[0134] The three-input OR gate 434 is configured to perform an OR operation on the second setting signal, the first intermediate signal and the second intermediate signal to generate a count reset signal.

[0135] Here, the count reset signal can be represented by CNT_RST. After obtaining the count reset signal, the count reset signal can be input into the counting module 41. On the one hand, it can be directly used for the reset and clear operation of the counting module 41. On the other hand, after performing a logical operation on it, the clock signal of the counting module 41 can also be masked.

[0136] Further, in some embodiments, as Figure 5 As shown, the counting module 41 may include an asynchronous binary counter 411.

[0137] In a specific example, the asynchronous binary counter 411 may include a plurality of second flip - flops 4111, and these plurality of second flip - flops 4111 are connected in sequence.

[0138] In the embodiments of the present application, the second flip - flop 4111 is a D - type flip - flop; wherein, the input terminal (D) of each second flip - flop is connected to its own second output terminal (Q bar, or denoted as QN), and the second output terminal (Q bar) of each second flip - flop is connected to the clock terminal (CK) of the next second flip - flop.

[0139] In addition, the second flip - flop 4111 may further include a first output terminal (Q) and a reset terminal (RST); wherein,

[0140] The first output terminal (Q) of the second flip - flop is used to output a counting signal;

[0141] The reset terminal (RST) of the second flip - flop is used to receive a counting reset signal, and when the counting reset signal is at a high level, by resetting the second flip - flop, control the counting signal to be at a low level.

[0142] Specifically, the second flip - flop 4111 also belongs to a type of D - type flip - flop. In the embodiments of the present application, the second flip - flop 4111 may include an input terminal (D), a clock terminal (CK), a reset terminal (RST), a first output terminal (Q) and a second output terminal (Q bar), and may even include a set terminal (SET). Here, the set terminal may be connected to the ground terminal. In a specific example, the set terminal of the second flip - flop is used to receive a second set signal, and the second set signal may be a global ground signal, denoted as VSS!.

[0143] Furthermore, in some embodiments, as Figure 5 shown, the counting module 41 may further include a clock control module 412, wherein,

[0144] The clock control module 412 is used to receive a counting reset signal and a clock signal, and generate an internal clock signal.

[0145] Here, the internal clock signal is connected to the clock terminal (CK) of the first second flip - flop among the plurality of second flip - flops, and is used to provide a clock signal to the counting module 41. Among them, the internal clock signal may include: when the counting reset signal is at a seventh level, stop outputting the internal clock signal; and when the counting reset signal is at an eighth level, output the internal clock signal.

[0146] In a specific example, the seventh level is a high level and the eighth level is a low level.

[0147] Furthermore, for the clock control module 412, in some embodiments, as Figure 5 shown, the clock control module 412 may include a second NOT gate module 4121 and a two-input AND gate 4122; wherein,

[0148] The second NOT gate module 4121 is configured to receive a count reset signal and perform a NOT operation on the count reset signal to obtain a third intermediate signal;

[0149] The two-input AND gate 4122 is configured to receive the third intermediate signal and a clock signal, and perform an AND operation on the third intermediate signal and the clock signal to obtain an internal clock signal.

[0150] It should be noted that since the count reset signal is related to the second setting signal, thus, if the second setting signal is a high level, it can be determined that the count reset signal is a high level; in this way, when the count reset signal is a high level, the asynchronous binary counter 411 can be turned off, achieving the technical effect of saving current.

[0151] It should also be noted that the internal clock signal used by the counting module 41 itself is also controlled by the count reset signal. In this way, after the counting ends, since the count reset signal is a high level, the internal clock signal used by the counting module is also turned off, thereby being able to further save current.

[0152] Furthermore, in some embodiments, the selection module 42 is further configured to receive a first setting signal and at least two characterization signals, and select one of the at least two characterization signals as a target achievement signal according to the first setting signal; wherein, the at least two characterization signals respectively characterize that the clock cycle count value reaches different clock cycle count target values.

[0153] Here, for the selection module 42, the first setting signal may be generated according to whether the additional delay AL and / or the parity delay PL is enabled, and the first setting signal is represented by AL_DIST. The following will describe it in four cases: both the additional delay AL and the parity delay PL are not enabled, both the additional delay AL and the parity delay PL are enabled, the additional delay AL is enabled and the parity delay PL is not enabled, and the parity delay PL is enabled and the additional delay AL is not enabled.

[0154] In a possible implementation manner, the selection module 42 is specifically configured to select the first characterization signal as the target achievement signal and determine the clock cycle count target value as a first value when the first setting signal indicates that both the additional delay AL and the parity delay PL are not enabled; wherein, the first value is a value greater than or equal to the value obtained by subtracting 2 from the column address write latency CWL.

[0155] In another possible implementation, the selection module 42 is specifically configured to select the second characterization signal as the target achievement signal and determine the clock cycle count target value as the second value when the first setting signal indicates that both the additional delay AL and the parity delay PL are enabled; wherein, the second value is a value greater than or equal to the sum of the column address write latency CWL, the additional delay AL, and the parity delay PL minus 2.

[0156] In yet another possible implementation, the selection module 42 is specifically configured to select the third characterization signal as the target achievement signal and determine the clock cycle count target value as the third value when the first setting signal indicates that the additional delay AL is enabled and the parity delay PL is not enabled; wherein, the third value is a value greater than or equal to the sum of the column address write latency CWL and the additional delay AL minus 2.

[0157] In still another possible implementation, the selection module 42 is specifically configured to select the fourth characterization signal as the target achievement signal and determine the clock cycle count target value as the fourth value when the first setting signal indicates that the parity delay PL is enabled and the additional delay AL is not enabled; wherein, the fourth value is a value greater than or equal to the sum of the column address write latency CWL and the parity delay PL minus 2.

[0158] Here, the first characterization signal represents that the clock cycle count value reaches the first value, the second characterization signal represents that the clock cycle count value reaches the second value, the third characterization signal represents that the clock cycle count value reaches the third value, and the fourth characterization signal represents that the clock cycle count value reaches the fourth value.

[0159] It should also be noted that the specific values of CWL are shown in Table 3. It can be seen from Table 3 that the maximum value of CWL is 20. The specific values of AL are shown in Table 4. It can be seen from Table 4 that the maximum value of AL is CL - 1. Among them, the specific values of CL are shown in Table 5. It can be seen from Table 5 that the maximum value of CL is 32, so the maximum value of AL is 31. The specific values of PL are shown in Table 6. It can be seen from Table 6 that the maximum value of PL is 8.

[0160] Table 3

[0161]

[0162] Table 4

[0163]

[0164] Table 5

[0165]

[0166]

[0167] Table 6

[0168] A2 A1 A0 PL Speed Bin 0 0 0 Disable 0 0 1 4 1600,1866,2133 0 1 0 5 2400,2666 0 1 1 6 2933,3200 1 0 0 8 RFU 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved

[0169] It should be noted that the above Tables 3 to 6 are from the relevant standard documents of DDR4 DRAM. Among them, A0, A1, A2, A3, A4, A5, A6, and A12 are bits in the corresponding mode register. According to Tables 3 to 6, the maximum value of CWL can be obtained as 20, the maximum value of AL is 31, and the maximum value of PL is 8. Then, according to the selection module 42, when the first setting signal indicates that both the additional latency AL and the parity latency PL are not enabled, the first value at this time is a value greater than or equal to 18; when the first setting signal indicates that both the additional latency AL and the parity latency PL are enabled, the second value at this time is a value greater than or equal to 57; when the first setting signal indicates that the additional latency AL is enabled and the parity latency PL is not enabled, the third value at this time is a value greater than or equal to 49; when the first setting signal indicates that the parity latency PL is enabled and the additional latency AL is not enabled, the fourth value at this time is a value greater than or equal to 26; in this way, the clock cycle count target value can be determined.

[0170] In short, this embodiment provides an enable control circuit, which includes a counting module, a selection module, and a control module. Among them, the counting module is used to count the current clock cycle to determine the clock cycle count value; the selection module is used to determine the clock cycle count target value according to the first setting signal; the control module is connected to the counting module and the selection module, and is used to control the ODT path to be in the enabled state and start the counting module when the level state of the ODT pin signal flips; and when the clock cycle count value reaches the clock cycle count target value, control the ODT path to switch from the enabled state to the off state. In this way, according to whether the clock cycle count value reaches the clock cycle count target value to control the enable state of the ODT path, it is possible to enable the ODT path within a certain time after detecting the change in the level state of the ODT pin, that is, the ODT path is in the enabled state; and after ensuring that the resistance value change of the RTT is completed, the ODT path can also be closed, which can achieve the purpose of reducing current and saving power.

[0171] In another embodiment of the present application, in combination with Figure 5 , taking the counting module 41 including six second flip-flops and the selection module 42 only receiving two characterization signals as an example, and these two characterization signals are the counting signals output by the fifth second flip-flop and the sixth second flip-flop respectively.

[0172] In some embodiments, the counting module 41 may include six second flip-flops, and these six second flip-flops are connected in sequence; among them,

[0173] The first output terminal (Q) of the i-th second flip-flop is used to output the i-th counting signal, where i is an integer greater than zero and less than or equal to six;

[0174] The selection module 42 is specifically configured to receive the first setting signal, the fifth counting signal, and the sixth counting signal, and select the fifth counting signal and the sixth counting signal according to the first setting signal to generate a target achievement signal; wherein, the two input terminals of the selection module are respectively connected to the first output terminal (Q) of the fifth second flip-flop and the first output terminal (Q) of the sixth second flip-flop.

[0175] It should be noted that the i-th counting signal is denoted as Q Indications. Specifically, the fifth counting signal can be represented by Q<5>, which is output from the first output terminal (Q) of the fifth second flip-flop; the sixth counting signal can be represented by Q<6>, which is output from the first output terminal (Q) of the sixth second flip-flop.

[0176] It should also be noted that since the selection module 42 only receives two characterization signals (the fifth counting signal and the sixth counting signal), the first setting signal either indicates that neither the additional delay AL nor the parity delay PL is enabled, or is used to indicate that at least one of the additional delay AL and the parity delay PL is enabled. Thus, in a specific example, the selection module 42 is further configured to determine the target achievement signal as the fifth counting signal and determine the clock cycle count target value as the first value when the first setting signal indicates that neither the additional delay AL nor the parity delay PL is enabled; or, the selection module 42 is further configured to determine the target achievement signal as the sixth counting signal and determine the clock cycle count target value as the second value when the first setting signal indicates that at least one of the additional delay AL and the parity delay PL is enabled.

[0177] It should also be noted that when neither the additional delay AL nor the parity delay PL is enabled, the clock cycle count target value (i.e., the first value) at this time is a value greater than or equal to 18; when at least one of the additional delay AL and the parity delay PL is enabled, the clock cycle count target value (i.e., the second value) at this time is a value greater than or equal to 57. Additionally, when the fifth counting signal becomes high level (i.e., "1"), the clock cycle count value reaches 32 at this time; when the sixth counting signal becomes high level (i.e., "1"), the clock cycle count value reaches 64 at this time; therefore, in a specific example, the first value can be 32 and the second value can be 64.

[0178] Exemplarily, refer to Figure 7 , which shows a schematic structural diagram of an enable control circuit 40 provided by an embodiment of the present application. As Figure 7 shown, the enable control circuit 40 may include a delay module 701, an exclusive-OR gate 702, a first flip-flop 703, a first NOT gate 704, a three-input OR gate 705, a second NOT gate 706, a two-input AND gate 707, an asynchronous binary counter 708, a selection module 709, and a two-input OR gate 710. The specific connection relationship is shown in detail in Figure 7 . Among them, the first flip-flop 703 is a D-type flip-flop. The asynchronous binary counter 708 may include six second flip-flops, and the second flip-flop may also be a D-type flip-flop. Moreover, the input terminal (D) of each second flip-flop is connected to its own second output terminal (QN), and the second output terminal (QN) of each second flip-flop is connected to the clock terminal (CK) of the next second flip-flop.

[0179] In Figure 7 Among them, the ODT pin signal is represented by ODT, the first intermediate signal output by the exclusive OR gate 702 is represented by NET01, the ODT enable signal output by the first NOT gate 704 is represented by ODT_CLK_EN, the count reset signal output by the three-input OR gate 705 is represented by CNT_RST, and the count signals output by the first output terminals (Q) of the six second flip-flops are successively represented by Q<1>, Q<2>, …, Q<5>, Q<6>. In addition, CLK represents the clock signal, SET represents the first set signal, AL_DIST represents the first setting signal, MRS_DIST represents the second setting signal, and VSS! represents the global ground signal.

[0180] Thus, according to Figure 7 the circuit structure shown, its corresponding signal timing diagram is as Figure 8 shown. In Figure 8 it, the curve with an arrow represents the causal relationship. Specifically, when the ODT pin signal changes from low level to high level, after being delayed by the delay module 701, it is still at low level. Then, when the two are input to the exclusive OR gate 702, a high level will be output, that is, the NET01 signal changes from low level to high level. The reason for the ODT_CLK_EN signal to change from low level to high level is that the first flip-flop 703 (i.e., D flip-flop) is triggered at the moment when the NET01 signal changes from low level to high level, and the input of the D terminal is used as the output of the Q terminal. At this time, the output of the Q terminal is at low level; after passing through the first NOT gate 704, it becomes high level, that is, the ODT_CLK_EN signal changes from low level to high level, enabling the ODT path to be in the enabled state.

[0181] In addition, when the MRS_DIST signal is at a low level, when the NET01 signal changes from a high level to a low level, since the output of the Q terminal of the first flip-flop 703 is at a low level, the three signals input to the three-input OR gate 705 will output a low level, that is, the CNT_RST signal changes from a high level to a low level. At this time, the asynchronous binary counter 708 starts counting. Taking the clock cycle count target value of 32tck as an example, after the clock cycle count reaches 32tck, the count value becomes 010000, and at this time the Q<5> signal changes from a low level to a high level; when neither the additional delay AL nor the parity delay PL is enabled and the AL_DIST is at a high level, since the Q<5> signal is at a high level, a high level will be output through the selection module 709, and when it is input to the two-input OR gate 710 together with the MRS_DIST signal, a high level will be output, that is, the SET signal changes from a low level to a high level. Or, taking the clock cycle count target value of 64tck as an example, after the clock cycle count reaches 64tck, the count value becomes 100000, and at this time the Q<6> signal changes from a low level to a high level; when at least one of the additional delay AL and the parity delay PL is enabled and the AL_DIST is at a low level, since the Q<6> signal is at a high level, a high level will be output through the selection module 709, and when it is input to the two-input OR gate 710 together with the MRS_DIST signal, a high level will be output, that is, the SET signal can also change from a low level to a high level.

[0182] Further, when the SET signal is at a high level, the first flip-flop 703 is set, so that the output of the Q terminal of the first flip-flop 703 is at a high level. On the one hand, when the output of the Q terminal of the first flip-flop 703 is at a high level, the CNT_RST signal can change from a low level to a high level through the three-input OR gate 705, so as to be able to turn off the asynchronous binary counter 708 and the internal clock signal of the asynchronous binary counter, making the Q<5> signal change from a high level to a low level; since the Q<5> signal is at a low level and the MRS_DIST signal is at a low level, when the two are input to the two-input OR gate 710, the SET signal will change from a high level to a low level. On the other hand, when the output of the Q terminal of the first flip-flop 703 is at a high level, it becomes a low level after passing through the first NOT gate 704, that is, the ODT_CLK_EN signal changes from a high level to a low level, making the ODT path in a closed state, so as to achieve the purpose of power saving.

[0183] It should be noted that Figure 7 The shown circuit structure is to generate the enable signal ODT_CLK_EN of the ODT path. When the level state of the ODT_CLK_EN is at a high level, the clock signal of the ODT path can be enabled, and then the ODT path is enabled. When the level state of the ODT_CLK_EN is at a low level, the clock signal of the ODT path is turned off, and then the ODT path is turned off.

[0184] It should also be noted that if the level state of MRS_DIST is high level, it means that the ODT function can be disabled through MRS, that is, the signal level state at the ODT pin has no effect. In this case, the level state of ODT_CLK_EN is low level, which also realizes the ODT function of the related technology. And since the level state of CNT_RST is high level, the asynchronous binary counter 708 and the internal clock signal of the asynchronous binary counter can also be turned off, thereby saving the current of this circuit itself. In addition, the delay module 701 can control the pulse width of NET01.

[0185] Based on the foregoing content, the relationship between ODT delay and CWL, AL, and PL can be known. To ensure the ODT delay, the time when the level state of ODT_CLK_EN is high level must ensure that the ODT path completes the shift of the ODT delay. If neither AL nor PL is enabled, the maximum possible value of CWL is 20 (DDR4 specification). Therefore, it can be set that after the asynchronous binary counter 708 counts to 32 clock cycles, the level state of ODT_CLK_EN becomes low level to turn off the clock signal of the ODT path. If at least one of AL and PL is enabled, considering the maximum AL = 31, PL = 8, and CWL = 20, it can be set that after the asynchronous binary counter 708 counts to 64 clock cycles, the level state of ODT_CLK_EN becomes low level to turn off the clock signal of the ODT path. This not only ensures that the timing of the ODT path can be realized, but also reduces the oscillation time of the clock signal of the ODT path and reduces the current consumed by the ODT path.

[0186] In addition, in Figure 7 the internal clock signal used by the asynchronous binary counter 708 itself is also controlled by the CNT_RST signal. After the counting ends, since the CNT_RST signal is high level, the internal clock signal used by the asynchronous binary counter 708 is also turned off, and the current consumed by the two-input AND gate 707 is also reduced, thereby further saving current.

[0187] Through this embodiment, the specific implementation of the foregoing embodiment is elaborated in detail. It can be seen from this that through the technical solution of the foregoing embodiment, the ODT path can be enabled within a certain time after detecting the change in the level state of the ODT pin, that is, the ODT path is in an enabled state; and after ensuring that the resistance value change of RTT is completed, the ODT path can also be turned off, which can achieve the purpose of reducing current and saving power consumption.

[0188] In another embodiment of the present application, see Figure 9 , which shows a schematic structural diagram of a semiconductor memory 90 provided by an embodiment of the present application. As Figure 9 shown, the semiconductor memory 90 may include the enable control circuit 40 described in any one of the foregoing embodiments.

[0189] In an embodiment of the present application, the semiconductor memory 90 may be a DRAM chip.

[0190] Further, in some embodiments, the DRAM chip complies with the DDR4 memory specification.

[0191] In an embodiment of the present application, the enable control circuit 40 specifically relates to the enable control of the ODT path in a DDR4 DRAM chip. The enable control circuit 40 can generate an enable signal and achieve the effect of power saving by controlling the clock signal of the ODT path.

[0192] Specifically, since the semiconductor memory 90 includes the enable control circuit 40, in this way, the enable state of the ODT path can be controlled according to whether the clock cycle count value reaches the clock cycle count target value, and it is also possible to enable the ODT path within a certain time after detecting the change in the level state of the ODT pin, that is, the ODT path is in an enabled state; and after ensuring that the resistance value change of the RTT is completed, the ODT path can be closed, which can achieve the purpose of reducing current and saving power consumption.

[0193] The above is only a preferred embodiment of the present application and is not used to limit the protection scope of the present application.

[0194] It should be noted that in the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including that element.

[0195] The serial numbers of the above embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0196] The methods disclosed in several method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments.

[0197] The features disclosed in several product embodiments provided by the present application can be arbitrarily combined without conflict to obtain new product embodiments.

[0198] The features disclosed in several method or device embodiments provided by this application can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

[0199] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims

1. An enabling control circuit, characterized in that, The enable control circuit includes: a counting module for counting the current clock cycle to determine a clock cycle count value; a selection module for determining a clock cycle count target value according to a first setting signal; a control module connected to the counting module and the selection module, configured to control the ODT path to be in an enabled state and start the counting module when the level state of the ODT pin signal flips; and when the clock cycle count value reaches the clock cycle count target value, control the ODT path to transition from the enabled state to a closed state; the control module includes a first control sub-module and a second control sub-module; wherein, the first control sub-module is configured to generate a first intermediate signal according to the ODT pin signal; wherein, the first intermediate signal includes: before the level state of the ODT pin signal flips, the first intermediate signal is at a first level; and within a preset time after the level state of the ODT pin signal flips, the first intermediate signal changes from the first level to a second level; and after the preset time, the first intermediate signal changes from the second level to the first level; the second control sub-module is configured to perform a logic operation on the first intermediate signal to generate an ODT enable signal; wherein, the ODT enable signal includes: when the ODT enable signal is at a third level, controlling the ODT path to be in the enabled state; and when the ODT enable signal is at a fourth level, controlling the ODT path to be in the closed state; the first control sub-module includes a delay module and an exclusive-OR gate module; wherein, the delay module is configured to delay the ODT pin signal by the preset time to obtain an ODT delay signal; the exclusive-OR gate module is configured to perform an exclusive-OR operation on the ODT pin signal and the ODT delay signal to obtain the first intermediate signal.

2. The enabling control circuit according to claim 1, characterized in that, The first level is a low level, the second level is a high level, the third level is a high level, and the fourth level is a low level.

3. The enabling control circuit according to claim 1, wherein the second control sub-module includes a first flip-flop and a first NOT gate module; wherein, the first flip-flop is a D-type flip-flop, the clock terminal (CK) of the first flip-flop is connected to the output terminal of the first control sub-module for receiving the first intermediate signal; the input terminal (D) of the first flip-flop is connected to the ground terminal, and the output terminal (Q) of the first flip-flop is configured to output a second intermediate signal; the first NOT gate module is configured to receive the second intermediate signal and perform a NOT operation on the second intermediate signal to obtain the ODT enable signal.

4. The enabling control circuit according to claim 3, wherein the first flip-flop further includes a set terminal (SET); wherein, the set terminal is configured to receive a first set signal, and when the first set signal is at a high level, control the ODT enable signal to be at a low level by setting the first flip-flop.

5. The enabling control circuit according to claim 4, wherein the control module further includes a two-input OR gate; wherein, The selection module is further configured to generate a target achievement signal for indicating that the clock cycle count value reaches the clock cycle count target value; The two-input OR gate is configured to perform an OR operation on the target achievement signal and a second setting signal to obtain the first setting signal, where the second setting signal is generated according to the setting of a mode register, and the second setting signal includes: when the second setting signal is at a fifth level, it represents that the ODT function of the chip is turned off; when the second setting signal is at a sixth level, it represents that the ODT function of the chip is turned on.

6. The enabling control circuit according to claim 5, wherein The fifth level is a high level, and the sixth level is a low level.

7. The enabling control circuit according to claim 5, wherein The control module further includes a three-input OR gate; where The three-input OR gate is configured to perform an OR operation on the second setting signal, the first intermediate signal, and the second intermediate signal to generate a count reset signal.

8. The enabling control circuit according to claim 7, wherein The counting module includes an asynchronous binary counter, and the asynchronous binary counter includes a plurality of second flip-flops that are sequentially connected.

9. The enabling control circuit according to claim 8, characterized in that, The second flip-flop is a D-type flip-flop; where the input terminal (D) of each second flip-flop is connected to its own second output terminal (Q bar), and the second output terminal (Q bar) of each second flip-flop is connected to the clock terminal (CK) of the next second flip-flop.

10. The enabling control circuit according to claim 9, characterized in that, The second flip-flop further includes a first output terminal (Q) and a reset terminal (RST); where The first output terminal of the second flip-flop is configured to output a count signal; The reset terminal of the second flip-flop is configured to receive the count reset signal, and when the count reset signal is at a high level, reset the second flip-flop to control the count signal to be at a low level.

11. The enabling control circuit according to claim 10, wherein The counting module further includes a clock control module, where The clock control module is configured to receive the count reset signal and a clock signal to generate an internal clock signal; where the internal clock signal is connected to the clock terminal (CK) of the first second flip-flop among the plurality of second flip-flops, and the internal clock signal includes: when the count reset signal is at a seventh level, stop outputting the internal clock signal; and when the count reset signal is at an eighth level, output the internal clock signal.

12. The enabling control circuit according to claim 11, wherein The seventh level is a high level, and the eighth level is a low level.

13. The enabling control circuit according to claim 11, wherein The clock control module includes a second NOT gate module and a two-input AND gate; where The second NOT gate module is configured to receive the count reset signal and perform a NOT operation on the count reset signal to obtain a third intermediate signal; The two-input AND gate is configured to receive the third intermediate signal and the clock signal and perform an AND operation on the third intermediate signal and the clock signal to obtain the internal clock signal.

14. The enable control circuit according to claim 5, wherein The selection module is further configured to receive the first setting signal and at least two characterization signals, and select one of the at least two characterization signals as the target achievement signal according to the first setting signal; wherein, the at least two characterization signals respectively characterize that the clock cycle count value reaches different clock cycle count target values.

15. The enable control circuit according to claim 14, wherein the selection module is specifically configured to, when the first setting signal indicates that neither the additional delay AL nor the parity delay PL is enabled, select the first characterization signal as the target achievement signal and determine the clock cycle count target value as a first value; wherein, the first value is a value greater than or equal to the column address write latency CWL minus 2; or the selection module is specifically configured to, when the first setting signal indicates that both the additional delay AL and the parity delay PL are enabled, select the second characterization signal as the target achievement signal and determine the clock cycle count target value as a second value; wherein, the second value is a value greater than or equal to the sum of the column address write latency CWL, the additional delay AL, and the parity delay PL minus 2; or the selection module is specifically configured to, when the first setting signal indicates that the additional delay AL is enabled and the parity delay PL is not enabled, select the third characterization signal as the target achievement signal and determine the clock cycle count target value as a third value; wherein, the third value is a value greater than or equal to the sum of the column address write latency CWL and the additional delay AL minus 2; or the selection module is specifically configured to, when the first setting signal indicates that the parity delay PL is enabled and the additional delay AL is not enabled, select the fourth characterization signal as the target achievement signal and determine the clock cycle count target value as a fourth value; wherein, the fourth value is a value greater than or equal to the sum of the column address write latency CWL and the parity delay PL minus 2; wherein, the first characterization signal characterizes that the clock cycle count value reaches the first value, the second characterization signal characterizes that the clock cycle count value reaches the second value, the third characterization signal characterizes that the clock cycle count value reaches the third value, and the fourth characterization signal characterizes that the clock cycle count value reaches the fourth value.

16. The enabling control circuit according to claim 15, characterized in that, The counting module includes six second flip-flops, and the six second flip-flops are connected in sequence; wherein the first output terminal of the i-th second flip-flop is configured to output the i-th counting signal, where i is an integer greater than zero and less than or equal to six; the selection module is specifically configured to receive the first setting signal, the fifth counting signal, and the sixth counting signal, and select between the fifth counting signal and the sixth counting signal according to the first setting signal to generate the target achievement signal; wherein, two input terminals of the selection module are respectively connected to the first output terminal of the fifth second flip-flop and the first output terminal of the sixth second flip-flop.

17. The enabling control circuit according to claim 16, wherein Wherein The selection module is further configured to, when the first setting signal indicates that both the additional delay AL and the parity delay PL are not enabled, determine the target achievement signal as the fifth counting signal and determine the clock cycle count target value as the first value; or, The selection module is further configured to, when the first setting signal indicates that at least one of the additional delay AL and the parity delay PL is enabled, determine the target achievement signal as the sixth counting signal and determine the clock cycle count target value as the second value.

18. The enabling control circuit according to claim 17, wherein The first value is 32, and the second value is 64.

19. A semiconductor memory, characterized in that, It includes the enabling control circuit according to any one of claims 1 to 18.

20. The semiconductor memory according to claim 19, wherein, The semiconductor memory is a dynamic random access memory DRAM chip.

21. The semiconductor memory according to claim 20, wherein, The dynamic random access memory DRAM chip complies with the DDR4 memory specification.

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