A wide-band clock generator based on real-time fractional frequency division

Abstract

The present invention discloses a wide-band clock generator based on real-time fractional frequency division, comprising a frequency division control word input terminal, a reference clock input terminal, a carrier signal output terminal, a frequency division and phase selection generator, a vector fractional phase detector, a low-pass filter, a multi-phase voltage-controlled oscillator, a frequency extension module, a multi-mode frequency divider and a dual-phase generator. The generator can effectively suppress the phase noise generated by fractional frequency division.

Description

Technical Field

[0001] The invention belongs to the field of electronic technology and relates to a wide-band clock generator based on real-time fractional frequency division. Background Art

[0002] Clock generators are a key functional module in RF / microwave wireless communication systems, widely used to generate carrier and clock signals. Today's clock generators are primarily implemented using a phase-locked loop (PLL) structure, due to its advantages such as excellent frequency tracking, low phase noise, minimal spurious components, and high system stability.

[0003] Compared to traditional integer-N phase-locked loops (PLLs), fractional-N phase-locked loops (FPLs) overcome the traditional PLL constraint that the output signal frequency must be an integer multiple of the input reference signal frequency. This allows clock generators based on FPLs to achieve high frequency modulation accuracy and fast response speed, while also providing improved suppression of oscillator noise. They are the mainstream architecture for frequency synthesizers in today's high-performance RF / microwave wireless communication systems. However, FPLs introduce additional quantization noise, which degrades the overall noise characteristics of the frequency synthesizer and limits its application. Therefore, quantization noise suppression is necessary. Over the past two decades, extensive research has focused on reducing quantization noise without compromising loop bandwidth. Various techniques have been proposed, including current digital-to-analog converter (DAC) feedforward compensation, direct compensation of digital-to-time converters (DTCs), phase interpolation, and filtering using finite impulse response (FIR) filters. However, among these technologies, the methods implemented using analog circuits are usually sensitive to the negative impacts of process, voltage, and temperature fluctuations, and require additional background calibration circuits to improve the efficiency of suppressing quantization noise, but with high power consumption and hardware overhead. The FIR filter technology with higher digital technology can only attenuate high-frequency quantization noise, and does not process low-frequency quantization noise within the loop bandwidth, so the suppression effect is limited. Summary of the Invention

[0004] The object of the present invention is to overcome the above-mentioned shortcomings of the prior art and provide a wide-band clock generator based on real-time fractional frequency division, which can effectively suppress the phase noise generated by fractional frequency division.

[0005] To achieve the above-mentioned object, the wide-band clock generator based on real-time fractional frequency division described in the present invention comprises a frequency division control word input terminal, a reference clock input terminal, a carrier signal output terminal, a frequency division and phase selection generator, a vector fractional phase detector, a low-pass filter, a multi-phase voltage-controlled oscillator, a frequency extension module, a multi-mode frequency divider and a dual-phase generator;

[0006] A first input terminal of the vector fractional phase detector is connected to a reference clock input terminal, an output terminal of the vector fractional phase detector is connected to an input terminal of a low-pass filter, an output terminal of the low-pass filter is connected to an input terminal of a multi-phase voltage-controlled oscillator, a first component output terminal of a vector output of the multi-phase voltage-controlled oscillator is connected to a first differential signal input terminal of a frequency extension module and a single-phase clock input terminal of a multi-mode frequency divider, a fifth component output terminal of a vector output of the multi-phase voltage-controlled oscillator is connected to a second differential signal input terminal of the frequency extension module, and a vector output terminal of the multi-phase voltage-controlled oscillator is connected to a multi-phase clock input terminal of a dual-phase generator The output end of the multi-mode frequency divider is connected to the single-phase clock input end of the dual-phase generator, the first output end and the second output end of the dual-phase generator are respectively connected to the second input end and the third input end of the vector fractional phase detector, the input end of the frequency division and phase selection generator is connected to the frequency division control word input end, the vector output end of the frequency division and phase selection generator is connected to the vector control end of the vector fractional phase detector, the first scalar output end of the frequency division and phase selection generator is connected to the scalar control end of the multi-mode frequency divider, and the second scalar output end of the frequency division and phase selection generator is connected to the scalar control end of the dual-phase generator.

[0007] The vector fractional phase detector includes a reference clock input terminal, a current output terminal, a first single-phase clock input terminal, a second single-phase clock input terminal, a first phase frequency detector, a second phase frequency detector and a vector charge pump;

[0008] The reference clock input terminal is connected to the first input terminal of the first phase and frequency detector and the first input terminal of the second phase and frequency detector, the first single-phase clock input terminal is connected to the second input terminal of the first phase and frequency detector, and the second single-phase clock input terminal is connected to the second input terminal of the second phase and frequency detector;

[0009] The vector control end, the output end of the first phase frequency detector and the output end of the second phase frequency detector are connected to the vector charge pump.

[0010] The vector charge pump includes a plurality of units, wherein each unit includes a first multiplexer, a second multiplexer, a first current source, a second current source, a first switch, and a second switch;

[0011] A first output end of the first phase frequency detector is connected to a first input end of a first multiplexer in each unit, a second output end of the first phase frequency detector is connected to a first input end of a second multiplexer in each unit, a first output end of the second phase frequency detector is connected to a second input end of the first multiplexer in each unit, a second output end of the second phase frequency detector is connected to a second input end of the second multiplexer in each unit, one end of a first current source in each unit is connected to one end of a first switch, the other end of the first current source is connected to a power supply, one end of a second current source in each unit is connected to one end of a second switch, the other end of the second current source is connected to a power ground, the other end of the first switch is connected to the other end of the second switch and the current output end, the output end of the first multiplexer is connected to a control end of the first switch, and the output end of the second multiplexer is connected to the control end of the second switch;

[0012] The vector control terminal includes several sub-input terminals, wherein one sub-input terminal corresponds to one unit, and each sub-input terminal is connected to the control terminal of the first multiplexer and the control terminal of the second multiplexer in the corresponding unit.

[0013] The dual-phase generator includes a single-phase clock input terminal, a phase selection control word input terminal, a first single-phase clock output terminal and a second single-phase clock output terminal, a multi-phase clock input terminal and a multiplexer;

[0014] The output end of the multi-mode frequency divider is connected to the input end of the multi-phase clock input end via the single-phase clock input end, the output end of the multi-phase clock input end and the phase selection control word input end are connected to the multiplexer, and the first single-phase clock output end and the second single-phase clock output end of the multiplexer serve as the phase detection signal output end of the dual-phase generator.

[0015] The multi-phase clock input terminal includes a multi-phase clock input terminal, a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, an eighth D flip-flop and a ninth D flip-flop;

[0016] The output end of the multi-mode frequency divider is connected to the data input end of the first D flip-flop via the single-phase clock input end, the first component end of the multi-phase clock input end is connected to the clock input end of the first D flip-flop, the output end of the first D flip-flop is connected to the signal input end of the second D flip-flop and the second data input end of the multiplexer, the second component end of the multi-phase clock input end is connected to the clock input end of the second D flip-flop, the output end of the second D flip-flop is connected to the data input end of the third D flip-flop and the third data input end of the multiplexer, the third component end of the multi-phase clock input end is connected to the clock input end of the third D flip-flop, the output end of the third D flip-flop is connected to the data input end of the fourth D flip-flop and the fourth data input end of the multiplexer, the fourth component end of the multi-phase clock input end is connected to the clock input end of the fourth D flip-flop, the output end of the fourth D flip-flop is connected to the data input end of the fifth D flip-flop and the fifth data input end of the multiplexer, and the fifth component end of the multi-phase clock input end is connected to the clock input end of the fourth D flip-flop. The first component terminal of the multi-phase clock input terminal is connected to the clock input terminal of the sixth D flip-flop, the output terminal of the sixth D flip-flop is connected to the data input terminal of the seventh D flip-flop and the seventh data input terminal of the multiplexer, the seventh component terminal of the multi-phase clock input terminal is connected to the clock input terminal of the seventh D flip-flop, the output terminal of the seventh D flip-flop is connected to the data input terminal of the eighth D flip-flop and the eighth data input terminal of the multiplexer, the eighth component terminal of the multi-phase clock input terminal is connected to the clock input terminal of the eighth D flip-flop, the output terminal of the eighth D flip-flop is connected to the data input terminal of the ninth D flip-flop and the ninth data input terminal of the multiplexer, the first component terminal of the multi-phase clock input terminal is connected to the clock input terminal of the eighth D flip-flop, and the output terminal of the ninth D flip-flop is connected to the tenth data input terminal of the multiplexer.

[0017] The frequency division and phase selection generator includes a frequency division control word input terminal, a fractional Δ∑ modulator, an accumulator, a dynamic element matching module, a first adder and a second adder module;

[0018] The frequency division control word input terminal is a 25-bit wide digital input terminal, which is connected to the input terminal of the fractional Δ∑ modulator. The upper 5-bit integer control word output terminal of the 16-bit wide output terminal of the fractional Δ∑ modulator is connected to the 5-bit wide input terminal of the first adder. There are lower 11-bit fractional control word output terminals in the 16-bit wide output terminal of the fractional Δ∑ modulator, among which the lower 8-bit fractional control word output terminals are connected to the input terminal of the dynamic element matching module. In addition, the lower 3-bit fractional control word output terminals are connected to the input terminal of the accumulator module. The vector output terminal of the dynamic element matching module serves as the frequency division and phase selection generator. Vector output end, wherein the vector output end is a 256-unit vector output end, the 1-bit wide output end of the dynamic element matching module is connected to the 1-bit wide input end of the second adder, the output end of the accumulator is connected to the 4-bit wide input end of the second adder, the highest bit of the 4-bit wide output end of the second adder is connected to the one-bit wide input end of the first adder, and the 5-bit wide output end of the first adder serves as the scalar control end of the multi-mode divider, wherein the scalar control end is a 5-bit wide output digital output end, and the lower 3 bits of the 4-bit wide output end of the second adder are connected to the scalar control end of the dual-phase generator as a 3-bit wide digital output end.

[0019] The frequency extension module includes a first differential signal input terminal, a second differential signal input terminal, a first carrier signal output terminal, a second carrier signal output terminal, a third carrier signal output terminal, a fourth carrier signal output terminal, a first frequency multiplier, a second frequency multiplier, a programmable frequency divider module, a first buffer, a second buffer, a third buffer and a fourth buffer;

[0020] The first component output terminal and the fifth component output terminal of the multi-phase voltage-controlled oscillator are both connected to the differential signal input terminal of the first frequency multiplier, the differential signal input terminal of the third buffer and the differential signal input terminal of the programmable frequency divider module, the differential signal output terminal of the first frequency multiplier is connected to the differential signal input terminal of the second frequency multiplier and the differential signal input terminal of the second buffer, the differential signal output terminal of the second frequency multiplier is connected to the differential signal input terminal of the first buffer, the output terminal of the first buffer is connected to the first carrier signal output terminal, the output terminal of the second buffer is connected to the second carrier signal output terminal, the output terminal of the third buffer is connected to the third carrier signal output terminal, the output terminal of the programmable frequency divider module is connected to the input terminal of the fourth buffer, and the output terminal of the fourth buffer is connected to the fourth carrier signal output terminal.

[0021] The present invention has the following beneficial effects:

[0022] The wide-band clock generator based on real-time fractional frequency division described in the present invention adopts multi-phase oscillator technology in specific operation. While having the advantages of low phase noise in the time-space mean fractional frequency phase-locked loop technology, it overcomes the problem of channel mismatch. This allows the present invention to reduce the number of channels in the array, reduce the additional power consumption and hardware overhead generated by the loop, reduce the additional noise introduced by the frequency-locked loop, and reduce potential system stability risks under the premise of maintaining the same quantization noise suppression effect. In addition, the present invention adopts the time-space mean technology based on the multi-phase oscillator to achieve real-time fractional frequency division, overcome the problem of quantization noise in traditional fractional frequency phase-locked loops deteriorating the noise characteristics of the frequency synthesizer, and solve the problem of limitations in existing fractional frequency phase-locked loop quantization noise suppression technology. This allows the present invention to achieve 66dB of quantization noise suppression within the full frequency band, giving the loop the advantages of low phase noise and low power consumption. It should also be noted that the frequency division and phase selection generators in this invention are implemented using digital circuits, making them highly immune to errors caused by process, voltage, and temperature fluctuations. Furthermore, they offer excellent process reconfigurability and facilitate automated design. With the continuous advancement of integrated circuit manufacturing processes, power consumption and hardware overhead can be further reduced. Simulation experiments have shown that the frequency extension module of this invention enables the output signal to cover a wide frequency range of 0.05 GHz to 48 GHz, achieving a high frequency coverage. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural schematic diagram of the present invention;

[0024] Figure 2 Schematic diagram of the vector fractional phase detector in the present invention;

[0025] Figure 3 is a schematic diagram of the dual-phase sound generator of the present invention;

[0026] Figure 4 Schematic diagram of the frequency division and phase selection generator in the present invention;

[0027] Figure 5 This is a schematic diagram of the frequency extension module of the present invention;

[0028] Figure 6 It is a structural block diagram of the multi-mode frequency divider in the present invention;

[0029] Figure 7 This is a schematic diagram of the 2 / 3 frequency divider in the present invention;

[0030] Figure 8 This is a schematic diagram of the frequency and phase detector in the present invention. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only embodiments of a part of the present invention, not all embodiments, and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts disclosed in the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.

[0032] The accompanying drawings illustrate schematic diagrams of the structures of the disclosed embodiments of the present invention. These figures are not drawn to scale; for the purpose of clarity, some details are exaggerated and some details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0033] refer to Figure 1 The wide-band clock generator based on real-time fractional frequency division of the present invention comprises a frequency division control word input terminal, a reference clock input terminal, a carrier signal output terminal, a frequency division and phase selection generator, a vector fractional phase detector, a low-pass filter, a multi-phase voltage-controlled oscillator, a frequency extension module, a multi-mode frequency divider and a dual-phase generator;

[0034] The first input terminal of the vector fractional phase detector is connected to the reference clock input terminal Φ REF The output of the vector fractional phase detector is connected to the input of the low-pass filter, the output of the low-pass filter is connected to the input of the multi-phase voltage-controlled oscillator, and the first component output terminal Φ of the multi-phase voltage-controlled oscillator vector output is connected. VCO,1 Connected to the first differential signal input terminal of the frequency extension module and the single-phase clock input terminal of the multi-mode frequency divider, the fifth component output terminal Φ of the multi-phase voltage-controlled oscillator vector output VCO,5 Connected to the second differential signal input terminal of the frequency extension module and the vector output terminal of the multi-phase voltage controlled oscillator Connected to the multi-phase clock input of the dual-phase generator, the output of the multi-mode divider Φ div Connected to the single-phase clock input terminal of the dual-phase generator, the first output terminal of the dual-phase generator Φ LEAD and the second output terminal Φ LAG The second and third input terminals of the vector fractional phase detector are connected respectively, the input terminal of the frequency division and phase selection generator is connected to the frequency division control word input terminal N+α, and the vector output terminal of the frequency division and phase selection generator is connected to the frequency division control word input terminal N+α. The first scalar output terminal of the frequency division and phase selection generator is connected to the scalar control terminal N of the multi-mode frequency divider. div The second scalar output terminal of the frequency division and phase selection generator is connected to the scalar control terminal N of the dual-phase generator. ps are connected.

[0035] refer to Figure 2 The vector fractional phase detector includes a reference clock input terminal Φ ref , current output terminal I CP , the first single-phase clock input terminal Φ LEAD , the second single-phase clock input terminal Φ LAG , a first phase frequency detector PFD1, a second phase frequency detector PFD2 and a vector charge pump;

[0036] Reference clock input Φ ref Connected to the first input terminal of the first phase frequency detector PFD1 and the first input terminal of the second phase frequency detector PFD2, the first single-phase clock input terminal Φ LEAD Connected to the second input terminal of the first phase frequency detector PFD1, the second single-phase clock input terminal Φ LAG Connected to the second input terminal of the second phase frequency detector PFD2; vector control terminal The output end of the first phase frequency detector PFD1 and the output end of the second phase frequency detector PFD2 are connected to the vector charge pump.

[0037] In addition, the vector charge pump includes several units, wherein each unit includes a first multiplexer MUX1, a second multiplexer MUX2, a first current source I1, a second current source I2, a first switch SW1 and a second switch SW2; a first output terminal UP of the first phase frequency detector PFD1 LEAD The first input terminal of the first multiplexer MUX1 in each unit is connected to the second output terminal DN of the first phase frequency detector PFD1. LEAD Connected to the first input terminal of the second multiplexer MUX2 in each unit, the first output terminal UP of the second phase frequency detector PFD2 LAG The second input terminal of the first multiplexer MUX1 in each unit is connected to the second output terminal DN of the second phase frequency detector PFD2. LAG The first input terminal of the second multiplexer MUX2 in each unit is connected, one end of the first current source I1 in each unit is connected to one end of the first switch SW1, and the other end of the first current source I1 is connected to the power supply. The second current source I2 in each unit is connected to one end of the second switch SW2, and the other end of the second current source I2 is connected to the power ground. The other end of the first switch SW1 is connected to the other end of the second switch SW2 and the current output terminal ICP The output end of the first multiplexer MUX1 is connected to the control end of the first switch SW1, and the output end of the second multiplexer MUX2 is connected to the control end of the second switch SW2; the vector control end It includes several sub-input terminals, wherein one sub-input terminal corresponds to one unit, and each sub-input terminal is connected to the control terminal of the first multiplexer MUX1 and the control terminal of the second multiplexer MUX2 in the corresponding unit.

[0038] When the vector fractional phase detector is working, the first single-phase clock input terminal Φ LEAD With the second single-phase clock input terminal Φ LAG They are connected to the first phase frequency detector PFD1 and the second phase frequency detector PFD2 respectively to generate two sets of phase difference pulse signals UP LEAD DN LEAD and UP LAG DN LAG . Vector control terminal Each element in the output vector signal controls the first multiplexer MUX1 and the second multiplexer MUX2 in the corresponding unit to output UP LEAD and DN LEAD or UP LAG and DN LAG , and then the first current source I1 and the second current source I2 are controlled by the signals output by the first multiplexer MUX1 and the second multiplexer MUX2, and Φ LEAD and Φ ref or Φ LAG and Φ ref The phase difference between them is converted into charge and output to the current output terminal I CP .

[0039] refer to Figure 3 The dual-phase generator includes a single-phase clock input terminal Φ div , Phase selection control word input terminal N PS , the first single-phase clock output terminal Φ LEAD And the second single-phase clock output terminal Φ LAG , multi-phase clock input terminal and multiplexer MUX3; the output terminal of the multi-mode divider is connected to the single-phase clock input terminal Φ div Connected to the input terminal of the multi-phase clock input terminal, the output terminal of the multi-phase clock input terminal and the phase control word input terminal N PS Connected to the multiplexer MUX3, the first single-phase clock output terminal Φ of the multiplexer MUX3 LEAD And the second single-phase clock output terminal Φ LAG Serves as the phase-locked signal output end of the dual-phase generator.

[0040] Wherein, the multi-phase clock input terminal includes a multi-phase clock input terminal a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, a fourth D flip-flop DFF4, a fifth D flip-flop DFF5, a sixth D flip-flop DFF6, a seventh D flip-flop DFF7, an eighth D flip-flop DFF8, and a ninth D flip-flop DFF9;

[0041] The output of the multi-mode frequency divider is connected to the single-phase clock input terminal Φ div Connected to the data input terminal of the first D flip-flop DFF1, the multi-phase clock input terminal The first component end Φ VCO，1 The output terminal of the first D flip-flop DFF1 is connected to the signal input terminal of the second D flip-flop DFF2 and the second data input terminal of the multiplexer MUX3. The second component end Φ VCO，2 The output terminal of the second D flip-flop DFF2 is connected to the data input terminal of the third D flip-flop DFF3 and the third data input terminal of the multiplexer MUX3. The multi-phase clock input terminal The third component end Φ VCO，3 The output terminal of the third D flip-flop DFF3 is connected to the data input terminal of the fourth D flip-flop DFF4 and the fourth data input terminal of the multiplexer MUX3. The multi-phase clock input terminal The fourth component end Φ VCO，4 The output terminal of the fourth D flip-flop DFF4 is connected to the data input terminal of the fifth D flip-flop DFF5 and the fifth data input terminal of the multiplexer MUX3. The multi-phase clock input terminal The fifth component end Φ VCO，5 The output terminal of the fifth D flip-flop DFF5 is connected to the data input terminal of the sixth D flip-flop DFF6 and the sixth data input terminal of the multiplexer MUX3. The multi-phase clock input terminal The sixth component end Φ VCO，6 The output terminal of the sixth D flip-flop DFF6 is connected to the data input terminal of the seventh D flip-flop DFF7 and the seventh data input terminal of the multiplexer MUX3. The multi-phase clock input terminal The seventh component end Φ VCO，7The output terminal of the seventh D flip-flop DFF7 is connected to the data input terminal of the eighth D flip-flop DFF8 and the eighth data input terminal of the multiplexer MUX3. The multi-phase clock input terminal The eighth component end Φ VCO，8 The output terminal of the eighth D flip-flop DFF8 is connected to the data input terminal of the ninth D flip-flop DFF9 and the ninth data input terminal of the multiplexer MUX3. The multi-phase clock input terminal The first component end Φ VCO，1 The output terminal of the ninth D flip-flop DFF9 is connected to the tenth data input terminal of the multiplexer MUX3.

[0042] It should be noted that the dual-phase generator generates eight sets of signals through the first D flip-flop DFF1, the second D flip-flop DFF2, the third D flip-flop DFF3, the fourth D flip-flop DFF4, the fifth D flip-flop DFF5, the sixth D flip-flop DFF6, the seventh D flip-flop DFF7, the eighth D flip-flop DFF8 and the ninth D flip-flop DFF9, which are controlled by the phase selection control word input terminal N PS Control the multiplexer MUX3 to select a group of adjacent phase signals Φ LEAD and Φ LAG .

[0043] refer to Figure 4 , the frequency division and phase selection generator includes a frequency division control word input terminal N+α, a fractional Δ∑ modulator, an accumulator ACC1, a dynamic element matching module, a first adder ADD1 and a second adder ADD2;

[0044] The frequency division control word input terminal N+α is a 25-bit wide digital input terminal, which is connected to the input terminal of the fractional Δ∑ modulator. The high 5-bit integer control word output terminal d inte The 5-bit wide input terminal of the first adder ADD1 is connected to the 16-bit wide output terminal of the fractional ΔΣ modulator. The lower 11-bit fractional control word output terminal exists in the 16-bit wide output terminal of the fractional ΔΣ modulator. Among them, the lower 8-bit fractional control word output terminal d frac，LSB Connected to the input of the dynamic element matching module. In addition, the lower 3 decimal control word output terminal d frac，MSB Connected to the input of the accumulator ACC1 module, the vector output of the dynamic element matching module is used as the vector output of the frequency division and phase selection generator Wherein, the vector output terminal 256-unit vector output terminal, 1-bit wide output terminal N of the dynamic element matching module refThe 1-bit wide input terminal of the second adder ADD2 is connected to the 1-bit wide input terminal of the second adder ADD2, the output terminal of the accumulator ACC1 is connected to the 4-bit wide input terminal of the second adder ADD2, the highest bit of the 4-bit wide output terminal of the second adder ADD2 is connected to the 1-bit wide input terminal of the first adder ADD1, and the 5-bit wide output terminal of the first adder ADD1 serves as the scalar control terminal N of the multi-mode frequency divider. div , where the scalar control terminal N div The lower 3 bits of the 4-bit output terminal of the second adder ADD2 are used as the 3-bit digital output terminal and the scalar control terminal N of the dual-phase generator. ps are connected.

[0045] It should be noted that the lower 8-bit fractional control word d in the 11-bit fractional control word output by the fractional Δ∑ modulator is frac，LSB The binary-thermometer code is converted into a 256-bit wide thermometer code by the dynamic element matching module, and then a 256-element vector control signal is generated. and 1-bit wide control signal N ref The upper three bits of the 11-bit fractional control word output by the fractional Δ∑ modulator are d frac，MSB The 4-bit width output of the fractional control word after passing through the accumulator ACC1 is combined with the control signal N ref The second adder ADD2 adds the 4-bit wide output, where the highest bit is equal to the 5-bit wide integer control word d output by the fractional Δ∑ modulator. inte The 5-bit wide control signal is obtained by the first adder ADD1 to control the multi-mode frequency divider to divide the oscillator output signal. The lower 3-bit control word output by the second adder ADD2 is used to control the multiplexer in the dual-phase generator to select the phase.

[0046] refer to Figure 5 The frequency extension module includes a first differential signal input terminal Φ VCO,1 , the second differential signal input terminal Φ VCO,5 , the first carrier signal output terminal Φ out1,mmW , the second carrier signal output terminal Φ out2,mmW , the third carrier signal output terminal Φ out3,RF , the fourth carrier signal output terminal Φ out4,RF+IF , a first frequency multiplier FM1, a second frequency multiplier FM2, a programmable frequency divider module, a first buffer BUF1, a second buffer BUF2, a third buffer BUF3 and a fourth buffer BUF4;

[0047] The first component output terminal Φ of the multi-phase voltage controlled oscillator VCO,1 And the fifth component output terminal Φ VCO,5The differential signal input terminals of the first frequency multiplier FM1, the differential signal input terminals of the third buffer BUF3 and the differential signal input terminals of the programmable frequency divider module are connected. The differential signal output terminals of the first frequency multiplier FM1 are connected to the differential signal input terminals of the second frequency multiplier FM2 and the differential signal input terminals of the second buffer BUF2. The differential signal output terminals of the second frequency multiplier FM2 are connected to the differential signal input terminals of the first buffer BUF1. The output terminals of the first buffer BUF1 are connected to the first carrier signal output terminals Φ out1,mmW The output terminal of the second buffer BUF2 is connected to the second carrier signal output terminal Φ out2,mmW The output terminal of the third buffer BUF3 is connected to the third carrier signal output terminal Φ out3,RF The output end of the programmable frequency divider module is connected to the input end of the fourth buffer BUF4, and the output end of the fourth buffer BUF4 is connected to the fourth carrier signal output end Φ out4,RF+IF are connected.

[0048] The output signal of the multi-phase voltage controlled oscillator is 8 signals with a phase difference of 45 degrees, and the output signal frequency range is 6GHz to 12GHz. VCO,1 and Φ VCO,5 After passing through the third buffer BUF3, the output signal frequency range is 6GHz~12GHz. VCO,1 and Φ VCO,5 After passing through the first frequency multiplier FM1 and the second buffer BUF2, the output signal frequency range is 12GHz to 24GHz. VCO,1 and Φ VCO,5 After passing through the first frequency multiplier FM1 and the second frequency multiplier FM2, it passes through the first buffer BUF1, and its output signal frequency range is 24GHz to 48GHz. VCO,1 and Φ VCO,5 After passing through the programmable frequency divider module and then the fourth buffer BUF4, the output signal frequency range is 0.05GHz to 6GHz, so the frequency coverage range of the carrier signal output end is 0.05GHz to 48GHz.

[0049] refer to Figure 6 The multi-mode frequency divider includes a first control terminal N div [0], the second control terminal N div [1] The third control terminal N div [2] The fourth control terminal N div [3] The fifth control terminal N div [4], Single-phase clock input terminal Φ VCO，1 , single-phase clock output terminal Φ div, the first divider by 2 / 3 frequency divider DIV1, the second divider by 2 / 3 frequency divider DIV2, the third divider by 2 / 3 frequency divider DIV3, the fourth divider by 2 / 3 frequency divider DIV4, the fifth divider by 2 / 3 frequency divider DIV5, the tenth D flip-flop DFF 10 , the eleventh D flip-flop DFF 11 , the twelfth D flip-flop DFF 12 , Thirteenth D flip-flop DFF 13 and the fourteenth D flip-flop DFF 14 ;

[0050] The first component output terminal Φ of the multi-phase voltage controlled oscillator vector output VCO,1 Connected to the first input terminal of the first 2 / 3 frequency divider DIV1, the tenth D flip-flop DFF 10 The output end of is connected to the second input end of the first divider DIV1, the first output end of the first divider DIV1 is connected to the first input end of the second divider DIV2, and the second output end of the first divider DIV1 is used as the output end of the multi-mode divider. div ;

[0051] Eleventh D flip-flop DFF 11 The output end of is connected to the second input end of the second divide-by-2 / 3 frequency divider DIV2, the first output end of the second divide-by-2 / 3 frequency divider DIV2 is connected to the first input end of the third divide-by-2 / 3 frequency divider DIV3, and the second output end of the second divide-by-2 / 3 frequency divider DIV2 is connected to the third input end of the first divide-by-2 / 3 frequency divider DIV1;

[0052] Twelfth D flip-flop DFF 12 The output end of is connected to the second input end of the third divide-by-2 / 3 frequency divider DIV3, the first output end of the third divide-by-2 / 3 frequency divider DIV3 is connected to the first input end of the fourth divide-by-2 / 3 frequency divider DIV4, and the second output end of the third divide-by-2 / 3 frequency divider DIV3 is connected to the third input end of the second divide-by-2 / 3 frequency divider DIV2;

[0053] Thirteenth D flip-flop DFF 13 The output end of is connected to the second input end of the fourth divide-by-2 / 3 frequency divider DIV4, the first output end of the fourth divide-by-2 / 3 frequency divider DIV4 is connected to the first input end of the fifth divide-by-2 / 3 frequency divider DIV5, and the second output end of the fourth divide-by-2 / 3 frequency divider DIV4 is connected to the third input end of the third divide-by-2 / 3 frequency divider DIV3;

[0054] Fourteenth D flip-flop DFF 14The output end of is connected to the second input end of the fifth divide-by-2 / 3 frequency divider DIV5, the third input end of the fifth divide-by-2 / 3 frequency divider DIV5 is connected to the high level signal end, the first output end of the fifth divide-by-2 / 3 frequency divider DIV5 is in an open circuit state, the second output end of the fifth divide-by-2 / 3 frequency divider DIV5 is connected to the third input end of the fourth divide-by-2 / 3 frequency divider DIV4 and the tenth D flip-flop DFF 10 , the eleventh D flip-flop DFF 11 , the twelfth D flip-flop DFF 12 , Thirteenth D flip-flop DFF 13 and the fourteenth D flip-flop DFF 14 The clock input of the tenth D flip-flop DFF is connected to 10 , the eleventh D flip-flop DFF 11 , the twelfth D flip-flop DFF 12 , Thirteenth D flip-flop DFF 13 and the fourteenth D flip-flop DFF 14 The data input terminals are respectively connected to the first control terminal N div [0], the second control terminal N div [1] The third control terminal N div [2] The fourth control terminal N div [3] The fifth control terminal N div [4] are connected.

[0055] By controlling the first control terminal N div [0], the second control terminal N div [1] The third control terminal N div [2] The fourth control terminal N div [3] and the fifth control terminal N div [4] is controlled to divide the high frequency signal output by the multi-phase voltage controlled oscillator to generate a single-phase clock signal for generating a dual-phase signal and a clock signal of the digital circuit of the present invention. The frequency division ratio of the multi-mode divider is the same as that of the first control terminal N div [0], the second control terminal N div [1] The third control terminal N div [2] The fourth control terminal N div [3] The fifth control terminal N div [4] The corresponding relationship of the output control signal is shown in the following formula.

[0056] N div =N div [0]*2 0 +N div [1]*2 1 +N div [2]*2 2 +N div [3]*23 +N div [4]*2 4 +2 5 .

[0057] refer to Figure 7 Each of the first divide-by-2 / 3 frequency divider DIV1, the second divide-by-2 / 3 frequency divider DIV2, the third divide-by-2 / 3 frequency divider DIV3, the fourth divide-by-2 / 3 frequency divider DIV4, and the fifth divide-by-2 / 3 frequency divider DIV5 includes a clock input terminal CKI, a first control input terminal MC, a second control input terminal MI, a clock output terminal CKO, a control output terminal MO, a low-level active D latch LN1, a high-level active D latch LH1, and a fifteenth D flip-flop DFF 15 , NOR gate NOR1, first AND gate AND1 and second AND gate AND2;

[0058] The clock input terminal CKI is connected to the enable terminal of the low-level active D latch LN1, the enable terminal of the high-level active D latch LH1 and the fifteenth D flip-flop DFF. 15 The output of the D latch LN1 with a low level is connected to the control output MO and one input of the first AND gate AND1. The other input of the first AND gate AND1 is connected to the first control input MC. The output of the first AND gate AND1 is connected to the data input of the D latch LH1 with a high level. The output of the D latch LH1 with a high level is connected to one input of the NOR gate NOR1. The output of the NOR gate NOR1 is connected to the fifteenth D flip-flop DFF. 15 The data input terminal of the fifteenth D flip-flop DFF is connected to 15 The output end of is connected to the clock output end CKO, the other input end of the NOR gate NOR1 and one input end of the second AND gate AND2, the other input end of the second AND gate AND2 is connected to the second control input end MI, and the output end of the second AND gate AND2 is connected to the data input end of the low-level active D latch LN1.

[0059] In each divide-by-2 / 3 frequency divider, the first control input terminal MC and the second control input terminal MI control each divide-by-2 / 3 frequency divider to switch between the divide-by-2 / 3 states. The corresponding relationship is shown in Table 1. At the same time, the control signal generated for controlling the working state of the previous stage divide-by-2 / 3 frequency divider is output through the control output terminal MO.

[0060] Table 1

[0061]

[0062] refer to Figure 8The first phase frequency detector PFD1 and the second phase frequency detector PFD2 each include a phase detection signal input terminal Φ[K], a first average voltage output terminal UP, a second average voltage output terminal DN, a second NOR gate NOR2, a third NOR gate NOR3, a fourth NOR gate NOR4, a fifth NOR gate NOR5, a sixth NOR gate NOR6, a seventh NOR gate NOR7, an eighth NOR gate NOR8, a ninth NOR gate NOR9, a third adder ADD3 and a programmable delay module;

[0063] Reference clock input Φ ref The first input terminal of the NOR gate is connected to an input terminal of the second NOR gate NOR2, the output terminal of the second NOR gate NOR2 is connected to an input terminal of the third NOR gate NOR3 and a fourth NOR gate NOR4, the output terminal of the third NOR gate NOR3 is connected to the other input terminal of the second NOR gate NOR2, an input terminal of the third adder ADD3 and the first average voltage output terminal UP, the output terminal of the fourth NOR gate NOR4 is connected to the other output terminal of the third NOR gate NOR3 and an input terminal of the fifth NOR gate NOR5, the other input terminal of the fifth NOR gate NOR5 is connected to the output terminal Reset of the programmable delay module, the output terminal of the fifth NOR gate NOR5 is connected to the other input terminal of the fourth NOR gate NOR4, the phase detection signal input terminal Φ[K] is connected to the sixth NOR gate NOR An input terminal of R6 is connected, an output terminal of the sixth NOR gate NOR6 is connected to an input terminal of the seventh NOR gate NOR7 and an input terminal of the eighth NOR gate NOR8, an output terminal of the seventh NOR gate NOR7 is connected to the other input terminal of the sixth NOR gate NOR6, the other input terminal of the third adder ADD3 and the second mean voltage output terminal DN, an output terminal of the eighth NOR gate NOR8 is connected to the other output terminal of the seventh NOR gate NOR7 and an input terminal of the ninth NOR gate NOR9, the other input terminal of the ninth NOR gate NOR9 is connected to the output terminal Reset of the programmable delay module, the output terminal of the ninth NOR gate NOR9 is connected to the other input terminal of the eighth NOR gate NOR8, and the output terminal of the third adder ADD3 is connected to the input terminal of the programmable delay module.

[0064] The second NOR gate NOR2, the third NOR gate NOR3, the fourth NOR gate NOR4, and the fifth NOR gate NOR5 constitute a latch, the sixth NOR gate NOR6, the seventh NOR gate NOR7, the eighth NOR gate NOR8, and the ninth NOR gate NOR9 constitute another latch, and a programmable delay module is added after the third adder ADD3 to increase the pulse width of the average voltage output signal to prevent the charge pump from entering the dead zone.

Claims

1. A wide-band clock generator based on real-time fractional frequency division, characterized in that: It includes a frequency division control word input terminal, a reference clock input terminal, a carrier signal output terminal, a frequency division and phase selection generator, a vector fractional phase detector, a low-pass filter, a multi-phase voltage-controlled oscillator, a frequency extension module, a multi-mode frequency divider and a dual-phase generator; The first input terminal of the vector fractional phase detector is connected to the reference clock input terminal (Φ REF ), the output of the vector fractional phase detector is connected to the input of the low-pass filter, the output of the low-pass filter is connected to the input of the multi-phase voltage-controlled oscillator, and the first component output terminal (Φ VCO,1 ) is connected to the first differential signal input terminal of the frequency extension module and the single-phase clock input terminal of the multi-mode frequency divider, and the fifth component output terminal (Φ VCO,5 ) is connected to the second differential signal input terminal of the frequency extension module, and the vector output terminal of the multi-phase voltage-controlled oscillator Connected to the multi-phase clock input of the dual-phase generator, the output of the multi-mode divider (Φ div ) is connected to the single-phase clock input terminal of the dual-phase generator, and the first output terminal of the dual-phase generator (Φ LEAD ) and the second output terminal (Φ LAG ) are connected to the second input terminal and the third input terminal of the vector fractional phase detector respectively, the input terminal of the frequency division and phase selection generator is connected to the frequency division control word input terminal (N+α), and the vector output terminal of the frequency division and phase selection generator is connected to the frequency division control word input terminal (N+α). The first scalar output terminal of the frequency division and phase selection generator is connected to the scalar control terminal (N div ) is connected to the second scalar output terminal of the frequency division and phase selection generator and the scalar control terminal (N ps ) are connected.

2. The wide-band clock generator based on real-time fractional frequency division according to claim 1, characterized in that: The vector fractional phase detector includes a reference clock input terminal (Φ ref )、current output terminal (I CP ), the first single-phase clock input terminal (Φ LEAD ), the second single-phase clock input terminal (Φ LAG ), a first phase frequency detector (PFD1), a second phase frequency detector (PFD2) and a vector charge pump; Reference clock input (Φ ref ) is connected to the first input terminal of the first phase frequency detector (PFD1) and the first input terminal of the second phase frequency detector (PFD2), and the first single-phase clock input terminal (Φ LEAD ) is connected to the second input terminal of the first phase frequency detector (PFD1), and the second single-phase clock input terminal (Φ LAG ) is connected to a second input terminal of a second phase frequency detector (PFD2); Vector control terminal The output end of the first phase frequency detector (PFD1) and the output end of the second phase frequency detector (PFD2) are connected to a vector charge pump.

3. The wide-band clock generator based on real-time fractional frequency division according to claim 2, characterized in that: The vector charge pump includes a plurality of units, wherein each unit includes a first multiplexer (MUX1), a second multiplexer (MUX2), a first current source (I1), a second current source (I2), a first switch (SW1) and a second switch (SW2); The first output terminal (UP) of the first phase frequency detector (PFD1) LEAD ) is connected to the first input terminal of the first multiplexer (MUX1) in each unit, and the second output terminal (DN LEAD ) is connected to the first input terminal of the second multiplexer (MUX2) in each unit, and the first output terminal (UP LAG ) is connected to the second input terminal of the first multiplexer (MUX1) in each unit, and the second output terminal (DN LAG ) is connected to the second input terminal of the second multiplexer (MUX2) in each unit, one end of the first current source (I1) in each unit is connected to one end of the first switch (SW1), the other end of the first current source (I1) is connected to the power supply, one end of the second current source (I2) in each unit is connected to one end of the second switch (SW2), the other end of the second current source (I2) is connected to the power ground, the other end of the first switch (SW1) is connected to the other end of the second switch (SW2) and the current output terminal (I CP ), the output end of the first multiplexer (MUX1) is connected to the control end of the first switch (SW1), and the output end of the second multiplexer (MUX2) is connected to the control end of the second switch (SW2); Vector control terminal It comprises several sub-input terminals, wherein one sub-input terminal corresponds to one unit, and each sub-input terminal is connected to the control terminal of the first multiplexer (MUX1) and the control terminal of the second multiplexer (MUX2) in the corresponding unit.

4. The wide-band clock generator based on real-time fractional frequency division according to claim 1, characterized in that: The dual-phase generator includes a single-phase clock input terminal (Φ div ), phase selection control word input terminal (N PS ), the first single-phase clock output terminal (Φ LEAD ) and the second single-phase clock output terminal (Φ LAG ), multi-phase clock input terminal and multiplexer (MUX3); The output of the multi-mode divider is connected to the single-phase clock input terminal (Φ div ) is connected to the input terminal of the multi-phase clock input terminal, the output terminal of the multi-phase clock input terminal and the phase selection control word input terminal (N PS ) is connected to the multiplexer (MUX3), the first single-phase clock output terminal (Φ LEAD ) and the second single-phase clock output terminal (Φ LAG ) as the phase-locked signal output terminal of the dual-phase generator.

5. The wide-band clock generator based on real-time fractional frequency division according to claim 4, characterized in that: The multi-phase clock input terminal includes a multi-phase clock input terminal a first D flip-flop (DFF1), a second D flip-flop (DFF2), a third D flip-flop (DFF3), a fourth D flip-flop (DFF4), a fifth D flip-flop (DFF5), a sixth D flip-flop (DFF6), a seventh D flip-flop (DFF7), an eighth D flip-flop (DFF8), and a ninth D flip-flop (DFF9); The output of the multi-mode divider is connected to the single-phase clock input terminal (Φ div ) is connected to the data input terminal of the first D flip-flop (DFF1), the multi-phase clock input terminal The first component end (Φ VCO，1 ) is connected to the clock input terminal of the first D flip-flop (DFF1), the output terminal of the first D flip-flop (DFF1) is connected to the signal input terminal of the second D flip-flop (DFF2) and the second data input terminal of the multiplexer (MUX3), and the multi-phase clock input terminal The second component end (Φ VCO，2 ) is connected to the clock input of the second D flip-flop (DFF2), the output of the second D flip-flop (DFF2) is connected to the data input of the third D flip-flop (DFF3) and the third data input of the multiplexer (MUX3), and the multi-phase clock input The third component end (Φ VCO，3 ) is connected to the clock input terminal of the third D flip-flop (DFF3), the output terminal of the third D flip-flop (DFF3) is connected to the data input terminal of the fourth D flip-flop (DFF4) and the fourth data input terminal of the multiplexer (MUX3), and the multi-phase clock input terminal The fourth component end (Φ VCO，4 ) is connected to the clock input terminal of the fourth D flip-flop (DFF4), the output terminal of the fourth D flip-flop (DFF4) is connected to the data input terminal of the fifth D flip-flop (DFF5) and the fifth data input terminal of the multiplexer (MUX3), and the multi-phase clock input terminal The fifth component end (Φ VCO，5 ) is connected to the clock input terminal of the fifth D flip-flop (DFF5), the output terminal of the fifth D flip-flop (DFF5) is connected to the data input terminal of the sixth D flip-flop (DFF6) and the sixth data input terminal of the multiplexer (MUX3), and the multi-phase clock input terminal The sixth component end (Φ VCO，6 ) is connected to the clock input terminal of the sixth D flip-flop (DFF6), the output terminal of the sixth D flip-flop (DFF6) is connected to the data input terminal of the seventh D flip-flop (DFF7) and the seventh data input terminal of the multiplexer (MUX3), and the multi-phase clock input terminal The seventh component end (Φ VCO，7 ) is connected to the clock input terminal of the seventh D flip-flop (DFF7), the output terminal of the seventh D flip-flop (DFF7) is connected to the data input terminal of the eighth D flip-flop (DFF8) and the eighth data input terminal of the multiplexer (MUX3), and the multi-phase clock input terminal The eighth component end (Φ VCO，8 ) is connected to the clock input terminal of the eighth D flip-flop (DFF8), the output terminal of the eighth D flip-flop (DFF8) is connected to the data input terminal of the ninth D flip-flop (DFF9) and the ninth data input terminal of the multiplexer (MUX3), and the multi-phase clock input terminal The first component end (Φ VCO，1 ) is connected to the clock input terminal of the eighth D flip-flop (DFF8), and the output terminal of the ninth D flip-flop (DFF9) is connected to the tenth data input terminal of the multiplexer (MUX3).

6. The wide-band clock generator based on real-time fractional frequency division according to claim 1, characterized in that: The frequency division and phase selection generator includes a frequency division control word input terminal (N+α), a fractional ΔΣ modulator, an accumulator (ACC1), a dynamic element matching module, a first adder (ADD1) and a second adder (ADD2) module; The frequency division control word input terminal (N+α) is connected to the input terminal of the fractional ΔΣ modulator, and the high 5-bit integer control word output terminal (d inte ) is connected to the 5-bit wide input terminal of the first adder (ADD1), and the 16-bit wide output terminal of the fractional ΔΣ modulator has the lower 11-bit fractional control word output terminal, wherein the lower 8-bit fractional control word output terminal (d frac，LSB ) is connected to the input of the dynamic element matching module. In addition, the lower 3-bit decimal control word output terminal (d frac，MSB ) is connected to the input of the accumulator (ACC1) module, and the vector output of the dynamic element matching module is used as the vector output of the frequency division and phase selection generator Wherein, the vector output terminal 256-unit vector output terminal, 1-bit wide output terminal of dynamic element matching module (N ref ) is connected to the 1-bit wide input terminal of the second adder (ADD2), the output terminal of the accumulator (ACC1) is connected to the 4-bit wide input terminal of the second adder (ADD2), the most significant bit of the 4-bit wide output terminal of the second adder (ADD2) is connected to the 1-bit wide input terminal of the first adder (ADD1), and the 5-bit wide output terminal of the first adder (ADD1) serves as the scalar control terminal (N div ), where the scalar control terminal (N div ) is a 5-bit wide output digital output terminal, and the lower 3 bits of the 4-bit wide output terminal of the second adder (ADD2) are used as a 3-bit wide digital output terminal and the scalar control terminal (N ps ) are connected.

7. The wide-band clock generator based on real-time fractional frequency division according to claim 1, characterized in that: The frequency division control word input terminal (N+α) is a 25-bit wide digital input terminal.

8. The wide-band clock generator based on real-time fractional frequency division according to claim 1, characterized in that: The frequency extension module includes a first differential signal input terminal (Φ VCO,1 ), the second differential signal input terminal (Φ VCO,5 )、the first carrier signal output terminal (Φ out1,mmW )、Second carrier signal output terminal (Φ out2,mmW )、The third carrier signal output terminal (Φ out3,RF )、the fourth carrier signal output terminal (Φ out4,RF+IF ), a first frequency multiplier (FM1), a second frequency multiplier (FM2), a programmable frequency divider module, a first buffer (BUF1), a second buffer (BUF2), a third buffer (BUF3) and a fourth buffer (BUF4); The first component output terminal of the multi-phase voltage controlled oscillator (Φ VCO,1 ) and the fifth component output terminal (Φ VCO,5 ) are connected to the differential signal input end of the first frequency multiplier (FM1), the differential signal input end of the third buffer (BUF3) and the differential signal input end of the programmable frequency divider module, the differential signal output end of the first frequency multiplier (FM1) is connected to the differential signal input end of the second frequency multiplier (FM2) and the differential signal input end of the second buffer (BUF2), the differential signal output end of the second frequency multiplier (FM2) is connected to the differential signal input end of the first buffer (BUF1), the output end of the first buffer (BUF1) is connected to the first carrier signal output end (Φ out1,mmW ), the output end of the second buffer (BUF2) is connected to the second carrier signal output end (Φ out2,mmW ), the output end of the third buffer (BUF3) is connected to the third carrier signal output end (Φ out3,RF ), the output end of the programmable frequency divider module is connected to the input end of the fourth buffer (BUF4), the output end of the fourth buffer (BUF4) is connected to the fourth carrier signal output end (Φ out4,RF+IF ) are connected.

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