FPGA-based cyclic modulation coding system and method for medium wave transmitter

Abstract

The present application discloses a medium wave transmitter cyclic modulation coding system and method based on FPGA, the system includes a plurality of FPGA chips electrically connected in sequence, each of the FPGA chips has a large cycle control module, a small cycle control module and a power amplifier control module. The system of the present application can be deployed in multiple FPGA chips or a single FPGA, and only a small amount of pin resources are needed for each FPGA, which reduces the cost of applying the 10KW all-solid-state medium wave transmitter cyclic modulation coding system based on FPGA to the cyclic modulation coding link of all-solid-state medium wave transmitters above 100KW; secondly, the data output delay of the system is 8 to 10 system clock cycles, and is not related to the number of power amplifier modules to be controlled by the system, thereby reducing the requirements for the system clock frequency.

Description

Technical Field

[0001] The present application relates to the field of digital circuit technology, and in particular to a medium wave transmitter cyclic modulation coding system and method based on FPGA. Background Art

[0002] With the rapid development of broadcasting, my country's medium wave broadcasting equipment is trending towards full solid-state digitalization. The original tube B-type board modulator is being phased out and replaced by full solid-state PDM and DAM medium wave broadcasting transmitters, especially DAM digital amplitude modulation technology will be widely used.

[0003] The cyclic modulation coding circuit is an important part of the DAM medium wave transmitter. The 12-bit data signal from the audio channel, that is, the binary audio code, is converted into an on / off control signal by the cyclic modulation coding circuit to perform the "on / off" operation on the RF module in the transmitter power amplifier stage.

[0004] The existing 10KW all-solid-state medium wave transmitter cyclic modulation coding system based on FPGA is deployed in an FPGA chip. The system needs to control 48 power amplifier modules, whose operating frequency is usually 80MHz~100MHz. The output delay of the system and the number of FPGA pins required are positively correlated with the number of power amplifier modules controlled. In the cyclic modulation coding link of the all-solid-state medium wave transmitter above 100KW, the cyclic modulation coding link needs to control 208 power amplifier modules. If the original 10KW all-solid-state medium wave transmitter cyclic modulation coding system is used, only the number of power amplifier modules controlled by the system is modified, and the original system is deployed in a single FPGA chip, this requires a single FPGA chip to have more than 400 available pin resources. The richer the pin resources of a single FPGA chip of the same level, the higher its price, which means higher cost; secondly, since the output delay of the original system is positively correlated with the number of power amplifier modules controlled, this will cause the output delay to increase to 3~4 times the original, and the corresponding system The required working clock frequency will also increase by 3~4 times. Moreover, due to the above defects, the original system's method of using shift registers to balance the utilization rate of power amplifier modules is no longer effective. Summary of the invention

[0005] The embodiment of the present application provides a cyclic modulation coding system and method for a medium wave transmitter based on FPGA, which is used to solve the problems in the prior art of applying a 10KW all-solid-state medium wave transmitter cyclic modulation coding system based on FPGA to the cyclic modulation coding link of an all-solid-state medium wave transmitter above 100KW, which has high cost, increased delay and increased requirements for the working clock.

[0006] On the one hand, the embodiment of the present application provides a medium wave transmitter cyclic modulation coding system based on FPGA, including a plurality of FPGA chips electrically connected in sequence, each FPGA chip having:

[0007] The large loop control module is used to determine the actual number of power amplifiers turned on for each FPGA chip according to the input binary audio code and the number of FPGA chips;

[0008] A small cycle control module is used to generate periodic pulses and count the pulses to obtain corresponding small cycle count values;

[0009] Amplifier control module, including:

[0010] The counting submodule 1 is used to accumulate the input power amplifier status codes to obtain the number of normal power amplifiers;

[0011] The correction amount calculation submodule is used to determine the corresponding correction amount according to the number of power amplifiers B that should be additionally turned off, the number of power amplifiers A that should be additionally turned on, and the number of power amplifiers that are turned on of the current FPGA chip input from other FPGA chips, and output the number of power amplifiers B0 that should be additionally turned off and the number of power amplifiers A0 that should be additionally turned on to other FPGA chips;

[0012] A first cyclic mapping submodule, used for performing multi-path selection on input cyclic shift data according to the small cyclic count value to obtain corresponding cyclic shift result data;

[0013] The elimination submodule 1 is used to perform code conversion on the cyclic shift result data, determine the number ND of power amplifiers to be turned off according to the number of normal power amplifiers and the correction amount, and perform multi-channel selection on the cyclic shift result data after code conversion according to the number of power amplifiers ND to obtain the corresponding output result;

[0014] The second cyclic mapping submodule is used to perform cyclic mapping on the output result to obtain a corresponding power amplifier control signal.

[0015] On the other hand, the embodiment of the present application provides a medium wave transmitter cyclic modulation coding method based on FPGA, including:

[0016] Determine the actual number of power amplifiers turned on for each FPGA chip according to the input binary audio code and the number of FPGA chips;

[0017] Generate periodic pulses and count the pulses to obtain corresponding small cycle count values;

[0018] Accumulate the input power amplifier status codes to obtain the number of normal power amplifiers;

[0019] Determine the corresponding correction amount according to the number B of power amplifiers that should be additionally turned off, the number A of power amplifiers that should be additionally turned on, and the number of power amplifiers that are turned on, which are input from other FPGA chips, and output the number B0 of power amplifiers that should be additionally turned off and the number A0 of power amplifiers that should be additionally turned on to other FPGA chips;

[0020] Performing multiple selection on the input cyclic shift data according to the small cyclic count value to obtain corresponding cyclic shift result data;

[0021] The cyclic shift result data is encoded and converted, the number of power amplifiers ND to be turned off is determined according to the number of normal power amplifiers and the correction amount, and the cyclic shift result data after the encoding conversion is multi-selected according to the number of power amplifiers ND to obtain the corresponding output result;

[0022] The output results are cyclically mapped to obtain the corresponding power amplifier control signal.

[0023] The FPGA-based medium wave transmitter cyclic modulation coding system and method in this application has the following advantages:

[0024] 1. It can be deployed in multiple FPGA chips or a single FPGA. Only 176 pin resources are needed for each FPGA. The total cost of multiple FPGA chips with fewer pins is lower than that of a single FPGA chip with the same number of pins.

[0025] 2. The data output delay is 8 to 10 system clock cycles, which is irrelevant to the number of power amplifier modules to be controlled by the system. Therefore, the required system clock frequency can be reduced to 5 to 10 MHz, which is conducive to communication between multiple FPGA chips.

[0026] 3. The ratio of the standard deviation of the utilization rate of each power amplifier module to the average utilization rate of the power amplifier module can be made less than 1‰, replacing the original method of using a circular shift register. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 A schematic diagram of the composition of a cyclic modulation and coding system for a medium wave transmitter based on FPGA provided in an embodiment of the present application;

[0029] Figure 2A structural block diagram of a single FPGA chip in a cyclic modulation coding system provided in an embodiment of the present application;

[0030] Figure 3 A structural block diagram of the calculation module 1 provided in an embodiment of the present application;

[0031] Figure 4 A structural block diagram of a cyclic mapping submodule provided in an embodiment of the present application;

[0032] Figure 5 A schematic diagram of the operation of the cyclic mapping submodule provided in an embodiment of the present application;

[0033] Figure 6 A structural block diagram of the elimination 1 submodule provided in an embodiment of the present application;

[0034] Figure 7 A state transition diagram of a cyclic coding modulation control state machine provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] Figure 1-7 The present invention provides a schematic diagram of the composition of a cyclic modulation and coding system for a medium wave transmitter based on FPGA. The present invention provides a cyclic modulation and coding system for a medium wave transmitter based on FPGA, including a plurality of FPGA chips electrically connected in sequence, each of which has:

[0037] The large loop control module is used to determine the actual number of power amplifiers turned on for each FPGA chip according to the input binary audio code and the number of FPGA chips;

[0038] A small cycle control module is used to generate periodic pulses and count the pulses to obtain corresponding small cycle count values;

[0039] Amplifier control module, including:

[0040] The counting submodule 1 is used to accumulate the input power amplifier status codes to obtain the number of normal power amplifiers;

[0041] The correction amount calculation submodule is used to determine the corresponding correction amount according to the number of power amplifiers B that should be additionally turned off, the number of power amplifiers A that should be additionally turned on, and the number of power amplifiers that are turned on of the current FPGA chip input from other FPGA chips, and output the number of power amplifiers B0 that should be additionally turned off and the number of power amplifiers A0 that should be additionally turned on to other FPGA chips;

[0042] A first cyclic mapping submodule, used for performing multi-path selection on input cyclic shift data according to the small cyclic count value to obtain corresponding cyclic shift result data;

[0043] The elimination submodule 1 is used to perform code conversion on the cyclic shift result data, determine the number ND of power amplifiers to be turned off according to the number of normal power amplifiers and the correction amount, and perform multi-channel selection on the cyclic shift result data after code conversion according to the number of power amplifiers ND to obtain the corresponding output result;

[0044] The second cyclic mapping submodule is used to perform cyclic mapping on the output result to obtain a corresponding power amplifier control signal.

[0045] For example, Figure 1 The system in the invention can be used for a 100KW all-solid-state medium wave transmitter. The system is composed of three FPGA chips, and the three FPGA chips are connected end to end with the signal lines "Number of amplifiers to be turned off BX" and "Number of amplifiers to be turned on AX". The 64-bit amplifier status code, 8-bit binary audio code, system clock Clk, and data clock are shared by the three FPGA chips. The FPGA chip model used can be EP1C6Q240C8N. After using the FPGA chip, the system clock is fixed to 10MHz. It is required to output the correct amplifier control signal according to the 8-bit binary audio code within a data clock cycle (500-800KHz), and avoid the amplifier control signal from driving the faulty amplifier module incorrectly; it is required to balance the utilization rate of each amplifier and balance the utilization rate of each amplifier as much as possible.

[0046] According to the above requirements, the system is deployed in three FPGA chips respectively, and the three FPGA chips are connected end to end with the signal lines of "number of amplifiers that should be turned off (6)" and "number of amplifiers that should be turned on (6)". The system clocks of the three FPGA chips are independent of each other but all 10MHz. The signals shared by the three FPGA chips are 64-bit amplifier status code, 8-bit binary audio code, and data clock. The A / D converter converts the analog audio signal into a 12-bit digital signal, and the FPGA chip extracts 8 bits as 8-bit binary audio code. At the same time, the sampling clock of the A / D converter is used as the data clock. Then, the 8-bit binary audio code and data clock are connected to the three FPGA chips through the wiring for processing. During the system test, any 1 to 10 of the 64-bit amplifier status pins are given a low level to simulate the amplifier failure. The system can avoid the faulty amplifier and always output the correct amplifier control signal. The power amplifier control signal was counted by external equipment. The results showed that with the increase of running time, the ratio of the standard deviation of the power amplifier module utilization rate to the average utilization rate gradually decreased. When the running time exceeded 10s, the above ratio was less than 1‰.

[0047] The above large cycle control module is used to balance the utilization rate of the power amplifier module of the all-solid-state medium wave transmitter above 100KW. The principle is to divide the 8-bit binary audio code by the number of FPGA chips used in the modulation and coding link, and the quotient is used as the actual number of power amplifiers turned on for each FPGA. The remainder is distributed to any FPGA chip. The actual number of power amplifiers turned on for each FPGA chip is, that is, Figure 2 The large circulation volume in Big.

[0048] The small cycle control module has a cycle control logic inside, which is composed of a counter and a pulse generation submodule. The pulse generation submodule generates a pulse signal with a length of one system clock cycle at a certain time interval, such as 1 to 5 seconds; after receiving the pulse signal, the counter accumulates 1 and uses the accumulated value as the small cycle count value; when accumulated to a certain value, such as 64, it is reset, such as reset to 0. The small cycle count value of the above counter is the small cycle amount L, which controls the switch cycle of the power amplifier control module in a single FPGA.

[0049] The power amplifier control module is used to implement the core functions of the system, and the block diagram of the calculation submodule is as follows Figure 3 In the figure, bit 0 to bit 63 are the input 64-bit amplifier status code, bit x is 0, indicating that the amplifier is faulty, bit x is 1, indicating that the amplifier is normal, and the 64 bits are accumulated bit by bit, and the accumulated result is the number of normal amplifiers.

[0050] The correction amount calculation submodule calculates the number of power amplifiers that should be turned off / on, i.e., the correction amount N, based on the number of power amplifiers B that should be turned off, the number of power amplifiers A that should be turned on, and the large cycle amount Big according to different device numbers, i.e., the numbers of each FPGA chip. Taking three FPGA chips, numbered 00, 01, and 10, as an example, the calculation logic of the correction amount calculation submodule is as follows:

[0051] For the FPGA chip with binary number 00:

[0052] If the binary audio code is less than 64, then:

[0053] N=D-B+A+Big

[0054] If D ≥ 64, then:

[0055] N=64-B+A+Big

[0056] For FPGA chip numbered 01:

[0057] If the binary audio code is less than 64, then:

[0058] N=0-B+A+Big

[0059] If 128>D≥64, then:

[0060] N=D-B+A+Big

[0061] If 128≤D, then:

[0062] N=64-B+A+Big

[0063] For FPGA chip number 10:

[0064] If the binary audio code is ≥128, then:

[0065] N=D-B+A+Big

[0066] If D < 128, then:

[0067] N=0-B+A+Big

[0068] The block diagram of the first loop mapping submodule is as follows Figure 4 As shown in FIG. 1 , the principle is to input all the input cyclic shift data into the multiplexer, and immediately output the cyclic shift result data according to the input cyclic coefficient, that is, the small cyclic count value, also called the small cyclic amount L. In order to distinguish it from the cyclic shift method of shifting one bit per cycle, this application refers to this process as cyclic mapping. The process of cyclic mapping can be referred to as Figure 5In the example shown, to ensure that the entire system meets the setup time requirement, a register should be added to the output of the first loop mapping submodule, so the entire module only consumes 1 system clock cycle.

[0069] The block diagram of the elimination module 1 is as follows Figure 6 As shown, the principle is based on the following formula, which changes the first 1 from the right of n to 0:

[0070] n=n&(n-1)

[0071] Based on the above formula, an adder and an AND gate array are used to form a 1 elimination subunit. According to the recursive idea, the subunit is cascaded, and the results of each level of subunits are output to the multiplexer, and the corresponding output result is selected according to the elimination amount, that is, the number of power amplifiers ND. The meaning of the result of the nth level subunit is that n 1 bits are changed to 0 from right to left, that is, the encoding conversion is completed.

[0072] The output result of the elimination submodule is actually also a 64-bit power amplifier status code, which is different from the above power amplifier status code. The second cyclic mapping submodule performs a cyclic mapping with a cyclic coefficient of 64 minus a small cyclic amount L on the output result to restore the original mapping relationship, and obtain the power amplifier control signal.

[0073] In the embodiment of the present application, the working process of each submodule in the power amplifier control module, that is, the control data of the state machine is as follows: Figure 7 As shown, the details are as follows:

[0074] S0, wait for start pulse.

[0075] S1. Use the correction amount calculation module to calculate the number of power amplifiers that should be turned off / on, i.e., the correction amount N, based on the number of power amplifiers B that should be turned off, the number of power amplifiers A that should be turned on, the large circulation amount Big, and the small circulation amount L of the machine according to different device numbers.

[0076] S2, map the low-order part with a width of small cycle amount L to the high-order part, so that after passing through the elimination module 1, the power amplifiers controlled by the original low-order part will not be in the off state for a long time, so as to achieve the effect of "circulation", and this process consumes 1 system clock cycle.

[0077] S3, since the input bit width of the multiplexer in the elimination 1 submodule is 64×64bit, this causes the combinational logic scale of the submodule to be too large, resulting in a register setup time violation. Therefore, the elimination 1 submodule is time-division multiplexed to reduce the scale of the combinational logic of the elimination 1 submodule, and the specific steps are as follows:

[0078] S3-1. Shift the number of power amplifiers to be turned off right by 1 bit (ie, divide by 2) and use it as the input of the above-mentioned elimination 1 submodule.

[0079] S3-2. Use the output of the elimination 1 submodule as the input of the elimination 1 submodule in S3-3.

[0080] S3-3, the input of the Elimination 1 submodule is the sum of the number of power amplifiers to be turned off, shifted right by 1 bit, and the number of power amplifiers to be turned off modulo 2. If the highest bit of the result of the calculation of the number of power amplifiers to be turned off minus 64 is 1 (that is, ND is less than 64), then the input of the Elimination 1 submodule becomes 0 at this time. If the highest bit of the result of the calculation of the number of power amplifiers to be turned off minus 64 is not 1, then the input of the Elimination 1 submodule is still the output of the S3-2 Elimination 1 submodule.

[0081] S3-4. Use the output of the elimination 1 submodule as the input of the second loop mapping submodule in S4.

[0082] S4. The 64-bit power amplifier status code after steps S2 and S3 is subjected to a cyclic mapping with a cyclic coefficient of 64 minus a small cyclic amount to restore the original mapping relationship.

[0083] S5. When the data clock is at a high level, the result of S4 is output through the latch.

[0084] In a possible embodiment, output ends of the first cyclic mapping submodule, the elimination submodule, and the second cyclic mapping submodule are respectively connected to registers.

[0085] Exemplarily, the register connected to the output end of the second loop mapping submodule is also connected to a latch, and the latch is used to latch and output the power amplifier control signal when the data clock is at a high level to ensure that the rate of the coded modulation is consistent with the data clock.

[0086] In a possible embodiment, the power amplifier control module further includes: a cyclic coding modulation control state machine, which is used to control the working states of the first cyclic mapping submodule, the elimination 1 submodule and the second cyclic mapping submodule under the control of the start pulse.

[0087] Exemplarily, the system further includes: a top-level module, which is used to buffer the power amplifier state code and the binary audio code through the first input buffer submodule and the second input buffer submodule, and then input them to the power amplifier control module and the large circulation module respectively. The first input buffer submodule and the second input buffer submodule both work under the control of the system clock.

[0088] The top-level module processes the high-order part of the external 12-bit data, namely the 8-bit binary audio code and the 64-bit amplifier status code, through the input buffer module driven by the system clock and outputs it to the subsequent modules to minimize the occurrence of metastable signals.

[0089] Furthermore, the top-level module also includes: a rising edge detection submodule, which is used to detect the rising edge of the data clock and generate a start pulse when the rising edge is detected. Through the rising edge detection submodule, the rising edge of the data clock signal can be synchronized with the 8-bit binary audio code. The rising edge detection submodule receives the data clock signal and outputs a start pulse with a length of one system clock cycle as a start signal for the cyclic coding modulation control state machine in the power amplifier control module.

[0090] The present application also provides a medium wave transmitter cyclic modulation coding method based on FPGA, including:

[0091] Determine the actual number of power amplifiers turned on for each FPGA chip according to the input binary audio code and the number of FPGA chips;

[0092] Generate periodic pulses and count the pulses to obtain corresponding small cycle count values;

[0093] Accumulate the input power amplifier status codes to obtain the number of normal power amplifiers;

[0094] Determine the corresponding correction amount according to the number B of power amplifiers that should be additionally turned off, the number A of power amplifiers that should be additionally turned on, and the number of power amplifiers that are turned on, which are input from other FPGA chips, and output the number B0 of power amplifiers that should be additionally turned off and the number A0 of power amplifiers that should be additionally turned on to other FPGA chips;

[0095] Performing multiple selection on the input cyclic shift data according to the small cyclic count value to obtain corresponding cyclic shift result data;

[0096] The cyclic shift result data is encoded and converted, the number of power amplifiers ND to be turned off is determined according to the number of normal power amplifiers and the correction amount, and the cyclic shift result data after the encoding conversion is multi-selected according to the number of power amplifiers ND to obtain the corresponding output result;

[0097] The output results are cyclically mapped to obtain the corresponding power amplifier control signal.

[0098] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0099] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. The cyclic modulation coding system of medium wave transmitter based on FPGA is characterized by: It includes a plurality of FPGA chips electrically connected in sequence, each of the FPGA chips having: A large loop control module is used to determine the actual number of power amplifiers turned on for each FPGA chip according to the input binary audio code and the number of FPGA chips; the large loop control module divides the binary audio code by the number of FPGA chips, and the quotient is used as the actual number of power amplifiers turned on for each FPGA chip, and the remainder is distributed to any FPGA chip; A small cycle control module is used to generate periodic pulses and count the pulses to obtain corresponding small cycle count values; Amplifier control module, including: The counting submodule 1 is used to accumulate the normal power amplifiers in the input power amplifier status code to obtain the number of normal power amplifiers; A correction amount calculation submodule, used to determine the corresponding correction amount according to the number B of power amplifiers that should be additionally turned off, the number A of power amplifiers that should be additionally turned on, and the number of power amplifiers that are turned on of the current FPGA chip input by other FPGA chips, and output the number B0 of power amplifiers that should be additionally turned off and the number A0 of power amplifiers that should be additionally turned on to other FPGA chips; A first cyclic mapping submodule, used for performing multi-path selection on input cyclic shift data according to the small cyclic count value to obtain corresponding cyclic shift result data; Elimination submodule 1, used for encoding and converting the cyclic shift result data, determining the number ND of power amplifiers to be shut down according to the number of normal power amplifiers and the correction amount, and performing multi-path selection on the cyclic shift result data after encoding and converting according to the number of power amplifiers ND to obtain a corresponding output result; The second cyclic mapping submodule is used to perform cyclic mapping on the output result to obtain a corresponding power amplifier control signal.

2. The FPGA-based medium wave transmitter cyclic modulation coding system according to claim 1, characterized in that: The output ends of the first loop mapping submodule, the elimination 1 submodule and the second loop mapping submodule are respectively connected to registers.

3. The FPGA-based medium wave transmitter cyclic modulation coding system according to claim 2, characterized in that: The register connected to the output end of the second cyclic mapping submodule is also connected to a latch, and the latch is used to latch and output the power amplifier control signal when the data clock is at a high level.

4. The FPGA-based medium wave transmitter cyclic modulation coding system according to claim 1, characterized in that: The power amplifier control module also includes: The cyclic coding modulation control state machine is used to control the working states of the first cyclic mapping submodule, the elimination 1 submodule and the second cyclic mapping submodule under the control of the start pulse.

5. The FPGA-based medium wave transmitter cyclic modulation coding system according to claim 4, characterized in that: Also includes: The top-level module is used to buffer the power amplifier status code and the binary audio code through the first input buffer submodule and the second input buffer submodule respectively, and then input them into the power amplifier control module and the large loop control module respectively.

6. The FPGA-based medium wave transmitter cyclic modulation coding system according to claim 5, characterized in that: The first input buffer submodule and the second input buffer submodule both operate under the control of a system clock.

7. The FPGA-based medium wave transmitter cyclic modulation coding system according to claim 5, characterized in that: The top-level module also includes: The rising edge detection submodule is used to detect the rising edge of the data clock and generate a start pulse when the rising edge is detected.

8. A medium wave transmitter cyclic modulation coding method based on FPGA, characterized in that: include: Determine the actual number of power amplifiers turned on for each FPGA chip according to the input binary audio code and the number of FPGA chips: divide the binary audio code by the number of FPGA chips, the quotient is the actual number of power amplifiers turned on for each FPGA chip, and the remainder is distributed to any FPGA chip; Generate periodic pulses and count the pulses to obtain corresponding small cycle count values; Accumulate the input power amplifier status codes to obtain the number of normal power amplifiers; Determine the corresponding correction amount according to the number B of power amplifiers that should be additionally turned off, the number A of power amplifiers that should be additionally turned on, and the number of power amplifiers that are turned on of the current FPGA chip input by the other FPGA chips, and output the number B0 of power amplifiers that should be additionally turned off and the number A0 of power amplifiers that should be additionally turned on to the other FPGA chips; Performing multi-path selection on the input cyclic shift data according to the small cyclic count value to obtain corresponding cyclic shift result data; Performing code conversion on the cyclic shift result data, determining the number ND of power amplifiers to be shut down according to the number of normal power amplifiers and the correction amount, and performing multi-path selection on the cyclic shift result data after code conversion according to the number of power amplifiers ND to obtain a corresponding output result; The output result is cyclically mapped to obtain a corresponding power amplifier control signal.

9. The FPGA-based medium wave transmitter cyclic modulation coding method according to claim 8, characterized in that: The generating of periodic pulses and counting the pulses to obtain corresponding small cycle count values ​​includes: Generate a pulse signal with a length of one system clock cycle at regular intervals; After receiving the pulse signal, accumulating 1 to obtain the small cycle count value; When the small cycle count value accumulates to a certain value, a reset process is performed.

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