A kind of olfactory memory calculator and preparation method

Abstract

The application discloses a kind of sense storage computing devices and preparation method, including forming first electrode and second electrode on substrate in parallel, and forming functional layer connected between first electrode and second electrode, functional layer is by the oxide nanowire of first electrode metal formed on the surface of first electrode and the oxide nanowire of second electrode metal formed on the surface of second electrode composition.The application can realize the sense storage computing integrated neural synapse device with the characteristics such as light, easy preparation by combining the memristor constructed based on the oxide nanowire of electrode metal and CMOS process material, has greater application prospect.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a sensor-memory computing device based on CMOS back-end technology and its fabrication method. Background Technology

[0002] With the continuous advancement of information technologies such as artificial intelligence and big data, there is a growing need for faster and more efficient computing systems to meet the demands of information technology development. However, the limitations of Moore's Law and the shortcomings of the von Neumann architecture have constrained the development of existing computer technology. Therefore, in-memory computing devices have become a new direction for the semiconductor industry. Memristors possess in-memory computing characteristics, offering faster speeds and lower energy consumption than traditional computers when handling the same amount of computational tasks.

[0003] Currently, various in-memory computing brain-inspired neural synaptic devices have been studied. To date, in-memory computing memristor functionality has been realized in various materials, including semiconductors, insulators, solid electrolytes, two-dimensional materials, and organic materials.

[0004] For resistive switching memristors, the functional layer is the carrier of resistive switching characteristics. The choice of the functional layer not only affects the manufacturing difficulty of the memristor, but also often determines the electrical characteristics of the memristor device.

[0005] Currently, most memristor-based in-memory computing devices under research are based on multilayer stacked MIM structures. Planar devices occupy a larger area compared to three-dimensional structures. Furthermore, in terms of material architecture, most materials are incompatible with traditional CMOS process materials, and introducing new materials into traditional integrated circuit processes requires very high R&D costs and technical difficulties.

[0006] With the miniaturization of transistors, current transistors have evolved from planar structures to three-dimensional stacking and fully encapsulated nanosheets and nanowires, making the research of nanowire-based devices increasingly important. Traditional transistor-based von Neumann computing architectures suffer from computational latency and memory wall problems due to the separation of computation and storage units. Therefore, the research of novel integrated sensing, memory, and computing devices based on nanowire functional layer structures is of great significance to the future development of integrated circuits. Summary of the Invention

[0007] The purpose of this invention is to overcome the above-mentioned defects in the prior art and to provide a sensing and storage device and its preparation method.

[0008] To achieve the above objectives, the technical solution of the present invention is as follows:

[0009] This invention provides a sensor-based computing device, comprising:

[0010] Substrate;

[0011] The first electrode and the second electrode are arranged side by side on the substrate;

[0012] A functional layer connecting the first electrode and the second electrode;

[0013] The functional layer is composed of oxide nanowires of a first electrode metal formed on the surface of the first electrode and oxide nanowires of a second electrode metal formed on the surface of the second electrode.

[0014] Furthermore, a first lower adhesion and barrier layer is provided between the substrate and the first electrode, and a second lower adhesion and barrier layer is provided between the substrate and the second electrode. The functional layer is suspended above the substrate between the first lower adhesion and barrier layer and the second lower adhesion and barrier layer.

[0015] Furthermore, a first upper adhesion and barrier layer is provided on the upper surface of the first electrode, a second upper adhesion and barrier layer is provided on the upper surface of the second electrode, and a dielectric layer covering the functional layer is provided between the first upper adhesion and barrier layer and the second upper adhesion and barrier layer.

[0016] Furthermore, the first electrode metal and the second electrode metal comprise copper, and the oxide nanowires of the first electrode metal and the oxide nanowires of the second electrode metal comprise copper oxide nanowires.

[0017] Furthermore, the dielectric layer material includes a low dielectric constant material.

[0018] The present invention also provides a method for fabricating an inductive computing device, comprising:

[0019] Provide substrate;

[0020] A first dielectric layer is formed on the substrate;

[0021] Two first trenches are formed on the first dielectric layer, extending to the surface of the substrate;

[0022] A lower adhesion and barrier layer is formed on the substrate surface exposed at the bottom of each of the first trenches;

[0023] An electrode is formed in each of the first trenches on each of the lower adhesion and barrier layers;

[0024] Remove the first dielectric layer material between the two first trenches to form a second trench reaching the surface of the substrate and expose the sidewalls of the two opposing electrodes;

[0025] An oxide nanowire functional layer of electrode metal is formed in the second trench, suspended between the opposing sidewalls of the two electrodes.

[0026] Furthermore, it also includes: forming an upper adhesion and barrier layer on the upper surface of each of the electrodes; and forming a second dielectric layer covering the functional layer between the two upper adhesion and barrier layers.

[0027] Furthermore, a copper electrode is formed in the first trench using physical vapor deposition technology.

[0028] Furthermore, a copper oxide nanowire functional layer is formed between the opposing sidewalls of the two copper electrodes using a thermal oxidation technique.

[0029] Furthermore, a first dielectric layer of low dielectric constant material is formed on the substrate using chemical vapor deposition, and the first trench is formed on the first dielectric layer using ultraviolet lithography and etching.

[0030] The present invention has the following advantages:

[0031] (1) The neural synapse device constructed based on copper oxide nanowires can realize the connection of brain synapses at the device level;

[0032] (2) Copper oxide nanowires can be used to respond to gas changes and can be applied to gas sensing to realize in-memory computing devices based on device sensing.

[0033] (3) By combining the memristor structure based on copper oxide nanowires with CMOS materials and processes, it is possible to realize the connection of brain synapses at the device level, thereby realizing the integrated neural synapse application of sensing, storage and computing.

[0034] (4) Devices can be fabricated through processes such as ultraviolet lithography and PVD. The method is simple and compatible with traditional CMOS materials and processes, as well as CMOS back-end processes.

[0035] (5) Devices can be fabricated based on photolithography, allowing for precise control of device dimensions;

[0036] (6) The electrical characteristics of the device are easy to test. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of a preferred embodiment of the present invention for a sensor-memory computing device.

[0038] Figure 2 This is a flowchart of a preferred embodiment of the present invention for fabricating a sensor-memory computing device;

[0039] Figures 3-12 According to a preferred embodiment of the present invention Figure 2A schematic diagram of the process steps for fabricating an inductive computing device. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0041] Traditional computing systems are primarily based on the von Neumann architecture, requiring information processing to be transferred between the arithmetic logic unit (ALU) and memory. However, novel integrated sensing-memory-computing devices based on the memristor, a novel semiconductor device, are inspired by the human brain. By simulating the synapses between brain cells to store and process information, they can provide a new mode of information computing and processing, potentially breaking through the traditional von Neumann computing system and achieving more efficient and lower-power information processing. The conductance of a memristor changes continuously with the amount of charge flowing through it, and this change persists even after power is turned off—a characteristic very similar to the nonlinear transmission characteristics of neural synapses. Utilizing memristors as neural synapses in neuromorphic circuits holds great promise.

[0042] This invention provides a copper oxide nanowire-based in-memory computing device based on CMOS back-end technology, belonging to the field of novel semiconductor in-memory computing artificial neural synapse devices. Specifically, it is based on CMOS process-compatible materials and is fabricated through ultraviolet lithography and physical vapor deposition processes, and is expected to be applied in the future manufacturing of in-memory computing devices.

[0043] Al, Co, Cu, CuO, and TaN are all materials compatible with and capable of being fabricated using CMOS back-end processes. Neuromorphic memristors using TaN, Al, and Co as electrodes and CuO nanowires as the functional layer can not only achieve in-memory computing with artificial synaptic functions but also realize gas responses, further achieving in-memory computing functionality. This holds promise for providing a reference for breaking through the traditional von Neumann computing architecture in the future and has significant application potential.

[0044] Currently, the highest temperature for CMOS back-end processes is approximately 400–450°C, while the current thermal oxidation growth temperature for CuO nanowires is around 400°C. In the inductively coupled plasma (ICP) device fabrication method of this invention, the impact of traditional CMOS process temperature conditions on the entire process is evaluated, and the process is optimized to achieve compatibility with traditional CMOS materials and processes, as well as CMOS back-end processes.

[0045] The conductance of a memristor changes continuously with the amount of charge flowing through it, and this change remains after power is turned off—a characteristic very similar to the nonlinear transmission properties of neural synapses. Neural synaptic devices constructed using copper oxide nanowires can simulate brain synapse connections at the device level, and copper oxide nanowires themselves can be applied to gas sensing. Combining memristors constructed using copper oxide nanowires with CMOS process materials enables the realization of lightweight, easily fabricated, and integrated sensing-memory-computing neural synaptic devices.

[0046] Based on the above research, this invention proposes a copper oxide nanowire sensing and storage device based on CMOS back-end technology and its fabrication method.

[0047] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0048] Please see Figure 1 , Figure 1 This is a schematic diagram of a preferred embodiment of the present invention, showing the structure of a sensor-memory computing device. Figure 1 As shown, a sensing and storage computing device of the present invention includes: a substrate 10; a first electrode 12 and a second electrode 17 disposed in parallel on the substrate 10; and a functional layer 15 connected between the first electrode 12 and the second electrode 17, etc., as well as several main structural components.

[0049] The functional layer 15 is composed of an interwoven structure (interlaced structure) with air gap, formed by the interlacing (interlacing) of oxide nanowires of the first electrode metal formed on the sidewall surface of the first electrode 12 and oxide nanowires of the second electrode metal formed on the sidewall surface of the second electrode 17.

[0050] In a preferred embodiment, the substrate 10 may be a conventional semiconductor substrate 10, such as a silicon substrate 10, but is not limited thereto.

[0051] In a preferred embodiment, the first electrode metal and the second electrode metal may include copper. Thus, the first electrode 12 is the first copper electrode, the second electrode 17 is the second copper electrode, and the oxide nanowires of the first and second electrode metals are copper oxide nanowires 24 formed by oxidizing the copper electrode metal on the sidewall surfaces of the first and second copper electrodes, respectively. This forms a memristor structure based on the copper oxide nanowires 24.

[0052] In a preferred embodiment, the thickness of the first copper electrode (first electrode 12) and the second copper electrode (second electrode 17) can be 300-1000 nm.

[0053] In some alternative embodiments, the first electrode metal and the second electrode metal may also be metals other than copper, and the functional layer 15 may be formed by oxide nanowires corresponding to these electrode metals.

[0054] Please see Figure 1 In a preferred embodiment, a first lower adhesion and barrier layer 11 may be provided between the substrate 10 and the first electrode 12; and a second lower adhesion and barrier layer 18 may be provided between the substrate 10 and the second electrode 17. The first lower adhesion and barrier layer 11 and the second lower adhesion and barrier layer 18 are disposed opposite to each other, thereby forming a trench between the first electrode 12 and the second electrode 17, and between the first lower adhesion and barrier layer 11 and the second lower adhesion and barrier layer 18 (see reference). Figure 10 The second trench (23) structure is described. The upper end of the trench is open, and the lower end reaches the upper surface of the silicon substrate 10, thus exposing the upper surface of the silicon substrate 10 on the bottom surface of the trench. In this way, the copper oxide nanowire functional layer 15, connecting the sidewalls of the first electrode 12 and the second electrode 17, is suspended in the trench above the silicon substrate 10 between the first lower adhesion and barrier layer 11 and the second lower adhesion and barrier layer 18. That is, a cavity 19 is formed between the copper oxide nanowire functional layer 15 and the upper surface of the silicon substrate 10.

[0055] Using the cavity 19 structure formed above, the cavity 19 can be connected to the outside, thereby utilizing the interwoven structure of the copper oxide nanowires 24 with air gaps to apply to gas sensing, realize a memory computing device based on device sensing, and realize a sensor-memory computing neural synapse application.

[0056] In a preferred embodiment, the material of the first lower adhesion and barrier layer 11 and / or the material of the second lower adhesion and barrier layer 18 may be made of a stack of Ti and Pt materials.

[0057] Furthermore, the thickness of the Ti layer material in the first lower adhesion and barrier layer 11 and / or the second lower adhesion and barrier layer 18 can be 10-20 nm, and the thickness of the Pt layer material can be 30-100 nm.

[0058] In another preferred embodiment, the material of the first lower adhesion and barrier layer 11 and / or the material of the second lower adhesion and barrier layer 18 may be made of a stack of Ta and TaN materials.

[0059] Furthermore, the thickness of the Ta layer material in the first lower adhesion and barrier layer 11 and / or the second lower adhesion and barrier layer 18 can be 10-20 nm, and the thickness of the TaN layer material can be 30-100 nm.

[0060] Please see Figure 1 In a preferred embodiment, a first upper adhesion and barrier layer 13 may be provided on the upper surface of the first electrode 12; and a second upper adhesion and barrier layer 16 may be provided on the upper surface of the second electrode 17.

[0061] In a preferred embodiment, the upper surface of the first upper adhesive and barrier layer 13 is flush with the upper surface of the second upper adhesive and barrier layer 16.

[0062] In an optional embodiment, the first upper adhesive and barrier layer 13 and the second upper adhesive and barrier layer 16 are disposed opposite to each other, and a medium layer 14 (second medium layer 14) covering the functional layer 15 may be provided between the first upper adhesive and barrier layer 13 and the second upper adhesive and barrier layer 16.

[0063] Furthermore, the dielectric layer 14 can simultaneously cover a portion of the surface of the first electrode 12 and a portion of the surface of the second electrode 17 between the first upper adhesion and barrier layer 13 and the second upper adhesion and barrier layer 16. Additionally, both ends of the dielectric layer 14 can be connected to the sidewalls of the first upper adhesion and barrier layer 13 and the second upper adhesion and barrier layer 16, respectively. In this way, the supporting effect of the first electrode 12 and the second electrode 17 on the dielectric layer 14 can be utilized to prevent the dielectric layer 14 from exerting excessive pressure on the copper oxide nanowire functional layer 15 in the trench, thereby enhancing the structural stability of the device.

[0064] In an optional embodiment, the dielectric layer 14 may not be provided between the first upper adhesion and barrier layer 13 and the second upper adhesion and barrier layer 16, so that a window communicating with the outside can be formed above the functional layer 15 between the first upper adhesion and barrier layer 13 and the second upper adhesion and barrier layer 16 (see reference). Figure 9 (Opening 22 in the middle). In this way, the window structure located above the copper oxide nanowire 24 can be combined with the cavity 19 structure located below the copper oxide nanowire 24 to form a gas convection channel, further enhancing the sensing effect and accuracy of the copper oxide nanowire 24 for external gases.

[0065] In a preferred embodiment, the material of the first upper adhesion and barrier layer 13 and / or the material of the second upper adhesion and barrier layer 16 may be made of a stack of Ta and TaN materials.

[0066] Furthermore, the thickness of the Ta layer material in the first upper adhesion and barrier layer 13 and / or the second upper adhesion and barrier layer 16 can be 10-20 nm, and the thickness of the TaN layer material can be 30-100 nm.

[0067] In a preferred embodiment, the dielectric layer 14 material may include a low dielectric constant material. For example, the dielectric layer 14 material may include a low dielectric constant material such as SiCOH.

[0068] In other alternative embodiments, the material of the dielectric layer 14 may include a light-transmitting material.

[0069] In a preferred embodiment, the upper surface of the dielectric layer 14 is flush with the upper surface of the first upper adhesion and barrier layer 13 and the upper surface of the second upper adhesion and barrier layer 16.

[0070] In a preferred embodiment, the upper surface of the dielectric layer 14 may be lower than the upper surface of the first upper adhesion and barrier layer 13 and lower than the upper surface of the second upper adhesion and barrier layer 16.

[0071] The following detailed description of a method for fabricating a sensor-based computing device according to the present invention, in conjunction with the accompanying drawings and specific embodiments, provides a detailed explanation.

[0072] Please see Figure 2 The present invention provides a method for fabricating a memcomputing device, which can be used to fabricate the aforementioned memcomputing device, and may include the following steps:

[0073] Step S1: Provide a substrate.

[0074] Please see Figure 3 In a preferred embodiment, the substrate 10 may be a conventional semiconductor substrate 10, such as a silicon substrate 10 that has undergone all or part of the CMOS front-end process. Furthermore, the silicon substrate 10 after completing all or part of the CMOS front-end process may be cleaned and dried to provide a clean silicon substrate 10 suitable for subsequent fabrication steps compatible with CMOS back-end processes.

[0075] Step S2: Form a first dielectric layer on the substrate.

[0076] Please see Figure 4 In a preferred embodiment, a first dielectric layer 20 may be grown on the surface of a silicon substrate 10 using chemical vapor deposition.

[0077] In a preferred embodiment, the first dielectric layer 20 may use a conventional interlayer dielectric layer 14 material.

[0078] Furthermore, the first dielectric layer 20 can be made of a low dielectric constant material. For example, the first dielectric layer 20 can be prepared using SiCOH, which has a low dielectric constant.

[0079] Step S3: Form two first trenches on the first dielectric layer that reach the substrate surface.

[0080] Please see Figure 5 In a preferred embodiment, ultraviolet lithography and etching techniques can be used to etch two first trenches 21 on the surface of the first dielectric layer 20, and by etching control, the lower end of the first trenches 21 reaches and stops on the upper surface of the silicon substrate 10, so that the upper surface of the silicon substrate 10 is exposed on the bottom surface of the first trenches 21.

[0081] Two first trenches 21 are formed side-by-side on the surface of the silicon substrate 10. The dimensions of each of the two first trenches 21 define the pattern dimensions of the two electrodes (first electrode 12 and second electrode 17) of the inductive computing device. The distance between the two first trenches 21 defines the dimensions of the functional layer 15 on the inductive computing device that connects the two electrodes.

[0082] Step S4: Form a lower adhesion and barrier layer on the substrate surface exposed at the bottom of each first trench.

[0083] Please see Figure 6 In a preferred embodiment, physical vapor deposition (PVD) can be used to deposit an under-adhesion and barrier layer for the electrode in the first trench 21. This forms a first under-adhesion and barrier layer 11 on the silicon substrate 10 exposed at the bottom of one of the first trenches 21, and a second under-adhesion and barrier layer 18 on the silicon substrate 10 exposed at the bottom of the other first trench 21.

[0084] In a preferred embodiment, the materials of the first lower adhesion and barrier layer 11 and the second lower adhesion and barrier layer 18 can be manufactured using a stacked material of Ta and TaN. That is, a Ta adhesion layer is first deposited on the bottom surface of the first trench 21, and then a TaN barrier layer is deposited on the Ta adhesion layer, and the Ta adhesion layer and the TaN barrier layer together form the first lower adhesion and barrier layer 11 and the second lower adhesion and barrier layer 18 having a stacked structure.

[0085] In a preferred embodiment, the thickness of the Ta adhesion layer can be 10-20 nm, and the thickness of the TaN barrier layer can be 30-100 nm.

[0086] Step S5: Form an electrode in the first trench on each of the lower adhesion and barrier layers.

[0087] Please see Figure 7In a preferred embodiment, physical vapor deposition can be used to grow electrode metals on a first under-adhesion and barrier layer 11 and a second under-adhesion and barrier layer 18 located in the two first trenches 21, respectively, and to fill the first trenches 21 to form a first electrode 12 on the first under-adhesion and barrier layer 11, while a second electrode 17 is formed on the second under-adhesion and barrier layer 18.

[0088] Please see Figure 8 In a preferred embodiment, the deposited electrode metal can be planarized using CMP technology to remove excess electrode metal outside the first trench 21, and to make the surfaces of the first electrode 12 and the second electrode 17 flush with the surface of the first dielectric layer 20.

[0089] In a preferred embodiment, the electrode metal can be deposited using metallic copper. That is, the first electrode 12 and the second electrode 17 can be formed using metallic copper (first copper electrode and second copper electrode).

[0090] In a preferred embodiment, the thickness of the first electrode 12 and the second electrode 17 can be 300-1000 nm.

[0091] Step S6: Form an upper adhesion and barrier layer on the upper surface of each electrode.

[0092] Please see Figure 9 In a preferred embodiment, ultraviolet lithography and physical vapor deposition techniques can be used to deposit the top adhesion and barrier layers on the electrodes. This forms a patterned first top adhesion and barrier layer 13 on the surface of the first electrode 12, and a patterned second top adhesion and barrier layer 16 on the surface of the second electrode 17.

[0093] In a preferred embodiment, the materials of the first upper adhesion and barrier layer 13 and the second upper adhesion and barrier layer 16 can be manufactured using a stacked material of Ta and TaN. Specifically, a Ta adhesion layer is first deposited on the surface of the first electrode 12 and the surface of the second electrode 17, and then a TaN barrier layer is deposited on the Ta adhesion layer, thereby further forming a first upper adhesion and barrier layer 13 pattern and a second upper adhesion and barrier layer 16 pattern with a stacked structure composed of the Ta adhesion layer and the TaN barrier layer.

[0094] In a preferred embodiment, the thickness of the Ta adhesion layer can be 10-20 nm, and the thickness of the TaN barrier layer can be 30-100 nm.

[0095] In a preferred embodiment, the width of the opening 22 (window) between the first upper adhesion and barrier layer 13 and the second upper adhesion and barrier layer 16 may be greater than the distance between the first electrode 12 and the second electrode 17 (i.e., the width of the first dielectric layer 20).

[0096] Step S7: Remove the first dielectric layer material between the two first trenches to form a second trench reaching the substrate surface and expose the sidewalls of the two opposing electrodes.

[0097] Please see Figure 10 In a preferred embodiment, etching techniques can be used to selectively remove the material of the first dielectric layer 20 between the two first trenches 21, thereby forming a second trench 23 between the first electrode 12 and the second electrode 17, and between the first lower adhesion and barrier layer 11 and the second lower adhesion and barrier layer 18 (corresponding to...). Figure 1 (groove structure in the middle).

[0098] After the material of the first dielectric layer 20 between the two first trenches 21 is removed, the lower end of the formed second trench 23 reaches the upper surface of the silicon substrate 10, so that the upper surface of the silicon substrate 10 is exposed on the bottom surface of the second trench 23.

[0099] Meanwhile, the sidewall of the second trench 23 is formed by two opposing sidewalls of the first electrode 12 and the second electrode 17, as well as two opposing sidewalls of the first lower adhesion and barrier layer 11 and the second lower adhesion and barrier layer 18. That is, the two opposing sidewalls of the first electrode 12 and the second electrode 17 are exposed on the sidewall of the second trench 23, and the two opposing sidewalls of the first lower adhesion and barrier layer 11 and the second lower adhesion and barrier layer 18 are also exposed on the sidewall of the second trench 23.

[0100] Step S8: Form an oxide nanowire functional layer of electrode metal suspended between the opposite sidewalls of the two electrodes in the second trench.

[0101] Please see Figure 11 In a preferred embodiment, a thermal oxidation technique can be used to form copper oxide nanowires 24 between two opposing sidewalls of the first electrode 12 and the second electrode 17, which are made of metallic copper material, as a functional layer 15 of the memristor.

[0102] During the thermal oxidation of the first electrode 12 and the second electrode 17, copper oxide nanowires 24 grown from the sidewall surface of the first electrode 12 in the second trench 23 will grow towards the sidewall surface of the second electrode 17 in the second trench 23; simultaneously, copper oxide nanowires 24 grown from the sidewall surface of the second electrode 17 in the second trench 23 will also grow towards the sidewall surface of the first electrode 12 in the second trench 23. In this way, the copper oxide nanowires 24 growing in opposite directions will interweave, entangle, and contact each other, forming an interwoven structure with air gaps. The first electrode 12 and the second electrode 17 are connected by the grown copper oxide nanowires 24 serving as the functional layer 15.

[0103] Furthermore, by setting the first lower adhesion and barrier layer 11 and the second lower adhesion and barrier layer 18 below the first electrode 12 and the second electrode 17, the height position of the first electrode 12 and the second electrode 17 in the second trench 23 is raised, so that the grown copper oxide nanowire 24 is suspended in the second trench 23, and a cavity 19 structure is formed between the copper oxide nanowire functional layer 15 and the upper surface of the silicon substrate 10.

[0104] Furthermore, it may include step S9: forming a second dielectric layer covering the functional layer between the two upper adhesion and barrier layers.

[0105] Please see Figure 12 In a preferred embodiment, a second dielectric layer 14 (corresponding to) can be formed by depositing a chemical vapor deposition technique in the opening between the first upper adhesion and barrier layer 13 and the second upper adhesion and barrier layer 16. Figure 1 The dielectric layer 14 is formed and planarized. The formed second dielectric layer 14 covers the surface of the functional layer 15, as well as a portion of the surface of the first electrode 12 and the second electrode 17.

[0106] Alternatively, by etching back, the upper surface of the second dielectric layer 14 can be made lower than the upper surface of the first upper adhesion and barrier layer 13 and lower than the upper surface of the second upper adhesion and barrier layer 16.

[0107] In a preferred embodiment, the second dielectric layer 14 can be prepared using conventional interlayer dielectric layer 14 materials.

[0108] Furthermore, the second dielectric layer 14 can be fabricated using a low dielectric constant material. For example, the second dielectric layer 14 can be fabricated using SiCOH, which has a low dielectric constant.

[0109] In an alternative embodiment, the material of the second dielectric layer 14 may include a light-transmitting material.

[0110] In other embodiments, the step of depositing the second dielectric layer 14 can be omitted, and the opening 22 located between the first upper adhesion and barrier layer 13 and the second upper adhesion and barrier layer 16 can be used as a window for the copper oxide nanowire 24 to communicate with the outside.

[0111] In summary, by combining the memristor constructed based on copper oxide nanowires 24 with CMOS process materials, this invention can realize a sensor-memory-computing integrated neural synapse device with the characteristics of being lightweight and easy to fabricate. It is expected to provide a reference for future breakthroughs in the traditional von Neumann computing architecture and has great application prospects.

[0112] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A sensing-memory computing device, characterized in that, include: Substrate; The first electrode and the second electrode are arranged side by side on the substrate; A functional layer connecting the first electrode and the second electrode; The functional layer is composed of oxide nanowires of a first electrode metal formed on the surface of the first electrode and oxide nanowires of a second electrode metal formed on the surface of the second electrode. A first lower adhesion and barrier layer is provided between the substrate and the first electrode, and a second lower adhesion and barrier layer is provided between the substrate and the second electrode. The functional layer is suspended above the substrate between the first lower adhesion and barrier layer and the second lower adhesion and barrier layer.

2. The inductive computing device according to claim 1, characterized in that, A first upper adhesion and barrier layer is provided on the upper surface of the first electrode, and a second upper adhesion and barrier layer is provided on the upper surface of the second electrode. A dielectric layer covering the functional layer is provided between the first upper adhesion and barrier layer and the second upper adhesion and barrier layer.

3. The inductive computing device according to claim 1, characterized in that, The first electrode metal and the second electrode metal include copper, and the oxide nanowires of the first electrode metal and the oxide nanowires of the second electrode metal include copper oxide nanowires.

4. The inductive computing device according to claim 2, characterized in that, The dielectric layer material includes a low dielectric constant material.

5. A method for fabricating an inductive computing device, characterized in that, include: Provide substrate; A first dielectric layer is formed on the substrate; Two first trenches are formed on the first dielectric layer, extending to the surface of the substrate; A lower adhesion and barrier layer is formed on the substrate surface exposed at the bottom of each of the first trenches; An electrode is formed in each of the first trenches on each of the lower adhesion and barrier layers; Remove the first dielectric layer material between the two first trenches to form a second trench reaching the surface of the substrate and expose the sidewalls of the two opposing electrodes; An oxide nanowire functional layer of electrode metal is formed in the second trench, suspended between the opposing sidewalls of the two electrodes.

6. The method for fabricating a sensor-memory computing device according to claim 5, characterized in that, Also includes: An upper adhesion and barrier layer is formed on the upper surface of each electrode; as well as A second dielectric layer covering the functional layer is formed between the two aforementioned adhesion and barrier layers.

7. The method for fabricating a sensory computing device according to claim 5, characterized in that, A copper electrode is formed in the first trench using physical vapor deposition.

8. The method for fabricating a sensory computing device according to claim 7, characterized in that, A copper oxide nanowire functional layer is formed between the opposing sidewalls of the two copper electrodes using a thermal oxidation technique.

9. The method for fabricating a sensory computing device according to claim 5, characterized in that, A first dielectric layer of low dielectric constant material is formed on the substrate using chemical vapor deposition, and the first trench is formed on the first dielectric layer using ultraviolet lithography and etching.

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