Memory detection method and memory detection device

Abstract

The embodiment of the present invention provides a detection method and a detection device of a memory, the detection method comprising: the memory comprises a first storage unit, a second storage unit, a bit line, a complementary bit line and a word line; the memory further comprises a plurality of sense amplifiers, each sense amplifier is electrically coupled to a bit line and a complementary bit line; storage data is written to each first storage unit and the second storage unit, wherein the storage data in the first storage unit connected to each bit line is the same as the storage data in the second storage unit connected to its corresponding complementary bit line; the reading operation comprises: sequentially selecting all word lines for reading, so as to read the real data in each first storage unit and the second storage unit through the bit line, the complementary bit line and the sense amplifier; based on the difference between the real data and the storage data, obtaining the test result; based on the test result, obtaining the leakage position of the bit line or the complementary bit line and the word line. The embodiment of the present invention is conducive to faster detection of the leakage position.

Description

Technical Field

[0001] The embodiments of the present invention relate to the semiconductor field, and in particular to a memory detection method and a memory detection device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers, consisting of many repeated storage cells. Each storage cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.

[0003] As DRAM manufacturing technology becomes more and more advanced and storage density becomes higher and higher, more and more problems have also appeared in the DRAM manufacturing process, such as short circuits caused by by-product dropping, bit line leakage current, capacitor collapse, metal line breakage, structural problems caused by unqualified key dimensions, etc. These problems in the process need to be screened out during the yield test. However, the existing yield test method needs to write two different storage data into the storage unit in succession to detect the leakage position. The leakage position can only be obtained after two tests, and the detection speed is slow.

[0004] How to quickly detect the location of leakage during the yield test process is a problem that technical personnel in this field need to solve urgently. Summary of the invention

[0005] The embodiments of the present invention provide a memory detection method and a memory detection device, which are helpful to solve the problem of slow detection of leakage position of the memory.

[0006] To solve the above problems, an embodiment of the present invention provides a detection method for a memory, comprising: the memory comprises a plurality of first memory cells, a plurality of second memory cells, a plurality of mutually separate bit lines, a plurality of mutually separate complementary bit lines and a plurality of mutually separate word lines, each of the complementary bit lines corresponds to a bit line, the first memory cell is connected to a corresponding bit line and a word line, and the second memory cell is connected to a corresponding complementary bit line and a word line; the memory further comprises a plurality of sense amplifiers, each of the sense amplifiers is electrically coupled to a bit line and a complementary bit line; a storage register is written to each of the first memory cell and the second memory cell; data, wherein the storage data in the first storage unit connected to each of the bit lines is the same as the storage data in the second storage unit connected to the corresponding complementary bit line; after writing the storage data, performing a read operation, the read operation comprising: sequentially selecting all the word lines for reading, so as to read the real data in each of the first storage unit and the second storage unit through the bit lines, the complementary bit lines and the sense amplifier; obtaining a test result based on the difference between the real data and the storage data; and obtaining the leakage position of the bit line or the complementary bit line and the word line based on the test result corresponding to each of the first storage unit and the second storage unit.

[0007] In addition, the manner of writing the storage data into the first storage unit and the second storage unit includes: writing the same storage data into all of the first storage units and the second storage units.

[0008] In addition, the storage data written into each of the first storage unit and the second storage unit is at a logic low level.

[0009] In addition, the method of writing the storage data into the first storage unit further includes: writing different storage data into a plurality of the first storage units connected to the adjacent bit lines.

[0010] In addition, the method of writing the storage data into the second storage unit further includes: writing different storage data into a plurality of the second storage units connected to the adjacent complementary bit lines.

[0011] In addition, after selecting one of the word lines, the method further includes: precharging the bit line and the corresponding complementary bit line, wherein the precharged bit line and the corresponding complementary bit line have the same level.

[0012] In addition, before performing the reading operation, the method further includes: performing an automatic refresh operation on all the first storage units and the second storage units.

[0013] In addition, before writing the storage data into each of the first storage unit and the second storage unit, the method further includes: performing an initialization operation on the first storage unit and the second storage unit to activate the first storage unit and the second storage unit.

[0014] In addition, the step of obtaining the leakage position of the bit line or the complementary bit line and the word line based on the test result corresponding to each of the first storage unit and the second storage unit specifically includes: the storage data of all the first storage units connected to the same bit line is different from the real data, and the storage data of a unique second storage unit among the second storage units connected to the corresponding complementary bit line is different from the real data, and the test result is the leakage of the complementary bit line and the word line connected to the unique second storage unit.

[0015] In addition, the step of obtaining the leakage position of the bit line or the complementary bit line and the word line based on the test result corresponding to each of the first storage unit and the second storage unit specifically includes: the storage data of all the second storage units connected to the same complementary bit line is different from the real data, and the storage data of a unique first storage unit among the first storage units connected to the corresponding bit line is different from the real data, and the test result is the leakage of the bit line and the word line connected to the unique first storage unit.

[0016] The embodiment of the present invention further provides a detection device for a memory, comprising: a memory, wherein the memory comprises a plurality of first memory cells, a plurality of second memory cells, a plurality of mutually discrete bit lines, a plurality of mutually discrete complementary bit lines, and a plurality of mutually discrete word lines, each of the complementary bit lines corresponds to a bit line, the first memory cell is connected to a corresponding bit line and a word line, and the second memory cell is connected to a corresponding complementary bit line and a word line; the memory further comprises a plurality of sense amplifiers, each of the sense amplifiers is electrically coupled to a bit line and a complementary bit line; a writing device is used to write storage data to the first memory cell and the second memory cell; a reading device is used to read the storage data from the first memory cell and the second memory cell; The device comprises a read device for sequentially selecting all the word lines for reading, so as to read the real data in each of the first storage unit and the second storage unit through the bit line, the complementary bit line and the sense amplifier; an instruction device for controlling the write device to write the same storage data into the first storage unit connected to each of the bit lines and the second storage unit connected to the corresponding complementary bit line; and an error reporting device, the error reporting device obtains a test result based on the difference between the real data and the storage data, and obtains the leakage position of the bit line or the complementary bit line and the word line based on the test result corresponding to each of the first storage unit and the second storage unit.

[0017] In addition, it also includes: an instruction decoder, which is used to adjust the type of the storage data written by the writing device to the first storage unit and the second storage unit according to the instruction issued by the instruction device.

[0018] In addition, it also includes: a precharging device, which is used to precharge the bit line and the corresponding complementary bit line, so that after one of the word lines is selected, the level of the precharged bit line is the same as the level of the corresponding complementary bit line after precharging.

[0019] In addition, it also includes: an automatic refresh device for periodically performing automatic refresh operations on the first storage unit and the second storage unit.

[0020] In addition, the error reporting device further includes a judgment device, and the judgment device is used to judge the leakage position of the bit line or the complementary bit line and the word line according to the test result.

[0021] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:

[0022] The detection method of the memory provided by the embodiment of the present invention is that the storage data written into the first storage unit connected to each bit line and the second storage unit connected to its corresponding complementary bit line are the same. When reading, when the selected bit line and the corresponding complementary bit line are not leaking, the selected word line is connected to one of the bit line and the complementary bit line, and the result of reading is that the one not connected to the selected word line is a logic high level; in this way, when the logic level of the read first storage unit does not match the preset result, the influencing factor is the leakage current of the short circuit between the bit line and the selected word line or the leakage current of the short circuit between the corresponding complementary bit line and a non-selected word line; when the logic level of the read second storage unit does not match the preset result, the influencing factor is the leakage current of the short circuit between the complementary bit line and the corresponding complementary bit line and a non-selected word line; The leakage current is shorted between the selected word line or the corresponding bit line and a non-selected word line, and all word lines are selected in sequence. Combined with the test results of all first storage units and second storage units connected to a bit line and the corresponding complementary bit line, the exact position of the leakage current can be determined. By using this method to select all word lines in sequence, the characteristic that when the logic levels of the bit line and the corresponding complementary bit line are the same, whichever one is connected to the selected word line is a logic low level. There is no need to write two logic levels into the first storage unit and the second storage unit respectively to compare the test results. The accurate position of the bit line or the complementary bit line of the leakage current can be obtained without omission based on one test result, thereby improving the detection efficiency of the memory detection method.

[0023] In addition, the storage data written into each of the first storage unit and the second storage unit are all at a logic low level, thereby preventing the possibility that the logic high level in the storage unit may decrease over time and affect the accuracy of the test result.

[0024] In addition, the bit line and the corresponding complementary bit line are precharged, and the precharged bit line and the corresponding complementary bit line have the same level, which avoids the influence of other factors on the sensing amplifier selecting the bit line with a larger level between the bit line and the corresponding complementary bit line, ensuring that the detected potential situation fully reflects the condition of the memory itself, which is conducive to improving the accuracy of detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0026] Figure 1 A schematic diagram of the structure of a memory in an embodiment of the present invention;

[0027] Figure 2 A schematic diagram of logic level changes of a first bit line and a corresponding complementary bit line in an embodiment of the present invention;

[0028] Figure 3 A schematic diagram of logic level changes of a second type of bit line and a corresponding complementary bit line in one embodiment of the present invention;

[0029] Figure 4 A schematic diagram of logic level changes of a third type of bit line and a corresponding complementary bit line in an embodiment of the present invention;

[0030] Figure 5 A schematic diagram of logic level changes of a fourth type of bit line and a corresponding complementary bit line in an embodiment of the present invention;

[0031] Figure 6 A schematic diagram of logic level changes of a fifth bit line and a corresponding complementary bit line in an embodiment of the present invention;

[0032] Figure 7 A schematic diagram of logic level changes of a sixth type of bit line and a corresponding complementary bit line in an embodiment of the present invention;

[0033] Figure 8 FIG. 4 is a schematic diagram of a module of a memory detection device in yet another embodiment of the present invention. DETAILED DESCRIPTION

[0034] As can be seen from the background art, the detection speed of the memory detection method in the prior art needs to be improved.

[0035] Now, a detection method of a memory is analyzed. The detection method includes: the memory includes a first storage unit and a second storage unit, the first storage unit is a storage unit connected to a bit line, and the second storage unit is a storage unit connected to a complementary bit line. The storage data is written into each storage unit for the first time, the first storage data is written into the first storage unit, and the second storage data is written into the second storage unit, and the first storage data and the second storage data are different; after writing the storage data, a reading operation is performed, and the reading operation includes: sequentially selecting all word lines for reading, so as to read the first real data in each storage unit through the bit line or the complementary bit line and the sense amplifier, and before reading, simultaneously selecting the power supply providing a low potential voltage in the sense amplifier corresponding to the bit line and the complementary bit line line NCS, and a power line PCS corresponding to the bit line or the complementary bit line that provides a high potential voltage, so that the logic level of the one with a higher logic level between the bit line and the complementary bit line is increased; based on the difference between the first real data and the storage data written for the first time, a first test result is obtained; the storage data is written to each storage unit for a second time, the second storage data is written to the first storage unit, and the first storage data is written to the second storage unit; after the storage data is written for the second time, a read operation is performed again to read the second real data in each storage unit; based on the difference between the second real data and the storage data written for the second time, a second test result is obtained; based on the second test result and the first test result, the specific position of the leaking bit line is obtained.

[0036] When the bit line is short-circuited with the word line, the following four situations will occur during detection: in the first situation, the bit line is at a low level. When the bit line is short-circuited with the enabled word line, the bit line becomes a high level, and the read result is a bit line high level, which is inconsistent with the actual situation, and the defect is confirmed, thereby detecting the specific position of the leakage potential line; in the second situation, the bit line is at a high level. When the bit line is short-circuited with the enabled word line, the bit line is still at a high level, and the read result is a bit line high level, which is consistent with the actual situation, and the defect cannot be obtained, and the specific position of the leakage potential line cannot be detected; in the third situation, the bit line is at a low level. When the bit line is short-circuited with the unselected word line, the bit line is still at a low level. The read result is a bit line low level, which is consistent with the actual situation, and the defect cannot be obtained, and the specific position of the leakage potential line cannot be detected; in the fourth situation, the bit line is at a high level. When the bit line is short-circuited with the unselected word line, the bit line becomes a low level. The read result is a bit line low level, which is inconsistent with the actual situation, and the defect is confirmed, thereby detecting the specific position of the leakage current bit line.

[0037] Among them, the second and third cases cannot be used to find defects, but by selecting all word lines in sequence, the second case can be changed to the fourth case, and the third case can be changed to the first case, so that the bit line leakage current caused by the short circuit between the bit line and the word line can be detected. The case of the short circuit between the complementary bit line and the word line is the same as the case of the short circuit between the bit line and the word line, which will not be repeated here.

[0038] From the above, it can be seen that this memory detection method needs to write different storage data to the storage unit twice respectively. Each time the storage data is written, the storage data of the first storage unit is different from the storage data of the second storage unit. Only then can the specific location of the leakage be obtained through the two test results. The detection speed is slow, which is not conducive to quickly obtaining the specific location of the memory leakage.

[0039] In order to solve the above problems, the present invention provides a detection method for a memory, wherein the storage data written into the first storage unit connected to each bit line and the second storage unit connected to its corresponding complementary bit line are the same, and when reading, when the selected bit line and the corresponding complementary bit line are not leaking, the selected word line is connected to one of the bit line and the complementary bit line, and the result of reading is that the one not connected to the selected word line is a logic high level; in this way, when the logic level of the read first storage unit does not match the preset result, the influencing factor is the leakage current of the short circuit between the bit line and the selected word line or the leakage current of the short circuit between the corresponding complementary bit line and a non-selected word line, and when the logic level of the read second storage unit does not match the preset result, the influencing factor is a mutual leakage current. The leakage current is shorted between the complementary bit line and the selected word line, or the leakage current is shorted between the corresponding bit line and a non-selected word line. All word lines are selected in sequence, and the test results of all first storage units and second storage units connected to a bit line and the corresponding complementary bit line are combined to determine the exact position of the leakage current. By using this method to select all word lines in sequence, the characteristic that when the logic levels of the bit line and the corresponding complementary bit line are the same, whichever one is connected to the selected word line is a logic low level. There is no need to write two logic levels into the first storage unit and the second storage unit respectively to compare the test results. The accurate position of the bit line or the complementary bit line of the leakage current can be obtained without omission based on one test result, thereby improving the detection efficiency of the memory detection method.

[0040] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

[0041] Figure 1Schematic diagram of the structure of the memory in the embodiment of the present invention.

[0042] The memory detection method provided in this embodiment includes: referring to Figure 1 The memory 100 includes a plurality of first memory cells 101, a plurality of second memory cells 102, a plurality of mutually independent bit lines 103, a plurality of mutually independent complementary bit lines 104, and a plurality of mutually independent word lines 105, each complementary bit line 104 corresponds to a bit line 103, the first memory cells 101 are connected to a corresponding bit line 103 and a word line 105, and the second memory cells 102 are connected to a corresponding complementary bit line 104 and a word line 105; the memory 100 also includes a plurality of sense amplifiers 106, each sense amplifier 106 is electrically coupled to a bit line 103 and a complementary bit line 104.

[0043] In this embodiment, the sense amplifier 106 includes a power line NCS providing a low potential voltage and a power line PCS providing a high potential voltage.

[0044] First, an initialization operation is performed on the first storage cell 101 and the second storage cell 102 to activate the first storage cell 101 and the second storage cell 102; after the initialization operation, a write operation is performed to write storage data into each of the first storage cell 101 and the second storage cell 102, wherein the storage data in the first storage cell 101 connected to each bit line 103 is the same as the storage data in the second storage cell 102 connected to its corresponding complementary bit line 104.

[0045] Assuming that the storage data written into the first storage unit 101 connected to each bit line 103 and the second storage unit 102 connected to its corresponding complementary bit line 104 are the same, in this embodiment, taking writing the same logic low level as an example, when reading, when the selected bit line 103 and the corresponding complementary bit line 104 are not leaking electricity, the selected word line 105 is connected to one of the bit line 103 and the complementary bit line 104, and the result of reading is that the one not connected to the selected word line 105 is a logic high level; using this method to select all word lines 105 in sequence, using the characteristic that when the logic levels of the bit line 103 and the corresponding complementary bit line 104 are the same, the selected word line 105 and the one not connected to the other are the logic high level, there is no need to write two logic levels in the first storage unit 101 and the second storage unit 102 respectively to compare the test results, and the accurate position of the bit line or complementary bit line with leakage current can be obtained without omission based on one test result, thereby improving the detection efficiency of the memory detection method.

[0046] In this embodiment, the manner of writing storage data into the first storage unit 101 and the second storage unit 102 includes: writing the same storage data into all the first storage units 101 and the second storage units 102 .

[0047] In other embodiments, the method of writing storage data into the first storage unit 101 further includes: writing different storage data into a plurality of first storage units 101 connected to adjacent bit lines 103 .

[0048] In other embodiments, the method of writing storage data into the second storage unit further includes: writing different storage data into a plurality of second storage units connected to adjacent complementary bit lines.

[0049] In this embodiment, the storage data written to each of the first storage unit 101 and the second storage unit 102 are all at a logic low level; the storage data written to each of the first storage unit 101 and the second storage unit 102 are all at a logic low level, which eliminates the possibility that the logic high level in the storage unit may decrease over time and affect the accuracy of the test result. In other embodiments, the storage data written to each of the first storage unit and the second storage unit may also be at a logic high level.

[0050] In this embodiment, after the storage data is written into the first storage unit 101 and the second storage unit 102 , an automatic refresh operation may be performed on all the first storage units 101 and the second storage units 102 .

[0051] A read operation is performed, and the read operation includes: sequentially selecting all word lines 105 for reading, so as to read the real data in each first storage unit 101 and the second storage unit 102 through the bit line 103, the complementary bit line 104 and the sense amplifier 106; based on the difference between the real data and the stored data, a test result is obtained; based on the test result corresponding to each first storage unit 101 and the second storage unit 102, the leakage position of the bit line 103 or the complementary bit line 104 and the word line 105 is obtained.

[0052] In this embodiment, before reading, the power line NCS providing a low potential voltage and the power line PCS providing a high potential voltage corresponding to the bit line 103 and the complementary bit line 104 are simultaneously selected to increase the level of the one with a higher logic level among the bit line 103 and the complementary bit line 104; then, an automatic refresh operation can be performed on all the first storage cells 101 and the second storage cells 102.

[0053] It is important to know that when a logic low level is written into the first storage unit 101 connected to each bit line 103 and the second storage unit 102 connected to the corresponding complementary bit line 104, when reading, when the selected bit line 103 and the corresponding complementary bit line 104 are not leaking electricity, the selected word line 105 is connected to one of the bit line 103 and the complementary bit line 104, and the read result is that the one not connected to the selected word line 105 is a logic high level.

[0054] The following will describe in detail the logic level changes of the bit line 103 and the complementary bit line 104 in various situations during the detection process in conjunction with the accompanying drawings. The storage data written to each first storage unit 101 and second storage unit 102 are all at a logic low level; all the word lines are sequentially selected for reading.

[0055] In the first case, a complementary bit line 104 and a word line 105 are short-circuited, resulting in a leakage current in a second memory cell 102. Figure 2 to Figure 4 In this case, there are three types of logic level changes of the bit line 103 and the complementary bit line 104.

[0056] Figure 2 Schematic diagram of logic level changes of a first bit line and a corresponding complementary bit line in an embodiment of the present invention.

[0057] refer to Figure 2 , the first type, when the first storage unit 101 corresponding to the second storage unit 102 with leakage is selected, an activation operation ACT is performed at the T0 time node, and after the activation operation ACT, a pre-charge process is performed on the power line NCS providing a low potential voltage and the power line PCS providing a high potential voltage. After the pre-charge process, the level of the power line NCS providing a low potential voltage is the same as the level of the power line PCS providing a high potential voltage; the selected bit line 103 and the corresponding complementary bit line 104 enter the charge sharing stage, and the bit line 103 and the corresponding complementary bit line 104 are pre-charged. The pre-charged bit line 103 and the corresponding complementary bit line 104 have the same level; a word line 105 connected to the first storage unit 101 is selected at the T1 time node; during the T1-T2 time In the segment, since the selected word line 105 is connected to the bit line 103, the level of the bit line 103 drops slightly, but since the complementary bit line 104 is short-circuited with the unselected word line 105, the complementary bit line 104 drops to a low level; at the T2 time node, the sense amplifier is turned on, and the power line NCS providing a low potential voltage and the power line PCS providing a high potential voltage corresponding to the bit line 103 and the complementary bit line 104 are selected to increase the level of the higher level of the bit line 103 and the complementary bit line 104. Since the level of the complementary bit line 104 is lower than the level of the bit line 103, the bit line 103 is high after reading, which is inconsistent with the low level of the bit line 103 to be read; all the first storage cells 101 corresponding to the second storage cell 102 with leakage are sequentially selected, and the read results are consistent with Figure 2 same.

[0058] The following will describe in detail the situation where the selected and drained second storage unit 102 is connected to other second storage units 102 of the same complementary bit line 104, and the same parts as the selected first storage unit 101 will not be repeated.

[0059] Figure 3 Schematic diagram of logic level changes of the second bit line and the corresponding complementary bit line in one embodiment of the present invention.

[0060] refer to Figure 3 In the second type, when the second memory cell 102 connected to the same complementary bit line 104 as the second memory cell 102 with leakage is selected, since the selected word line 105 is connected to the complementary bit line 104, the level of the complementary bit line 104 drops slightly, and the level of the bit line 103 remains unchanged, and the complementary bit line 104 should be read as a low level. In fact, since the complementary bit line 104 is short-circuited with the non-selected word line 105, the complementary bit line 104 drops to a low level, and the read complementary bit line 104 is also a low level, which is consistent with the actual situation.

[0061] All other second storage cells 102 connected to the same complementary bit line 104 as the leaky second storage cell 102 are sequentially selected, and the read result is the same as Figure 3 Consistent.

[0062] The following will describe in detail the case of enabling the second memory cell 102 with leakage, and the same parts as enabling the first memory cell 101 will not be described in detail.

[0063] Figure 4 Schematic diagram of logic level changes of the third bit line and the corresponding complementary bit line in one embodiment of the present invention.

[0064] refer to Figure 4 In the third category, when the second memory cell 102 with leakage is selected, the level of the bit line 103 remains unchanged, and the level of the complementary bit line 104 is pulled to a high level by the selected word line 105. The read result is a high level of the complementary bit line 104, which is inconsistent with the actual result to be read.

[0065] In summary, according to the changes in the logic levels of the three types of bit lines 103 and complementary bit lines 104, the first situation of short circuit of the bit line 103 or the complementary bit line 104 is analyzed: in the first category, there are two reasons for the error in the read level of the bit line 103: the first is that the first storage unit 101 that is selected is short-circuited; the second is that at least one of all the second storage units 102 connected to the corresponding complementary bit line 104 is short-circuited; first, it is assumed that all the second storage units 102 connected to the corresponding complementary bit lines 104 are not short-circuited, and the assumption is verified in combination with the second and third categories, and the results of all the second storage units 102 connected to the complementary bit lines 104 that are sequentially selected are analyzed, wherein in the third category, there is a second storage unit 102 whose read condition is a high level of the complementary bit line 104, and the read result is inconsistent with the preset result of no short circuit, and in the second category, the read result of the connection to other second storage units 102 is a low level of the complementary bit line 104, and the read result is consistent with the preset result of no short circuit. Therefore, it can be determined that the assumption is not true, that is, at least one of all the second storage cells 102 connected to the corresponding complementary bit lines 104 is short-circuited. According to the result, it can be determined that the leakage position is the second storage cell 102 connected in the third case.

[0066] In summary, it can be concluded that the storage data of all the first storage cells 101 connected to the same bit line 103 are different from the real data, and the storage data of a unique second storage cell 102 among the second storage cells 102 connected to the corresponding complementary bit line 104 is different from the real data. The test result shows that the complementary bit line 104 and the word line 105 connected to the unique second storage cell 102 are leaking.

[0067] Next, the second situation that the bit line 103 or the complementary bit line 104 is short-circuited, that is, a situation that a bit line 103 and a word line 105 are short-circuited and cause a leakage current of a first storage unit 101 is described in detail; Figure 5 to Figure 7 In this case, there are also three types of changes in the logic levels of the bit line 103 and the complementary bit line 104.

[0068] Figure 5 Schematic diagram of logic level changes of a fourth type of bit line and a corresponding complementary bit line in an embodiment of the present invention.

[0069] refer to Figure 5, the first type, when the second storage unit 102 corresponding to the first storage unit 101 with leakage is selected, an activation operation ACT is performed at the T0 time node, and after the activation operation ACT, a pre-charge process is performed on the power line NCS providing a low potential voltage and the power line PCS providing a high potential voltage. After the pre-charge process, the level of the power line NCS providing a low potential voltage is the same as the level of the power line PCS providing a high potential voltage; the selected bit line 103 and the corresponding complementary bit line 104 enter the charge sharing stage, and the bit line 103 and the corresponding complementary bit line 104 are pre-charged. The pre-charged bit line 103 and the corresponding complementary bit line 104 have the same level; a word line 105 connected to the second storage unit 102 is selected at the T1 time node; in the T1-T2 time period , since the selected word line 105 is connected to the complementary bit line 104, the level of the complementary bit line 104 drops slightly, but since the bit line 103 is short-circuited with the unselected word line 105, the bit line 103 drops to a low level; at time node T2, the sense amplifier is turned on, and the power line NCS providing a low potential voltage and the power line PCS providing a high potential voltage corresponding to the bit line 103 and the complementary bit line 104 are selected to increase the level of the higher level of the bit line 103 and the complementary bit line 104. Since the level of the bit line 103 is lower than the level of the complementary bit line 104, the complementary bit line 104 is at a high level after reading, which is inconsistent with the low level of the complementary bit line 104 that should be read; all the second storage cells 102 corresponding to the first leakage storage cell 101 are sequentially selected, and the read results are consistent with Figure 5 same.

[0070] The following will describe in detail the situation where the first memory cell 101 that is enabled and leaked is connected to other first memory cells 101 of the same bit line 103, and the same part as the second memory cell 102 that is enabled will not be described again.

[0071] Figure 6 Schematic diagram of logic level changes of a fifth bit line and a corresponding complementary bit line in an embodiment of the present invention.

[0072] refer to Figure 6 In the second type, when other first storage cells 101 connected to the same bit line 103 as the leaking first storage cell 101 are selected, since the selected word line 105 is connected to the bit line 103, the level of the bit line 103 drops slightly, and the level of the complementary bit line 104 remains unchanged, and the bit line 103 should be read as a low level. In fact, since the bit line 103 is short-circuited with the unselected word line 105, the bit line 103 drops to a low level, and the read bit line 103 is also a low level, which is consistent with the actual situation.

[0073] All other first storage cells 101 connected to the same bit line 103 as the leaky first storage cell 101 are sequentially selected, and the read result is the same as Figure 6Consistent.

[0074] The following will describe in detail the case of enabling the leaky first memory cell 101, and the same parts as enabling the second memory cell 102 will not be described in detail.

[0075] Figure 7 Schematic diagram of logic level changes of a sixth type of bit line and a corresponding complementary bit line in an embodiment of the present invention.

[0076] refer to Figure 7 In the third category, when the first memory cell 101 with leakage is selected, the level of the complementary bit line 104 remains unchanged, and the level of the bit line 103 is pulled to a high level by the selected word line 105. The read result is a high level of the bit line 103, which is inconsistent with the actual result to be read.

[0077] In summary, according to the changes in the logic levels of the three types of bit lines 103 and complementary bit lines 104, the second situation of short circuit of the bit line 103 or the complementary bit line 104 is analyzed: in the first category, there are two reasons for the error in the read level of the complementary bit line 104: the first is that the second storage unit 102 that is selected is short-circuited; the second is that at least one of all the first storage units 101 connected to the corresponding bit line 103 is short-circuited; first, it is assumed that all the first storage units 101 connected to the corresponding bit line 103 are not short-circuited, and the assumption is verified in combination with the second and third categories, and the results of all the first storage units 101 connected to the bit lines 103 that are selected in sequence are analyzed, wherein in the third category, there is a first storage unit 101 whose read condition is a high level of the bit line 103, and the read result is inconsistent with the preset result of no short circuit, and in the second category, the read result of connecting other first storage units 101 is a low level of the bit line 103, and the read result is consistent with the preset result of no short circuit. Therefore, it can be determined that the assumption is not true, that is, at least one of all the first storage cells 101 connected to the corresponding bit line 103 is short-circuited. According to the result, it can be determined that the leakage position is the first storage cell 101 connected in the third case.

[0078] In summary, it can be concluded that the storage data of all the second storage cells 102 connected to the same complementary bit line 104 are different from the real data, and the storage data of a unique first storage cell 101 among the first storage cells 101 connected to the corresponding bit line 103 are different from the real data. The test result shows that the bit line 103 and the word line 105 connected to the unique first storage cell 101 are leaking.

[0079] The detection method of the memory provided in the present embodiment is that the storage data written into the first storage unit 101 connected to each bit line 103 and the second storage unit 102 connected to its corresponding complementary bit line 104 are the same. When reading, when the selected bit line 103 and the corresponding complementary bit line 104 are not leaking, the selected word line 105 is connected to one of the bit line 103 and the complementary bit line 104, and the result of reading is that the one not connected to the selected word line 105 is a logic high level; in this way, when the logic level of the read first storage unit 101 does not match the preset result, the influencing factor is the leakage current caused by the short circuit between the bit line 103 and the selected word line 105 or the leakage current caused by the short circuit between the corresponding complementary bit line 104 and a non-selected word line 105; when the logic level of the read second storage unit 102 does not match the preset result, the influencing factor is the leakage current caused by the short circuit between the bit line 103 and the selected word line 105 or the corresponding complementary bit line 104 and a non-selected word line 105; The selected word line 105 shorts the leakage current or the corresponding bit line 103 shorts the leakage current with a certain unselected word line 105, and all the word lines 105 are selected in sequence. Combined with the test results of all the first storage units 101 and the second storage units 102 connected to the bit line 103 and the corresponding complementary bit line 104, the exact position of the leakage current can be determined; by using this method to select all the word lines 105 in sequence, using the characteristic that when the logic levels of the bit line 103 and the corresponding complementary bit line 104 are the same, the selected word line 105 and the one that is not connected are the logic high level, without writing two logic levels in the first storage unit 101 and the second storage unit 102 respectively to compare the test results, the accurate position of the bit line 103 or the complementary bit line 104 of the leakage current can be obtained without omission based on one test result, thereby improving the detection efficiency of the memory detection method.

[0080] Another embodiment of the present invention provides a memory detection device corresponding to the memory detection method of the above embodiment. The memory detection device of this embodiment will be described in detail below with reference to the accompanying drawings.

[0081] refer to Figure 1 , memory 100, the memory 100 includes a plurality of first storage units 101, a plurality of second storage units 102, a plurality of mutually discrete bit lines 103, a plurality of mutually discrete complementary bit lines 104 and a plurality of mutually discrete word lines 105, each complementary bit line 104 corresponds to a bit line 103, the first storage unit 101 is connected to a corresponding bit line 103 and a word line 105, and the second storage unit 102 is connected to a corresponding complementary bit line 104 and a word line 105; the memory 100 also includes a plurality of sense amplifiers 106, each sense amplifier 106 is electrically coupled to a bit line 103 and a complementary bit line 104.

[0082] Figure 8 FIG. 4 is a schematic diagram of a module of a memory detection device in yet another embodiment of the present invention.

[0083] refer to Figure 1 and Figure 8 , a writing device 110, used for writing storage data into the first storage unit 101 and the second storage unit 102; a reading device 140, the reading device 140 is used for sequentially selecting all word lines 105 for reading, so as to read the real data in each first storage unit 101 and the second storage unit 102 through the bit line 103, the complementary bit line 104 and the sense amplifier 106; an instruction device 120, used for controlling the writing device 110 to write the same storage data into the first storage unit 101 connected to each bit line 103 and the second storage unit 102 connected to its corresponding complementary bit line 104; an error reporting device 150, the error reporting device 150 obtains the test result based on the difference between the real data and the storage data, and obtains the leakage position of the bit line 103 or the complementary bit line 104 and the word line 105 based on the test result corresponding to each first storage unit 101 and the second storage unit 102.

[0084] Specifically, in this embodiment, the error reporting device 150 includes a judgment device 151, which is used to judge the leakage position of the bit line 103 or the complementary bit line 104 and the word line 105 according to the test result. The error reporting device 150 also includes a response device 152, which is used to respond according to the judgment result of the judgment device 151.

[0085] In this embodiment, it also includes: a pre-charging device, which is used to pre-charge the bit line 103 and the corresponding complementary bit line 104, so that after the word line 105 is selected, the level of the pre-charged bit line 103 is the same as the level of the pre-charged complementary bit line 104. It also includes: an automatic refresh device, which is used to perform an automatic refresh operation on the first storage unit 101 and the second storage unit 102 at a fixed time.

[0086] In this embodiment, it also includes: an instruction decoder 130 for adjusting the type of storage data written by the writing device 110 to the first storage unit 101 and the second storage unit 102 according to the instruction issued by the instruction device 120.

[0087] The memory detection device provided in this embodiment writes the same storage data into the first storage unit 101 connected to each bit line 103 and the second storage unit 102 connected to its corresponding complementary bit line 104; thus, when the logic level of the read first storage unit 101 does not match the preset result, the influencing factor is the leakage current shorted between a bit line 103 and a selected word line 105 or the leakage current shorted between the corresponding complementary bit line 104 and a non-selected word line 105; when the logic level of the read second storage unit 102 does not match the preset result, the influencing factor is the leakage current shorted between a complementary bit line 104 and a selected word line 105 or the leakage current shorted between the corresponding bit line 103 and a non-selected word line 105, and the selected word line 105 is selected in sequence. By combining the test results of all the word lines 105 connected to the bit line 103 and the corresponding complementary bit line 104 with the test results of all the first storage cells 101 and the second storage cells 102, the exact position of the leakage current can be determined. By using this method to select all the word lines 105 in sequence, and utilizing the characteristics that when the logic levels of the bit line 103 and the corresponding complementary bit line 104 are the same, the word line 105 selected and whichever one is not connected is a logic high level, there is no need to write two logic levels into the first storage cell 101 and the second storage cell 102 respectively to compare the test results. The exact position of the bit line 103 or the complementary bit line 104 of the leakage current can be obtained without omission based on a single test result, thereby improving the detection efficiency of the memory detection method.

[0088] Those skilled in the art will appreciate that the above embodiments are specific examples of the present invention, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention, and therefore the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A method for detecting a memory, It is characterized in that include: The memory comprises a plurality of first memory cells, a plurality of second memory cells, a plurality of mutually separate bit lines, a plurality of mutually separate complementary bit lines and a plurality of mutually separate word lines, each of the complementary bit lines corresponds to a bit line, the first memory cells are connected to a corresponding bit line and a corresponding word line, and the second memory cells are connected to a corresponding complementary bit line and a corresponding word line; the memory further comprises a plurality of sense amplifiers, each of the sense amplifiers is electrically coupled to a bit line and a complementary bit line; Writing storage data into each of the first storage unit and the second storage unit, wherein the storage data in the first storage unit connected to each of the bit lines and the second storage unit connected to the corresponding complementary bit line are the same; After writing the storage data, performing a read operation, the read operation comprising: sequentially selecting all the word lines for reading, so as to read the real data in each of the first storage unit and the second storage unit through the bit line, the complementary bit line and the sense amplifier; Based on the difference between the real data and the stored data, obtaining a test result; Based on the test results corresponding to each of the first storage unit and the second storage unit, the leakage position of the bit line or the complementary bit line and the word line is obtained, specifically including: the storage data of all the second storage units connected to the same complementary bit line is different from the real data, and there is a unique first storage unit among the first storage units connected to the corresponding bit line, and the storage data is different from the real data, and the test result is the leakage of the bit line and the word line connected to the unique first storage unit.

2. The memory detection method according to claim 1, It is characterized in that The manner of writing the storage data into the first storage unit and the second storage unit includes: writing the same storage data into all the first storage units and the second storage units.

3. The memory detection method according to claim 2, It is characterized in that The storage data written into each of the first storage unit and the second storage unit is at a logic low level.

4. The memory detection method according to claim 1, It is characterized in that The method of writing the storage data into the first storage unit further includes: writing different storage data into a plurality of the first storage units connected to the adjacent bit lines.

5. The memory detection method according to claim 1, It is characterized in that The method of writing the storage data into the second storage unit further includes: writing different storage data into a plurality of the second storage units connected to the adjacent complementary bit lines.

6. The memory detection method according to claim 1, It is characterized in that After selecting one of the word lines, the method further includes: precharging the bit line and the corresponding complementary bit line, wherein the precharged bit line and the corresponding complementary bit line have the same level.

7. The memory detection method according to claim 1, It is characterized in that Before performing the reading operation, the method further includes: performing an automatic refresh operation on all the first storage units and the second storage units.

8. The memory detection method according to claim 1, It is characterized in that Before writing the storage data into each of the first storage unit and the second storage unit, the method further includes: performing an initialization operation on the first storage unit and the second storage unit to activate the first storage unit and the second storage unit.

9. The memory detection method according to claim 1, It is characterized in that The step of obtaining the leakage position of the bit line or the complementary bit line and the word line based on the test result corresponding to each of the first storage unit and the second storage unit specifically includes: The storage data of all the first storage cells connected to the same bit line are different from the real data, and the storage data of a unique second storage cell among the second storage cells connected to the corresponding complementary bit line are different from the real data, and the test result is that the complementary bit line and the word line connected to the unique second storage cell are leaking.

10. A memory detection device, It is characterized in that include: A memory, the memory comprising a plurality of first memory cells, a plurality of second memory cells, a plurality of mutually separate bit lines, a plurality of mutually separate complementary bit lines, and a plurality of mutually separate word lines, each of the complementary bit lines corresponds to a bit line, the first memory cells are connected to a corresponding bit line and a corresponding word line, and the second memory cells are connected to a corresponding complementary bit line and a corresponding word line; The memory further includes a plurality of sense amplifiers, each of the sense amplifiers being electrically coupled to one of the bit lines and one of the complementary bit lines; A writing device, used for writing storage data into the first storage unit and the second storage unit; A reading device, the reading device is used to sequentially select all the word lines for reading, so as to read the real data in each of the first storage unit and the second storage unit through the bit line, the complementary bit line and the sense amplifier; an instruction device, used for controlling the writing device to write the same storage data into the first storage unit connected to each of the bit lines and the second storage unit connected to the corresponding complementary bit line; An error reporting device, wherein the error reporting device obtains a test result based on the difference between the real data and the stored data, and obtains the leakage position of the bit line or the complementary bit line and the word line based on the test result corresponding to each of the first storage unit and the second storage unit, specifically comprising: the storage data of all the second storage units connected to the same complementary bit line are different from the real data, and the storage data of a unique first storage unit among the first storage units connected to the corresponding bit line are different from the real data, and the test result is that the bit line and the word line connected to the unique first storage unit are leaking.

11. The memory detection device according to claim 10, It is characterized in that Also includes: An instruction decoder is used to adjust the type of the storage data written by the writing device to the first storage unit and the second storage unit according to the instruction issued by the instruction device.

12. The memory detection device according to claim 10, It is characterized in that Also includes: A precharging device is used to precharge the bit line and the corresponding complementary bit line, so that after selecting one of the word lines, the level of the precharged bit line is the same as the level of the corresponding complementary bit line after precharging.

13. The memory detection device according to claim 10, It is characterized in that Also includes: The automatic refresh device is used for periodically performing automatic refresh operations on the first storage unit and the second storage unit.

14. The memory detection device according to claim 10, It is characterized in that Also includes: The error reporting device further comprises a judging device, and the judging device is used for judging the leakage position of the bit line or the complementary bit line and the word line according to the test result.

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