Background calibration method for analog-digital converter model and electronic device

Abstract

The present disclosure provides a background calibration method for an analog-digital converter model and an electronic device, which can be applied to the field of calibration technology. The method comprises: inputting a first output result of a to-be-calibrated analog-digital converter model in a current round and a second output result of a reference analog-digital converter model into a loss function to obtain a loss function value in the current round; determining a step size in the current round according to a loss function value in a previous round and the loss function value in the current round, wherein the loss function value in the previous round is obtained by inputting a first output result of a to-be-calibrated analog-digital converter model in the previous round and a second output result of a reference analog-digital converter model into a loss function; and calibrating first parameter information of the to-be-calibrated analog-digital converter model in the current round according to the step size in the current round and a set of learning factors.

Description

Technical Field

[0001] This disclosure relates to the field of calibration technology, and more particularly to a background calibration method and electronic device for an analog-to-digital converter model. Background Technology

[0002] Analog-to-digital converters (ADCs) connect the analog world and the digital world, converting analog signals from nature into visualized digital signals. They are an indispensable part of modern electronic products.

[0003] However, with the continuous advancement and development of science and technology, people have placed higher demands on the precision of various devices, and the demand for high-resolution ADCs is constantly increasing. While advanced processes have brought smaller area and lower power consumption to ADC designs, they have also reduced the operating power supply voltage, making ADCs more susceptible to interference. Especially for ultra-high-resolution ADCs used in advanced applications, error interference has a decisive impact on their performance; therefore, how to reduce ADC errors has become a research hotspot in recent years.

[0004] In related technologies, ADC background calibration methods can be used to reduce ADC errors. However, the calibration process of ADC background calibration methods is complex, resulting in a large amount of computation and a long calibration time. Summary of the Invention

[0005] In view of the above problems, this disclosure provides a background calibration method and electronic device for analog-to-digital converter models.

[0006] According to a first aspect of this disclosure, a background calibration method for an analog-to-digital converter (ADC) model is provided, comprising: inputting a first output result of the ADC model to be calibrated in the current round and a second output result of a reference ADC model into a loss function to obtain the loss function value for the current round, wherein the first output result represents the output result of a comparator in the ADC model to be calibrated, the second output result represents the output result of a comparator in the reference ADC model, the ADC model to be calibrated includes multiple cascaded ADCs, and each ADC includes a margin amplifier and a comparator. Based on the loss function value of the previous round and the loss function value of the current round, the step size of the current round is determined, wherein the loss function value of the previous round is obtained by inputting the first output result of the analog-to-digital converter model to be calibrated in the previous round and the second output result of the reference analog-to-digital converter model into the loss function; and based on the step size of the current round and the learning factor set, the first parameter information of the analog-to-digital converter model to be calibrated in the current round is calibrated, wherein the first parameter information includes the parameters of the margin amplifier and the parameters of the comparator, and the learning factor set includes multiple learning factors, each of which corresponds one-to-one with the analog-to-digital converter to be calibrated.

[0007] According to an embodiment of this disclosure, the aforementioned analog-to-digital converter model to be calibrated includes M cascaded analog-to-digital converters to be calibrated; the aforementioned first output result includes M third output results at multiple time points, and the aforementioned second output result includes M fourth output results at multiple time points, where M is an integer greater than or equal to 1; the aforementioned loss function value characterizes the average value of the differences between the multiple third output results and the multiple fourth output results.

[0008] According to an embodiment of this disclosure, the third output result of the m-th stage is obtained by processing the output result of the margin amplifier in the (m-1)-th stage analog-to-digital converter to be calibrated using the m-th stage analog-to-digital converter to be calibrated, where m is an integer greater than or equal to 1 and less than or equal to M.

[0009] According to an embodiment of this disclosure, determining the step size of the current round based on the loss function value of the previous round and the loss function value of the current round includes: determining the difference between the loss function value of the current round and the loss function value of the previous round; and determining the step size of the current round based on the loss function value of the current round and the difference between the loss function value of the current round and the loss function value of the previous round.

[0010] According to an embodiment of this disclosure, calibrating the first parameter information of the analog-to-digital converter model to be calibrated in the current round based on the step size and learning factor set of the current round includes: determining the product between the step size of the current round and the learning factor corresponding to each level of the analog-to-digital converter to be calibrated in the model; and calibrating the first parameter information of the analog-to-digital converter to be calibrated in the current round based on the product.

[0011] According to embodiments of this disclosure, the aforementioned analog-to-digital converter to be calibrated further includes an operational amplifier; the aforementioned background calibration method for the analog-to-digital converter model further includes: inputting the loss function value of the current round, the sampling quantization information of the aforementioned analog-to-digital converter model to be calibrated, and the sampling quantization information of the aforementioned reference analog-to-digital converter model into a learning logic model to obtain the model output value of the current round; and calibrating the second parameter information of the aforementioned analog-to-digital converter model to be calibrated based on the model output value of the current round, wherein the second parameter information includes the comparator threshold of the aforementioned comparator and the operational amplifier gain of the aforementioned operational amplifier.

[0012] According to embodiments of this disclosure, calibrating the second parameter information of the analog-to-digital converter model to be calibrated based on the model output value of the current round includes repeatedly performing the following operations until the termination condition is met: if it is determined that the termination condition is not met, updating the current positions of the plurality of traction particles according to their respective current fitness function values, wherein the particle swarm also includes a plurality of ordinary particles, wherein the traction particles represent the operational amplifier gain and the ordinary particles represent the comparator threshold; if it is determined that the updated current positions of the traction particles have not changed, adjusting the current fitness function values ​​of the plurality of traction particles and the plurality of ordinary particles according to their respective current fitness function values. The local optimal positions of the plurality of traction particles and the plurality of ordinary particles are updated based on the degree function value. The local optimal position of the traction particle represents the local optimal operational amplifier gain of the traction particle, and the local optimal position of the ordinary particle represents the local optimal comparator threshold of the ordinary particle. Based on the updated local optimal positions of the plurality of traction particles and the plurality of ordinary particles, the global optimal position of the particle swarm is updated. The global optimal position obtained under the condition of satisfying the above termination is determined as the target second parameter information of the analog-to-digital converter model to be calibrated. The target second parameter information includes the global optimal comparator threshold and the global optimal operational amplifier gain.

[0013] According to embodiments of this disclosure, the above-described background calibration method for an analog-to-digital converter model further includes: constructing the analog-to-digital converter model to be calibrated based on the error information of the actual analog-to-digital converter.

[0014] According to embodiments of this disclosure, the error information mentioned above includes at least one of the following: clock jitter error, switching thermal noise, comparator offset, capacitor mismatch, op-amp finite gain, and op-amp parasitic capacitance.

[0015] A second aspect of this disclosure provides a background calibration apparatus for an analog-to-digital converter (ADC) model, comprising: a first acquisition module, a determination module, and a first calibration module. The first acquisition module is configured to input a first output result of the ADC model to be calibrated in the current round and a second output result of a reference ADC model into a loss function to obtain the loss function value for the current round. The first output result represents the output result of a comparator in the ADC model to be calibrated, and the second output result represents the output result of a comparator in the reference ADC model. The ADC model to be calibrated includes multiple cascaded ADCs, each including a margin amplifier and a comparator. The determination module is configured to determine the step size for the current round based on the loss function value from the previous round and the loss function value for the current round. The loss function value from the previous round is obtained by inputting the first output result of the ADC model to be calibrated in the previous round and the second output result of the reference ADC model into the loss function. The first calibration module is used to calibrate the first parameter information of the analog-to-digital converter model to be calibrated in the current round according to the step size and learning factor set of the current round. The first parameter information includes the parameters of the margin amplifier and the parameters of the comparator. The learning factor set includes multiple learning factors, and each learning factor corresponds one-to-one with the analog-to-digital converter to be calibrated.

[0016] A third aspect of this disclosure provides an electronic device comprising: one or more processors; and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors perform the methods described above.

[0017] A fourth aspect of this disclosure also provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the methods described above.

[0018] The fifth aspect of this disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0019] According to embodiments of this disclosure, a loss function is used to determine the value of the loss function, and the step size is determined based on the loss function value. The larger the step size, the greater the degree of error calibration required in the analog-to-digital converter model to be calibrated. Finally, based on the step size and the learning factor, the margin amplifier parameters and comparator parameters that need to be calibrated in the analog-to-digital converter model to be calibrated are determined. When the error is large, a larger step size results in a greater degree of error calibration, solving the problems of large computational load and long calibration time during the calibration process, and achieving rapid convergence of the calibration process. Attached Figure Description

[0020] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0021] Figure 1 The illustration schematically depicts an application scenario of a background calibration method, apparatus, device, medium, and program product for an analog-to-digital converter model according to embodiments of the present disclosure;

[0022] Figure 2 The basic architecture of a pipelined analog-to-digital converter model according to an embodiment of the present disclosure is illustrated schematically.

[0023] Figure 3 A flowchart illustrating a background calibration method for an analog-to-digital converter model according to an embodiment of the present disclosure is shown schematically.

[0024] Figure 4 A flowchart illustrating the determination of the step size of the current round according to an embodiment of the present disclosure is shown schematically.

[0025] Figure 5 A flowchart illustrating the first parameter information of the analog-to-digital converter model to be calibrated for the current round is shown schematically according to an embodiment of the present disclosure.

[0026] Figure 6 The overall architecture of a supervised learning-based analog-to-digital converter digital back-end calibration algorithm according to an embodiment of the present disclosure is illustrated schematically.

[0027] Figure 7 A flowchart illustrating second parameter information of an analog-to-digital converter model to be calibrated according to an embodiment of the present disclosure is shown schematically.

[0028] Figure 8 This schematically illustrates a process diagram for calibrating the second parameter information of an analog-to-digital converter model to be calibrated according to an embodiment of the present disclosure;

[0029] Figure 9 The basic structure of each stage of the analog-to-digital converter in the model to be calibrated according to an embodiment of the present disclosure is schematically shown;

[0030] Figure 10(a) schematically illustrates the spectral changes of a 14-bit pipelined analog-to-digital converter model based on a traction-driven particle swarm optimization algorithm according to an embodiment of the present disclosure before and after calibration.

[0031] Figure 10(b) schematically illustrates the DNL (Differential Nonlinearity) plot of a 14-bit pipelined analog-to-digital converter model calibrated according to an embodiment of the present disclosure based on a traction-based particle swarm optimization algorithm;

[0032] Figure 10(c) schematically shows the INL (integral nonlinearity) plot of a 14-bit pipeline analog-to-digital converter model based on a traction-driven particle swarm optimization algorithm according to an embodiment of the present disclosure before calibration.

[0033] Figure 11(a) schematically illustrates the variation of a portion of the comparator loss function during calibration of a 14-bit pipelined analog-to-digital converter model according to an embodiment of the present disclosure;

[0034] Figure 11(b) schematically illustrates the spectrum changes of a 14-bit pipelined analog-to-digital converter model before and after calibration according to an embodiment of the present disclosure;

[0035] Figure 11(c) schematically illustrates a DNL (Differential Nonlinearity) plot of a 14-bit pipelined analog-to-digital converter model calibrated according to an embodiment of the present disclosure;

[0036] Figure 11(d) schematically illustrates the INL (integral nonlinearity) plot of a 14-bit pipelined analog-to-digital converter model before calibration according to an embodiment of the present disclosure;

[0037] Figure 12 The diagram illustrates a real-world test of card issuance according to an embodiment of this disclosure.

[0038] Figure 13 A schematic block diagram of a background calibration apparatus for an analog-to-digital converter model according to an embodiment of the present disclosure is shown; and

[0039] Figure 14 A block diagram schematically illustrates an electronic device suitable for implementing a background calibration method for an analog-to-digital converter model according to an embodiment of the present disclosure. Detailed Implementation

[0040] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0042] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0043] When using expressions such as "at least one of A, B, and C", they should generally be interpreted in accordance with the meaning that is commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc.).

[0044] In implementing this disclosure, it was discovered that ADC errors are typically compensated for using digital calibration methods, which are generally divided into foreground calibration and background calibration. Foreground calibration usually requires interrupting the ADC's operation, while background calibration can perform real-time calibration in the background without interrupting the ADC's operation. Therefore, foreground calibration is generally used before the ADC is powered on, while background calibration is commonly used during ADC operation. Thus, background calibration can be used to reduce ADC errors. However, in related technologies, the background calibration process is complex, resulting in a large computational load and a long calibration time.

[0045] Therefore, embodiments of this disclosure provide a background calibration method for an analog-to-digital converter (ADC) model, comprising: inputting a first output result of the ADC model to be calibrated in the current round and a second output result of a reference ADC model into a loss function to obtain the loss function value for the current round, wherein the first output result can characterize the output result of the comparator in the ADC model to be calibrated, and the second output result can characterize the output result of the comparator in the reference ADC model. The ADC model to be calibrated may include multiple cascaded ADCs, and the ADCs may include margin amplifiers. The system includes a comparator and a margin amplifier. Based on the loss function values ​​from the previous and current rounds, the step size for the current round is determined. The loss function value from the previous round can be obtained by inputting the first output of the analog-to-digital converter (ADC) model to be calibrated from the previous round and the second output of the reference ADC model into the loss function. Based on the step size and the learning factor set, the first parameter information of the ADC model to be calibrated in the current round is calibrated. The first parameter information may include the parameters of the margin amplifier and the comparator. The learning factor set may include multiple learning factors, each corresponding one-to-one with the ADC model to be calibrated.

[0046] Figure 1 The diagram illustrates an application scenario of a background calibration method for an analog-to-digital converter model according to an embodiment of the present disclosure.

[0047] like Figure 1 As shown, application scenario 100 according to this embodiment may include terminal devices 101, 102, and 103, network 104, and server 105. Network 104 is used as a medium to provide a communication link between terminal devices 101, 102, and 103 and server 105. Network 104 may include various connection types, such as wired or wireless communication links or fiber optic cables, etc.

[0048] Users can use terminal devices 101, 102, and 103 to interact with server 105 via network 104 to receive or send messages, etc. Various communication client applications can be installed on terminal devices 101, 102, and 103, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, social media platform software, etc. (for example only).

[0049] Terminal devices 101, 102, and 103 can be various electronic devices with displays and web browsing capabilities, including but not limited to smartphones, tablets, laptops, and desktop computers.

[0050] For example, the model of the analog-to-digital converter to be calibrated can be constructed using terminal devices 101, 102, and 103 based on the error information of the actual analog-to-digital converter.

[0051] Server 105 can be a server that provides various services, such as a backend management server that supports websites browsed by users using terminal devices 101, 102, and 103 (for example only). The backend management server can analyze and process data such as received user requests, and feed back the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal devices.

[0052] For example, the server 105 can input the first output of the analog-to-digital converter model to be calibrated in the current round and the second output of the reference analog-to-digital converter model into the loss function to obtain the loss function value of the current round. Based on the loss function value of the previous round and the loss function value of the current round, the step size of the current round is determined. Thus, based on the step size of the current round and the learning factor set, the first parameter information of the analog-to-digital converter model to be calibrated in the current round is calibrated.

[0053] It should be noted that the background calibration method for the analog-to-digital converter model provided in this disclosure embodiment can generally be executed by server 105. Correspondingly, the background calibration device for the analog-to-digital converter model provided in this disclosure embodiment can generally be located in server 105. The background calibration method for the analog-to-digital converter model provided in this disclosure embodiment can also be executed by a server or server cluster that is different from server 105 and capable of communicating with terminal devices 101, 102, 103 and / or server 105. Correspondingly, the background calibration device for the analog-to-digital converter model provided in this disclosure embodiment can also be located in a server or server cluster that is different from server 105 and capable of communicating with terminal devices 101, 102, 103 and / or server 105.

[0054] It should be understood that Figure 1 The number of terminal devices, networks, and servers shown is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, and servers can be included.

[0055] The following will be based on Figure 1 The described scene, through Figures 2 to 12 The background calibration method for an analog-to-digital converter model according to the disclosed embodiments is described in detail.

[0056] Figure 2 The basic architecture of a pipelined analog-to-digital converter model according to an embodiment of the present disclosure is illustrated schematically.

[0057] like Figure 2As shown, in 200, the analog-to-digital converter (ADC) model 201 to be calibrated can be a pipelined ADC model. The pipelined ADC model 201 can include M cascaded ADCs to be calibrated. For example, ADCs to be calibrated 201_1, ADCs to be calibrated 201_2, ADCs to be calibrated 201_m, ..., ADCs to be calibrated 201_M. ADC 201_m can include a comparator 201_m_1 and a margin amplifier 201_m_2. M can be an integer greater than or equal to 1. m can be an integer greater than or equal to 1 and less than or equal to M.

[0058] Figure 3 A flowchart illustrating a background calibration method for an analog-to-digital converter model according to an embodiment of the present disclosure is shown.

[0059] like Figure 3 As shown, the method 300 includes operations S310 to S330.

[0060] In operation S310, the first output of the analog-to-digital converter model to be calibrated in the current round and the second output of the reference analog-to-digital converter model are input into the loss function to obtain the loss function value for the current round.

[0061] According to embodiments of this disclosure, a first output result can characterize the output result of the comparator in the analog-to-digital converter model to be calibrated. A second output result can characterize the output result of the comparator in the reference analog-to-digital converter model. The analog-to-digital converter model to be calibrated may include multiple cascaded analog-to-digital converters to be calibrated. The analog-to-digital converters to be calibrated may include a margin amplifier and a comparator.

[0062] According to embodiments of this disclosure, the analog-to-digital converter (ADC) model to be calibrated may include an ADC model with errors. The ADC model to be calibrated may be based on a reference ADC model.

[0063] According to embodiments of this disclosure, the loss function may be determined based on the output of the comparator in the analog-to-digital converter model to be calibrated and the output of the comparator in the reference analog-to-digital converter model.

[0064] In operation S320, the step size of the current round is determined based on the loss function value of the previous round and the loss function value of the current round.

[0065] According to embodiments of this disclosure, the loss function value of the previous round can be obtained by inputting the first output result of the analog-to-digital converter model to be calibrated in the previous round and the second output result of the reference analog-to-digital converter model into the loss function.

[0066] According to embodiments of this disclosure, the step size of the current round is determined based on the difference between the loss function value of the previous round and the loss function value of the current round. Alternatively, the difference between the loss function value of the current round and the loss function value of the previous round is determined. The step size of the current round is determined based on the loss function value of the current round and the difference between the loss function value of the current round and the loss function value of the previous round.

[0067] In operation S330, the first parameter information of the analog-to-digital converter model to be calibrated in the current round is calibrated according to the step size and learning factor set of the current round.

[0068] According to embodiments of this disclosure, the first parameter information may include parameters of the margin amplifier and parameters of the comparator. The learning factor set may include multiple learning factors. Each learning factor corresponds one-to-one with the analog-to-digital converter to be calibrated.

[0069] According to embodiments of this disclosure, when each stage of the analog-to-digital converter model to be calibrated is adjusted by the same amount, its influence will decrease with each stage, with a larger influence in the earlier stages and a smaller influence in the later stages. Therefore, a small learning factor is set for the earlier stages and a large learning factor is set for the later stages.

[0070] According to embodiments of this disclosure, the product of the step size of the current round and the learning factor of each stage of the analog-to-digital converter (ADC) in the ADC model to be calibrated is determined. Based on the product of this product and the corresponding control factor, the margin amplifier parameters and comparator parameters in the ADC model to be calibrated in the current round are calibrated. Alternatively, the product between the step size of the current round and the learning factor corresponding to each stage of the ADC in the ADC model to be calibrated is determined. Based on the product, the first parameter information in the ADC to be calibrated in the current round is calibrated.

[0071] According to embodiments of this disclosure, a loss function is used to determine the value of the loss function, and the step size is determined based on the loss function value. The larger the step size, the greater the degree of error calibration required in the analog-to-digital converter model to be calibrated. Finally, based on the step size and the learning factor, the margin amplifier parameters and comparator parameters that need to be calibrated in the analog-to-digital converter model to be calibrated are determined. When the error is large, a larger step size results in a greater degree of error calibration, solving the problems of large computational load and long calibration time during the calibration process, and achieving rapid convergence of the calibration process.

[0072] According to embodiments of this disclosure, the analog-to-digital converter model to be calibrated may include M cascaded analog-to-digital converters to be calibrated. The first output result may include M third output results at multiple time points, and the second output result may include M fourth output results at multiple time points, where M is an integer greater than or equal to 1. The loss function value can characterize the average of the differences between the multiple third output results and the multiple fourth output results.

[0073] According to embodiments of this disclosure, the multiple time points may include N time points. For the nth time point, the m-th stage analog-to-digital converter to be calibrated has a corresponding third output result. The m-th stage reference analog-to-digital converter has a corresponding fourth output result. N can be an integer greater than 1. n is an integer greater than or equal to 1 and less than or equal to N.

[0074] According to embodiments of this disclosure, at time n, the difference between the third output of the m-th stage analog-to-digital converter to be calibrated and the fourth output of the m-th stage reference analog-to-digital converter can be determined to obtain the difference at time n for the m-th stage. The average of the M×N differences is then determined to obtain the loss function value.

[0075] According to embodiments of this disclosure, the loss function value is determined based on the average of the differences between multiple third output results and multiple fourth output results, thereby improving the accuracy of the loss function value.

[0076] According to an embodiment of this disclosure, the third output result of the m-th stage is obtained by processing the output result of the margin amplifier in the (m-1)-th stage analog-to-digital converter to be calibrated using the m-th stage analog-to-digital converter to be calibrated, where m is an integer greater than or equal to 1 and less than or equal to M.

[0077] According to embodiments of this disclosure, the adjustment result of the margin amplifier will affect the subsequent stage signal. Therefore, the third output result of the m-th stage is obtained by processing the output result of the margin amplifier in the (m-1)-th stage analog-to-digital converter to be calibrated using the m-th stage analog-to-digital converter to be calibrated, which can reduce the amount of calculation in the calibration process.

[0078] Figure 4 A flowchart illustrating the determination of the step size of the current round according to an embodiment of the present disclosure is shown schematically.

[0079] like Figure 4 As shown, the method 400 includes operations S410 to S420.

[0080] In operation S410, the difference between the loss function value of the current round and the loss function value of the previous round is determined.

[0081] According to embodiments of this disclosure, the loss function value can be the average of the differences between the comparator outputs of the M cascaded analog-to-digital converters to be calibrated in the model to be calibrated and the comparator outputs of the M cascaded reference analog-to-digital converters in the model to be calibrated.

[0082] According to embodiments of this disclosure, the loss function can be expressed as the following formula (1).

[0083]

[0084] Where H(t) can represent the length of the sampling time series; V x It can represent the input signal; V c It can represent the comparator output of a reference analog-to-digital converter model; V d It can represent the comparator output of the analog-to-digital converter model to be calibrated; s~H can represent the number of samples.

[0085] In operation S420, the step size of the current round is determined based on the loss function value of the current round and the difference between the loss function value of the current round and the loss function value of the previous round.

[0086] According to embodiments of this disclosure, the step size of the current round is the product of the loss function value of the current round and the corresponding control factor, and the sum of the product of the difference between the loss function value of the current round and the loss function value of the previous round and the corresponding control factor.

[0087] According to embodiments of this disclosure, the step size is determined based on the magnitude and change of the loss function value. The step size increases as the loss function value or its gradient increases. The expression for determining the step size for the current iteration can be represented by the following formula (2).

[0088] Stp e =αE e +β(E e -E e-1 (2)

[0089] Among them, Step e E can represent the step size of the current round. e E can represent the loss function value of the current round. e-1 This can represent the loss function value from the previous round. α and β can represent control factors, which need to be adjusted in different working environments.

[0090] According to embodiments of this disclosure, the step size of the current round can be determined based on the loss function value of the current round and the difference between the loss function value of the current round and the loss function value of the previous round. If the step size of the current round is smaller than the step size of the previous round, it can be determined that the calibration of the previous round reduced the error of the analog-to-digital converter model to be calibrated.

[0091] Figure 5 A flowchart illustrating the first parameter information of the analog-to-digital converter model to be calibrated for the current cycle is shown schematically according to an embodiment of the present disclosure.

[0092] like Figure 5 As shown, the method 500 includes operations S510 to S520.

[0093] In operation S510, the step size of the current round is determined and multiplied with the learning factor corresponding to each stage of the analog-to-digital converter to be calibrated in the model to be calibrated.

[0094] According to an embodiment of this disclosure, the step size of the current round is multiplied by the learning factor corresponding to each stage of the analog-to-digital converter to be calibrated in the model to be calibrated, and then multiplied by the corresponding control factor to obtain a product for calibrating the first parameter information in the analog-to-digital converter to be calibrated in the current round.

[0095] According to embodiments of this disclosure, the expression for determining the product between the step size of the current round and the learning factor corresponding to each level of the analog-to-digital converter to be calibrated in the model to be calibrated can be expressed as the following formula (3).

[0096] A = γ(Learning Factor × Step) e (3)

[0097] Where A can represent product, Step e It can represent the step size of the current round, and γ can represent the control factor.

[0098] In operation S520, the first parameter information in the analog-to-digital converter to be calibrated in the current round is calibrated based on the product.

[0099] According to the embodiments of this disclosure, the larger the step size, the greater the degree of error calibration required in the analog-to-digital converter model to be calibrated. Finally, based on the product of the step size and the learning factor, the margin amplifier parameters and comparator parameters that need to be calibrated in the analog-to-digital converter model to be calibrated are determined. When the error is large, the larger the step size, the greater the degree of error calibration. This solves the problems of large computational load and long calibration time during the calibration process, and achieves rapid convergence of the calibration process.

[0100] According to embodiments of this disclosure, the analog-to-digital converter to be calibrated may further include an operational amplifier.

[0101] The aforementioned background calibration method for analog-to-digital converter (ADC) models further includes: inputting the loss function value of the current round, the sampling quantization information of the ADC model to be calibrated, and the sampling quantization information of the reference ADC model into the learning logic model to obtain the model output value of the current round; and calibrating the second parameter information of the ADC model to be calibrated based on the model output value of the current round.

[0102] According to embodiments of this disclosure, the second parameter information may include the comparator threshold of the comparator and the operational amplifier gain. The sampled quantization information can characterize the quantization output result.

[0103] According to embodiments of this disclosure, by calibrating the comparator threshold of the comparator and the operational amplifier gain of the operational amplifier of the analog-to-digital converter model to be calibrated based on the output value of the learning logic model in the current round, high calibration accuracy can be guaranteed.

[0104] Figure 6 The overall architecture of a supervised learning-based analog-to-digital converter digital back-end calibration algorithm according to an embodiment of the present disclosure is illustrated schematically.

[0105] According to embodiments of this disclosure, the overall architecture 600 of the supervised learning-based analog-to-digital converter (ADC) digital back-end calibration algorithm may include a reference ADC model 601, an ADC model to be calibrated 602, a loss function model 603, a frequency reduction model 604, and a learning logic model 605.

[0106] According to an embodiment of this disclosure, in this architecture, input signals are respectively input to a reference analog-to-digital converter (ADC) model 601 and an ADC model 602 to be calibrated, and then the comparator outputs of the reference ADC model 601 and the ADC model 602 to be calibrated are output. Then, based on the comparator outputs in the reference ADC model 601 and the comparator outputs in the ADC model 602 to be calibrated, a loss function value is obtained through a loss function model 603.

[0107] According to an embodiment of this disclosure, the quantized output of the analog-to-digital converter model 602 to be calibrated is processed by a frequency reduction model 604, and then input into a learning logic model 605 along with the quantized output of a reference analog-to-digital converter model 601 and the loss function value to obtain second parameter information for calibrating the analog-to-digital converter model 602 to be calibrated.

[0108] According to embodiments of this disclosure, the analog-to-digital converter model can be a P-bit resolution analog-to-digital converter. The P-bit resolution can be decomposed into M levels. Each level of the analog-to-digital converter can correspond to P / M bits. Quantization is gradually achieved by performing pursuit processing on the input signal, and finally, all quantized bits are combined to achieve quantization, resulting in a quantized output.

[0109] According to an embodiment of this disclosure, the obtained second parameter information is used to calibrate the second parameter information in the analog-to-digital converter model 602 to be calibrated.

[0110] Figure 7 A flowchart illustrating the second parameter information of the analog-to-digital converter model to be calibrated according to an embodiment of the present disclosure is shown.

[0111] In operation S710, is the termination condition met? If yes, then execute operation S760; otherwise, execute operations S720 to S750.

[0112] According to embodiments of this disclosure, the termination condition may include the maximum number of iterations.

[0113] In operation S720, the current positions of multiple traction particles are updated based on their respective current fitness function values.

[0114] According to embodiments of this disclosure, the particle swarm may further include multiple ordinary particles, wherein the traction particles can characterize the operational amplifier gain, and the ordinary particles can characterize the comparator threshold.

[0115] According to embodiments of this disclosure, the traction-based particle swarm optimization algorithm is actually a multi-domain, multi-particle particle swarm optimization algorithm with interconnections. Different particles search for optimal solutions in different spaces, but the behavior of some particles can affect the behavior of particles in other domains.

[0116] According to embodiments of this disclosure, it is assumed that in a one-dimensional search space, there are Q different domains that simultaneously achieve optimization. The position variables of all particles in the k-th step can be expressed as follows (4).

[0117]

[0118] Where 'a' can represent the position of the tractor particle, and 'x' can represent the velocity of the ordinary particle. 2i (k) can represent the position of the i-th particle in the second domain.

[0119] The velocity vector can be expressed as follows (5).

[0120]

[0121] Where b can represent the velocity of the tractor particle, b can represent the velocity of the ordinary particle, and v 2i () can represent the velocity of the i-th particle in the second domain.

[0122] In operation S730, is the updated current position of the traction particle unchanged? If yes, then execute operation S740; otherwise, execute the return operation S710.

[0123] In operation S740, the local optimal positions of the multiple traction particles and multiple ordinary particles are updated according to their current fitness function values.

[0124] According to embodiments of this disclosure, the local optimal position of the traction particle can characterize the local optimal operational amplifier gain of the traction particle, and the local optimal position of the ordinary particle can characterize the local optimal comparator threshold of the ordinary particle.

[0125] According to embodiments of this disclosure, the Pbest variable searched by these particles can be expressed as the following formula (6).

[0126]

[0127] Where P(k) can represent the local optimal position of all particles in the k-th step, c can represent the local optimal position of the traction particle, and p can represent the local optimal position of the ordinary particle. 2i (k) can represent the local optimal position of the i-th particle in the second domain.

[0128] In operation S750, based on the updated local optimal positions of the multiple traction particles and the multiple ordinary particles, the global optimal position of the particle swarm is updated, and operation S710 is returned to be executed.

[0129] According to embodiments of this disclosure, the Gbest found in the example group can be represented as the following formula (7).

[0130]

[0131] Where G(k) represents the global optimal position of the particle swarm at step k, d represents the global optimal position of the traction particle, and g represents the global optimal position of the ordinary particle. 2i (k) can represent the global optimal position of the i-th particle in the second domain.

[0132] When operating S760, the globally optimal position obtained under the condition of meeting the termination criteria will be determined as the target second parameter information of the analog-to-digital converter model to be calibrated.

[0133] According to embodiments of this disclosure, the target second parameter information may include the globally optimal comparator threshold and the globally optimal operational amplifier gain.

[0134] According to embodiments of this disclosure, the above discussion is conducted in a one-dimensional search space, but it can still be reasonably generalized to multi-dimensional spaces. In the traction-based particle swarm optimization algorithm, particles adjust their velocity and position as shown in formula (8).

[0135]

[0136] Where i (i = 1, 2, 3, ..., m) can represent the i-th particle in the particle swarm, m can represent the total number of particles in the particle swarm, h (h = 1, 2, 3, ..., Q) can represent the h-th neighborhood of the particle, v hi (k) can represent the velocity of the i-th particle in the h-th region, x hi (k) can represent the position of the i-th particle in the h-th neighborhood, p hi (k) can represent the local optimal position of the i-th particle in the h-th neighborhood, g hi (k) can represent the global optimal position of the i-th particle in the h-th domain, c1 and c2 can represent learning factors, and r1 and r2 can represent random numbers between (0, 1).

[0137] According to embodiments of this disclosure, the inertia weight can be expressed as the following formula (9).

[0138]

[0139] Here, W represents the inertia weight, which determines whether the effect of the previous change should be retained. When the position of the traction particle changes, the weight disappears. When the position of the traction particle remains unchanged, the weight decreases linearly.

[0140] According to an embodiment of this disclosure, the update of the position of the i-th particle in the h-th field at step k+1 can be expressed as the following formula (10).

[0141] x hi (k+1)=x hi (k)+v hi (k+1) (10)

[0142] Where, x hi (k+1) can represent the update of the position of the i-th particle in the h-th neighborhood at step k+1, v hi (k+1) can represent the velocity of the i-th particle in the h-th field at step k+1.

[0143] According to embodiments of this disclosure, a globally optimal comparator threshold and a globally optimal operational amplifier gain are obtained using a tractor-driven particle swarm optimization algorithm, which are then used to calibrate the second parameter information of the analog-to-digital converter (ADC) model to be calibrated. Utilizing the tractor-driven particle swarm optimization algorithm reduces the time required to obtain the second parameter information from the loss function value, the sampled quantization information of the ADC model to be calibrated, and the sampled quantization information of the reference ADC model, thereby improving the convergence speed of the calibration and ensuring high calibration accuracy.

[0144] Figure 8 The diagram schematically illustrates the process of calibrating the second parameter information of an analog-to-digital converter model to be calibrated according to an embodiment of the present disclosure.

[0145] According to embodiments of this disclosure, the optimal solution for each comparator stage is driven by the operational amplifier of the preceding stage.

[0146] Figure 9 The schematic diagram illustrates the basic structure of each stage of the analog-to-digital converter in the model to be calibrated according to an embodiment of the present disclosure.

[0147] According to embodiments of this disclosure, the basic structure 800 of each stage of the analog-to-digital converter model to be calibrated may further include a sub-analog-to-digital converter 801, a sub-digital-to-analog converter, a comparator 803, and a margin amplifier 804.

[0148] According to embodiments of this disclosure, a change in the operational amplifier gain of each stage leads to a change in the quantization output of the subsequent sub-analog-to-digital converter. The optimal solution of each comparator stage is influenced by the operational amplifier of the preceding stage; therefore, after a change in the operational amplifier gain, the position of the optimal solution of the comparator threshold in the subsequent stage also changes accordingly.

[0149] According to embodiments of this disclosure, the above-described background calibration method for an analog-to-digital converter model may further include: constructing an analog-to-digital converter model to be calibrated based on error information of the actual analog-to-digital converter.

[0150] According to embodiments of this disclosure, an analog-to-digital converter model to be calibrated is constructed based on the error information of the actual analog-to-digital converter. This model can simultaneously calibrate different errors in the analog-to-digital converter, achieving accurate modeling that is closer to the analog-to-digital converter in actual experiments.

[0151] According to embodiments of this disclosure, error information may include at least one of the following: clock jitter error, switching thermal noise, comparator offset, capacitor mismatch, op-amp finite gain, and op-amp parasitic capacitance.

[0152] According to an embodiment of this disclosure, the peak value of the clock jitter error can be expressed as the following formula (11).

[0153]

[0154] Where S can represent signal power, and SNR can represent the total signal-to-noise ratio. low f0 can represent the low-frequency signal-to-noise ratio, and f0 can represent the input signal frequency. rmss It can represent the root mean square of the signal amplitude.

[0155] According to an embodiment of this disclosure, the power of the switching thermal noise can be expressed as the following formula (12).

[0156]

[0157] in, Let represent the noise power at level n, k represent the Boltzmann constant, T represent the Kelvin temperature, β represent the feedback coefficient, G represent the gain, and C represent the noise level at level n. s It can represent the sampling capacitance.

[0158] According to embodiments of this disclosure, since the capacitor mismatch and comparator offset are process-related, the capacitor mismatch and comparator offset are respectively added with a random mismatch with a peak value of 5% and a random offset with a peak value of 1 / 2 LSB, respectively, in consideration of the effectiveness of the calibration algorithm, as expressed in the following formula (13) and the following formula (14).

[0159] C = C u ±rand(0,5%)*C u (13)

[0160]

[0161] Among them, C u It can represent unit capacitance, V th0 This can represent the initial comparator threshold. A finite open-loop gain of 100dB and parasitic capacitance error are added to the operational amplifier. C can represent the capacitance considering capacitance mismatch, and V... th This can represent the comparator threshold that takes into account the comparator offset.

[0162] According to embodiments of this disclosure, by incorporating error information such as clock jitter, switching thermal noise, comparator offset, capacitor mismatch, operational amplifier finite gain, and operational amplifier parasitic capacitance into the modeling, accurate modeling can be achieved, which is closer to the analog-to-digital converter in actual experiments.

[0163] Figure 10(a) schematically illustrates the spectral changes of a 14-bit pipelined analog-to-digital converter model based on a traction-driven particle swarm optimization algorithm according to an embodiment of the present disclosure before and after calibration.

[0164] According to embodiments of this disclosure, the image shows the spectral changes before and after calibration. After calibration, the signal-to-noise ratio and spurious-free dynamic range of the ADC are effectively improved, and the ADC noise floor is significantly reduced.

[0165] Figure 10(b) schematically illustrates the DNL (Differential Nonlinearity) plot of a 14-bit pipelined analog-to-digital converter model calibrated according to an embodiment of the present disclosure based on a traction-based particle swarm optimization algorithm.

[0166] According to embodiments of this disclosure, as can be seen from the image, the calibrated differential nonlinearity is less than 1 LSB. Since the differential nonlinearity of the ADC after calibration is no greater than 1 LSB, misalignment calibration can be achieved.

[0167] Figure 10(c) schematically illustrates the INL (integral nonlinearity) plot of a 14-bit pipelined analog-to-digital converter model calibrated according to an embodiment of the present disclosure based on a traction-based particle swarm optimization algorithm.

[0168] According to embodiments of this disclosure, as can be seen from the images, the calibrated integral nonlinearity is less than 1 LSB, and the ADC calibration can achieve a non-cumulative error of less than 1 LSB.

[0169] Figure 11(a) schematically illustrates the variation of a portion of the comparator loss function during calibration of a 14-bit pipelined analog-to-digital converter model according to an embodiment of the present disclosure.

[0170] According to embodiments of this disclosure, the error of some comparators can be seen from the images, and these comparators achieve effective convergence within 1500 sampling points.

[0171] Figure 11(b) schematically illustrates the spectral changes of a 14-bit pipelined analog-to-digital converter model before and after calibration according to an embodiment of the present disclosure.

[0172] According to embodiments of this disclosure, the image shows the spectral changes before and after calibration. After calibration, the signal-to-noise ratio and spurious-free dynamic range of the ADC are effectively improved, and the ADC noise floor is significantly reduced.

[0173] Figure 11(c) schematically illustrates the DNL (Differential Nonlinearity) plot of a 14-bit pipelined analog-to-digital converter model calibrated according to an embodiment of the present disclosure.

[0174] According to embodiments of this disclosure, as can be seen from the image, the calibrated differential nonlinearity is less than 1 LSB. Since the differential nonlinearity of the ADC after calibration is no greater than 1 LSB, misalignment calibration can be achieved.

[0175] Figure 11(d) schematically illustrates the INL (integral nonlinearity) plot of a 14-bit pipelined analog-to-digital converter model calibrated according to an embodiment of the present disclosure.

[0176] According to embodiments of this disclosure, as can be seen from the images, the calibrated integral nonlinearity is less than 1 LSB, and the ADC calibration can achieve a non-cumulative error of less than 1 LSB.

[0177] Figure 12 The diagram illustrates a real-world test of card issuance according to an embodiment of this disclosure.

[0178] According to embodiments of this disclosure, the images show calibration test results. The left side shows the data acquisition card, and the right side shows enlarged views of the front and back of the card. The front side features an ADC12D1600RFIUT, a pipeline ADC with a sampling rate of 1.6 GHz and a resolution of 12 bits. However, since pipeline ADCs can only achieve 8.4 effective bits, they require calibration. The back side features an ADS7066, an ADC with a sampling rate of 125 ksps and a resolution of 16 bits. Because it uses a successive approximation ADC, its sampling speed is slow, but it achieves accurate sampling and can be considered an ideal ADC. The VIRTEX-7 is a resource-rich FPGA capable of calculating the TPSO calibration algorithm.

[0179] Based on the aforementioned background calibration method for analog-to-digital converter models, this disclosure also provides a background calibration apparatus for analog-to-digital converter models. The following will be combined with... Figure 13 The device is described in detail.

[0180] Figure 13 A schematic block diagram of a background calibration apparatus for an analog-to-digital converter model according to an embodiment of the present disclosure is shown.

[0181] like Figure 13 As shown, the background calibration device 1300 for the analog-to-digital converter model in this embodiment includes a first acquisition module 1310, a determination module 1320 and a first calibration module 1330.

[0182] The first obtaining module 1310 is used to input the first output result of the analog-to-digital converter model to be calibrated in the current round and the second output result of the reference analog-to-digital converter model into a loss function to obtain the loss function value of the current round. The first output result represents the output result of the comparator in the analog-to-digital converter model to be calibrated, and the second output result represents the output result of the comparator in the reference analog-to-digital converter model. The analog-to-digital converter model to be calibrated includes multiple cascaded analog-to-digital converters, each including a margin amplifier and a comparator. In one embodiment, the obtaining module 1310 can be used to perform the operation S310 described above, which will not be repeated here.

[0183] The determining module 1320 is used to determine the step size of the current round based on the loss function value of the previous round and the loss function value of the current round. The loss function value of the previous round is obtained by inputting the first output result of the analog-to-digital converter model to be calibrated and the second output result of the reference analog-to-digital converter model from the previous round into the loss function. In one embodiment, the determining module 1320 can be used to perform the operation S320 described above, which will not be repeated here.

[0184] The first calibration module 1330 is used to calibrate the first parameter information of the analog-to-digital converter model to be calibrated in the current round according to the step size and learning factor set of the current round. The first parameter information includes the parameters of the margin amplifier and the comparator. The learning factor set includes multiple learning factors, each corresponding one-to-one with the analog-to-digital converter to be calibrated. In one embodiment, the calibration module 1330 can be used to perform the operation S330 described above, which will not be repeated here.

[0185] According to embodiments of this disclosure, the determining module 1320 may include a first determining unit and a second determining unit. The first determining unit is configured to determine the difference between the loss function value of the current round and the loss function value of the previous round. The second determining unit is configured to determine the step size of the current round based on the loss function value of the current round and the difference between the loss function value of the current round and the loss function value of the previous round.

[0186] According to embodiments of this disclosure, the first calibration module 1330 may include a third determining unit and a first calibration unit. The third determining unit is used to determine the product between the step size of the current round and the learning factor corresponding to each stage of the analog-to-digital converter (ADC) in the ADC model to be calibrated. The first calibration unit is used to calibrate the first parameter information in the ADC of the current round based on the product.

[0187] According to embodiments of this disclosure, the background calibration method 1300 for an analog-to-digital converter (ADC) model described above may further include a second acquisition module and a second calibration module. The second acquisition module is used to input the loss function value of the current round, the sampling quantization information of the ADC model to be calibrated, and the sampling quantization information of a reference ADC model into the learning logic model to obtain the model output value of the current round. The second calibration module is used to calibrate the second parameter information of the ADC model to be calibrated based on the model output value of the current round, wherein the second parameter information includes the comparator threshold of the comparator and the operational amplifier gain of the operational amplifier.

[0188] According to embodiments of this disclosure, the second calibration module may include a first update unit, a second update unit, a third update unit, and a fourth determination unit. The first update unit is used to update the current positions of multiple traction particles based on their respective current fitness function values ​​when the termination condition is not met. The particle swarm also includes multiple ordinary particles, where the traction particles represent operational amplifier gains and the ordinary particles represent comparator thresholds. The second update unit is used to update the local optimal positions of the multiple traction particles and the multiple ordinary particles based on their respective current fitness function values ​​when the updated current positions of the traction particles remain unchanged. The local optimal position of the traction particles represents their local optimal operational amplifier gains, and the local optimal position of the ordinary particles represents their local optimal comparator thresholds. The third update unit is used to update the global optimal position of the particle swarm based on the updated local optimal positions of the multiple traction particles and the multiple ordinary particles. The fourth determination unit is used to determine the global optimal position obtained when the termination condition is met as the target second parameter information of the analog-to-digital converter model to be calibrated. The target second parameter information includes the globally optimal comparator threshold and the globally optimal operational amplifier gain.

[0189] According to embodiments of this disclosure, the second calibration module may further include a construction unit. The construction unit is used to construct a model of the analog-to-digital converter to be calibrated based on the error information of the actual analog-to-digital converter.

[0190] According to embodiments of this disclosure, any plurality of modules among the obtaining module 1310, determining module 1320, and calibration module 1330 may be combined into one module, or any one of these modules may be split into multiple modules. Alternatively, at least a portion of the functionality of one or more of these modules may be combined with at least a portion of the functionality of other modules and implemented in one module. According to embodiments of this disclosure, at least one of the obtaining module 1310, determining module 1320, and calibration module 1330 may be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or any other reasonable means of integrating or packaging circuitry, or implemented in software, hardware, or firmware, or in any suitable combination of any of these three implementation methods. Alternatively, at least one of the obtaining module 1310, determining module 1320, and calibration module 1330 may be at least partially implemented as a computer program module, which, when run, can perform corresponding functions.

[0191] Figure 14 A block diagram schematically illustrates an electronic device suitable for implementing a background calibration method for an analog-to-digital converter model according to an embodiment of the present disclosure.

[0192] like Figure 14 As shown, an electronic device 1400 according to an embodiment of the present disclosure includes a processor 1401, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1402 or a program loaded from a storage portion 908 into a random access memory (RAM) 1403. The processor 1401 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 1401 may also include onboard memory for caching purposes. The processor 1401 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present disclosure.

[0193] RAM 1403 stores various programs and data required for the operation of electronic device 1400. Processor 1401, ROM 1402, and RAM 1403 are interconnected via bus 1404. Processor 1401 performs various operations of the method flow according to embodiments of the present disclosure by executing programs in ROM 1402 and / or RAM 1403. It should be noted that the programs may also be stored in one or more memories other than ROM 1402 and RAM 1403. Processor 1401 may also perform various operations of the method flow according to embodiments of the present disclosure by executing programs stored in said one or more memories.

[0194] According to embodiments of this disclosure, the electronic device 1400 may further include an input / output (I / O) interface 1405, which is also connected to a bus 1404. The electronic device 1400 may also include one or more of the following components connected to the I / O interface 1405: an input section 1406 including a keyboard, mouse, etc.; an output section 1407 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1408 including a hard disk, etc.; and a communication section 1409 including a network interface card such as a LAN card, modem, etc. The communication section 1409 performs communication processing via a network such as the Internet. A drive 1410 is also connected to the I / O interface 1405 as needed. A removable medium 1411, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 1410 as needed so that computer programs read from it can be installed into the storage section 1408 as needed.

[0195] This disclosure also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs that, when executed, implement the method according to the embodiments of this disclosure.

[0196] According to embodiments of this disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this disclosure, the computer-readable storage medium may include ROM 1402 and / or RAM 1403 and / or one or more memories other than ROM 1402 and RAM 1403 described above.

[0197] Embodiments of this disclosure also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to cause the computer system to implement the item recommendation method provided in the embodiments of this disclosure.

[0198] When the computer program is executed by the processor 1401, it performs the functions defined in the system / apparatus of this disclosure embodiments. According to embodiments of this disclosure, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0199] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 1409, and / or installed from the removable medium 1411. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0200] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 1409, and / or installed from the removable medium 1411. When the computer program is executed by the processor 1401, it performs the functions defined in the system of this disclosure embodiment. According to embodiments of this disclosure, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0201] According to embodiments of this disclosure, program code for executing the computer programs provided in embodiments of this disclosure can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can execute entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0202] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0203] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0204] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A background calibration method for an analog-to-digital converter model, comprising: The first output of the analog-to-digital converter (ADC) model to be calibrated in the current round and the second output of the reference ADC model are input into the loss function to obtain the loss function value of the current round. The first output represents the output of the comparator in the ADC model to be calibrated, and the second output represents the output of the comparator in the reference ADC model. The ADC model to be calibrated includes multiple cascaded ADCs to be calibrated, and each ADC includes a margin amplifier and a comparator. The model to be calibrated for analog-to-digital converters includes M cascaded analog-to-digital converters to be calibrated; the first output result includes M third output results at multiple time points, and the second output result includes M fourth output results at the multiple time points, where M is an integer greater than or equal to 1; the loss function value represents the average of the differences between the multiple third output results and the multiple fourth output results. The step size for the current round is determined based on the loss function value from the previous round and the loss function value for the current round. The loss function value from the previous round is obtained by inputting the first output of the analog-to-digital converter model to be calibrated from the previous round and the second output of the reference analog-to-digital converter model into the loss function. Based on the step size and learning factor set of the current round, the first parameter information of the analog-to-digital converter model to be calibrated in the current round is calibrated, wherein the first parameter information includes the parameters of the margin amplifier and the parameters of the comparator, and the learning factor set includes multiple learning factors, each of which corresponds one-to-one with the analog-to-digital converter to be calibrated.

2. The method according to claim 1, wherein, The third output of the m-th stage is obtained by processing the output of the margin amplifier in the (m-1)-th stage analog-to-digital converter to be calibrated using the m-th stage analog-to-digital converter to be calibrated, where m is an integer greater than or equal to 1 and less than or equal to M.

3. The method according to any one of claims 1 to 2, wherein, Determining the step size for the current round based on the loss function value of the previous round and the loss function value of the current round includes: Determine the difference between the loss function value of the current round and the loss function value of the previous round; and The step size of the current round is determined based on the loss function value of the current round and the difference between the loss function value of the current round and the loss function value of the previous round.

4. The method according to any one of claims 1 to 2, wherein, The step of calibrating the first parameter information of the analog-to-digital converter model to be calibrated in the current round based on the step size and learning factor set of the current round includes: Determine the product between the step size of the current round and the learning factor corresponding to each stage of the analog-to-digital converter to be calibrated in the model to be calibrated; and Based on the product, the first parameter information in the analog-to-digital converter to be calibrated in the current round is calibrated.

5. The method according to any one of claims 1 to 2, wherein, The analog-to-digital converter to be calibrated also includes an operational amplifier; The method further includes: The loss function value of the current round, the sampling quantization information of the analog-to-digital converter model to be calibrated, and the sampling quantization information of the reference analog-to-digital converter model are input into the learning logic model to obtain the model output value of the current round; and Based on the model output value of the current round, the second parameter information of the analog-to-digital converter model to be calibrated is calibrated, wherein the second parameter information includes the comparator threshold of the comparator and the operational amplifier gain of the operational amplifier.

6. The method according to claim 5, wherein, The step of calibrating the second parameter information of the analog-to-digital converter model to be calibrated based on the model output value of the current round includes repeating the following operations until the termination condition is met: If it is determined that the termination conditions are not met. The current positions of the multiple traction particles are updated according to their respective current fitness function values. The particle swarm also includes multiple ordinary particles, where the traction particles represent the operational amplifier gain and the ordinary particles represent the comparator threshold. If it is determined that the current position of the traction particle has not changed after the update, the local optimal position of each of the multiple traction particles and the multiple ordinary particles is updated according to the current fitness function value of each of the multiple traction particles and the multiple ordinary particles. The local optimal position of the traction particle represents the local optimal op-amp gain of the traction particle, and the local optimal position of the ordinary particle represents the local optimal comparator threshold of the ordinary particle. The global optimal position of the particle swarm is updated based on the updated local optimal positions of the plurality of traction particles and the plurality of ordinary particles; and The globally optimal position obtained under the condition of satisfying the termination condition is determined as the target second parameter information of the analog-to-digital converter model to be calibrated, wherein the target second parameter information includes the globally optimal comparator threshold and the globally optimal operational amplifier gain.

7. The method according to claim 6, further comprising: The model of the analog-to-digital converter to be calibrated is constructed based on the error information of the actual analog-to-digital converter.

8. The method according to claim 7, wherein, The error information includes at least one of the following: clock jitter error, switching thermal noise, comparator offset, capacitor mismatch, op-amp finite gain, and op-amp parasitic capacitance.

9. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 8.

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