Solid state transformer topology and fault blocking method based on complementary sub-module pairs

Abstract

The application discloses a solid-state transformer topology based on complementary sub-module pairs and a fault blocking method, and the topology comprises a medium-voltage alternating-current end, a medium-voltage direct-current end, a low-voltage alternating-current end, a low-voltage direct-current end and a three-phase circuit topology, wherein the three-phase circuit topology comprises three identical single-phase lines, the single-phase line comprises a plurality of complementary sub-module pairs, the complementary sub-module pair comprises a first sub-module and a second sub-module which are structurally identical, and the fault blocking method comprises the following steps: in the case of a direct-current fault, the pulse of all switch tubes in each sub-module is turned off; the capacitor in the capacitor bridge arm is introduced into the current path, and the reverse blocking of the conducting diode is realized by using the capacitor voltage, so that the current path is cut off. Compared with a traditional topology, the number of switch tubes is reduced, and the power density is improved; in the case of a direct-current fault, the current path is effectively cut off, and the stability of the system is significantly improved.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a solid-state transformer topology and fault-blocking method based on complementary submodule pairs. Background Technology

[0002] AC / DC hybrid distribution networks have ports with multiple voltage levels and voltage configurations, allowing for the transmission and conversion of electrical energy between AC / DC and high / low voltage ports. They are suitable for integrating new energy sources and DC loads, and represent one of the important directions for future distribution network development. Solid-state transformers (SSTs), due to their flexible controllability and multi-port access capabilities, have become core equipment in AC / DC hybrid distribution networks.

[0003] The MMC-SST (modular-multilevel-converter, MMC) features an MVDC (medium-voltage DC) port, making it suitable for medium- and high-voltage power transmission and distribution applications. It enables grid connection and local consumption of distributed energy resources, thus holding broad application prospects in AC / DC hybrid distribution networks. The Dual Active Bridge (DAB) type MMC-SST topology offers advantages such as flexible control and ease of redundancy and fault tolerance. However, because a DAB connection is required on the DC side of each submodule, a large number of switching devices are needed in medium-voltage distribution networks, resulting in low power density for the SST. This severely restricts the application of the DAB type MMC-SST, and the solid-state transformer needs to be shut down in the event of a DC short-circuit fault. Summary of the Invention

[0004] Objective of the Invention: This invention provides a solid-state transformer topology and fault-blocking method based on complementary submodule pairs. Utilizing the structure of complementary submodule pairs in a three-phase line reduces the number of switching transistors used, thereby increasing power density. Based on the decoupling of common-mode and differential-mode complementary submodule pairs, the mixing modulation method eliminates the need for any frequency selection network, achieving decoupling of high- and low-frequency modulation signals from the submodules and avoiding mutual interference between high-frequency and low-frequency switching signals. In the event of a DC fault in the solid-state transformer topology, the switching transistors in the submodules can be controlled to shut down, effectively cutting off the current path and significantly improving system stability.

[0005] Technical Solution: This invention provides a solid-state transformer topology based on complementary submodule pairs, including: a medium-voltage AC terminal, a medium-voltage DC terminal, a low-voltage AC terminal, a low-voltage DC terminal, and a three-phase circuit topology, wherein: the three-phase circuit topology includes three identical single-phase lines, each single-phase line including multiple complementary submodule pairs; each complementary submodule pair includes a first submodule and a second submodule with identical structures, each submodule including a front-end circuit, a back-end circuit, and a transformer, the front-end circuit including a first bridge arm, a second bridge arm, and a capacitor bridge arm connected in parallel, the first bridge arm and the second bridge arm each including two series-connected switching transistors, and the capacitor bridge arm including two series-connected switching transistors. The capacitor, the subsequent circuit includes a third bridge arm and a fourth bridge arm connected in parallel, each of which includes two series-connected switching transistors; the midpoints of the first and second bridge arms are connected to the primary side of the transformer, and the midpoints of the third and fourth bridge arms are connected to the secondary side of the transformer; a first wiring leads out from the midpoint of the first bridge arm, and a second wiring leads out from the midpoint of the capacitor bridge arm; the second wiring of the first submodule is connected to the first wiring of the second submodule; the first wiring of the first submodule and the second wiring of the second submodule serve as interfaces for interconnection between complementary submodule pairs; the corresponding endpoints in the fourth bridge arms of the first and second submodules are... Instead of connecting via connecting lines, two interfaces are led out from each of the two connecting lines, serving as interfaces for interconnection between complementary submodule pairs. These interfaces are connected to the third and fourth wiring terminals, respectively. The endpoint refers to the parallel connection point between two bridge arms; the midpoint refers to the connection point between two switching transistors or two capacitors; the medium-voltage AC terminal consists of one port led out from the connecting line between complementary submodule pairs on each single-phase line, forming three ports on three single-phase lines; the medium-voltage DC terminal includes two ports, corresponding to the first submodule of the first complementary submodule pair on the three single-phase lines, according to the order of their positions on the single-phase lines. The first wiring is interconnected to form one port. The second wiring of the second submodule of the last complementary submodule pair on the three single-phase lines is interconnected to form another port. The low-voltage AC terminal includes four parallel low-voltage bridge arms. Each low-voltage bridge arm includes two series-connected switching transistors. The two ends of the low-voltage bridge arm are connected to the third or fourth wiring of a single-phase line. The midpoints of the four low-voltage bridge arms lead out to four ports. The low-voltage DC terminal includes two ports. The third wiring of the three single-phase lines is interconnected to form one port. The fourth wiring of the three single-phase lines is interconnected to form another port.

[0006] Specifically, a protection diode is provided on the second wiring of each submodule. The positive terminal of the protection diode is connected to the first wiring of the adjacent submodule, and the negative terminal of the protection diode is connected to the midpoint of the capacitor bridge arm of the submodule.

[0007] Specifically, each submodule also includes a protection switch transistor. One end of the protection switch transistor is connected to the corresponding endpoint of the first bridge arm of the submodule, and the other end is connected to the positive terminal of the protection diode of the submodule. The current conduction direction is opposite to the current conduction direction of the first bridge arm of the submodule.

[0008] Specifically, each submodule's subsequent circuitry includes a capacitor connected in parallel with the fourth bridge arm.

[0009] Specifically, an inductor is installed on the connection line between the midpoint of the first bridge arm of each submodule and the primary side of the transformer.

[0010] Specifically, inductors are installed on both sides of the port where the medium-voltage AC terminal is led out on the connection line between the complementary submodules.

[0011] This invention also provides a fault blocking method for a solid-state transformer topology based on complementary submodule pairs. For the solid-state transformer topology based on complementary submodule pairs described above, the method includes: in the event of a DC fault: shutting off the pulses of all switching transistors in each submodule; the capacitors in the capacitor bridge arms are introduced into the current path, and the capacitor voltage causes the conducting diodes to reverse-biased cutoff, thereby cutting off the current path; under normal operating conditions: in the complementary submodule pair, the first submodule serves as a high-frequency submodule, and the second submodule is configured as a corresponding high-frequency cancellation submodule; the modulation signal of the high-frequency cancellation submodule has the same DC component and fundamental frequency component as the high-frequency submodule, and the high-frequency component is opposite to that of the high-frequency submodule.

[0012] Specifically, under normal operating conditions: the common-mode low-frequency modulation signal and the differential-mode high-frequency modulation signal of the first bridge arm are used in the second bridge arm of the submodule.

[0013] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: Compared with the traditional half-bridge topology and full-bridge topology, the number of switching transistors used is reduced by 1 / 10 and 1 / 4 respectively, while improving power density; mutual interference between high-frequency switching signals and low-frequency switching signals is avoided; in the event of a DC fault, the current path is effectively cut off, significantly improving the stability of the system. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the solid-state transformer topology provided by the present invention;

[0015] Figure 2 This is a schematic diagram of the structure of the complementary submodule pair provided by the present invention;

[0016] Figure 3 This is a schematic diagram illustrating the principle of differential mode elimination of high-frequency interference signals in the output voltage by the complementary submodule provided by the present invention.

[0017] Figure 4 This is a schematic diagram illustrating the principle of common-mode cancellation of low-frequency interference signals in the output voltage by the complementary submodule provided by the present invention.

[0018] Figure 5 and Figure 6 These are simulation verification diagrams showing the decoupling of high-frequency and low-frequency modulation signals under normal operating conditions of the solid-state transformer topology provided by this invention.

[0019] Figures 7 to 9 The figures shown are the simulated waveforms of the MVDC port voltage, the MVAC port DC current, and the AC current when the solid-state transformer topology provided by this invention experiences a DC short-circuit fault. Detailed Implementation

[0020] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0021] See Figure 1 This is a schematic diagram of the solid-state transformer topology provided by the present invention; see reference. Figure 2 This is a schematic diagram of the complementary submodule pair provided by the present invention.

[0022] This invention provides a solid-state transformer topology based on complementary submodule pairs, comprising: a medium-voltage AC terminal (MVAC port), a medium-voltage DC terminal (MVDC port), a low-voltage AC terminal (LVAC port), a low-voltage DC terminal (LVDC port), and a three-phase circuit topology, wherein: the three-phase circuit topology includes three identical single-phase lines, each single-phase line comprising multiple complementary submodule pairs; each complementary submodule pair includes a first submodule and a second submodule with identical structures, each submodule including a front-end circuit, a back-end circuit, and a transformer, the front-end circuit including a first bridge arm, a second bridge arm, and a capacitor bridge arm connected in parallel, the first bridge arm and the second bridge arm respectively including... The circuit consists of two series-connected switching transistors and two series-connected capacitors on each of its capacitor bridge arms. The subsequent circuit includes a third and fourth bridge arm connected in parallel, each containing two series-connected switching transistors. The midpoints of the first and second bridge arms are connected to the primary side of the transformer, and the midpoints of the third and fourth bridge arms are connected to the secondary side of the transformer. A first connection is led out from the midpoint of the first bridge arm, and a second connection is led out from the midpoint of the capacitor bridge arm. The second connection of the first submodule is connected to the first connection of the second submodule. The first connection of the first submodule and the second connection of the second submodule serve as interfaces for interconnection between complementary submodule pairs. The corresponding endpoints in the fourth bridge arm of the module are connected via connecting lines. Two interfaces, each extending from one of the two connecting lines, serve as interfaces for interconnection between complementary submodule pairs. These interfaces are connected to the third and fourth wiring terminals, respectively. The endpoint refers to the parallel connection point between two bridge arms. The midpoint refers to the connection point between two switching transistors or two capacitors. The medium-voltage AC terminal consists of one port extending from the connecting line between complementary submodule pairs on each single-phase line, forming three ports on three single-phase lines. The medium-voltage DC terminal includes two ports, corresponding to the first complementary submodule pair on each of the three single-phase lines, based on their position in the single-phase lines. The first wiring of the first submodule is interconnected to form a port, and the second wiring of the second submodule of the last complementary submodule pair on the three single-phase lines is interconnected to form another port; the low-voltage AC terminal includes four parallel low-voltage bridge arms, each low-voltage bridge arm including two series-connected switching transistors, the two ends of the low-voltage bridge arm are connected to the third or fourth wiring of a single-phase line, and the midpoints of the four low-voltage bridge arms lead out to four ports respectively; the low-voltage DC terminal includes two ports, the third wiring of the three single-phase lines is interconnected to form a port, and the fourth wiring of the three single-phase lines is interconnected to form another port.

[0023] In this embodiment of the invention, each submodule's subsequent circuit includes a capacitor connected in parallel with the fourth bridge arm.

[0024] In this embodiment of the invention, an inductor is provided on the connection line between the midpoint of the first bridge arm of each submodule and the primary side of the transformer.

[0025] In this embodiment of the invention, inductors are provided on both sides of the port where the medium-voltage AC terminal is led out on the connection line between the complementary submodules (between the first and second wirings of the submodules).

[0026] In practical implementation, the terms low voltage, medium voltage, high voltage, low frequency, medium frequency, and high frequency used in this invention distinguish different ports in the topology provided by the invention through differences in voltage or frequency ranges, rather than limiting the voltage or frequency. Generally speaking, 1kV and below is considered low voltage, above 1kV and below 20kV is considered medium voltage, above 20kV is considered high voltage, low frequency is below 50Hz, and high frequency is above 10kHz.

[0027] In practical implementation, as shown in the diagram of the SM-DAB (complementary submodule pair), the first submodule (SM-DAB1) or the second submodule (SM-DAB2) has a downstream circuit structure consisting of an H-bridge rectifier circuit composed of four switching transistors Q1 to Q4 and an output parallel capacitor C. The upstream circuit consists of four switching transistors S1 to S4 and two capacitors (C1 and C2) (capacitor bridge arms). Switches S1 and S2 are connected in series to form the first bridge arm, switches S3 and S4 are connected in series to form the second bridge arm, the capacitor bridge arm is connected in parallel between the first and second bridge arms, switches Q1 and Q2 are connected in series to form the third bridge arm, and switches Q3 and Q4 are connected in series to form the fourth bridge arm. Lr represents the leakage inductance of the high-frequency transformer.

[0028] In specific implementation, regarding the parallel connection between the subsequent circuits of the first and second submodules in the complementary submodule pair, the corresponding endpoints of the fourth bridge arms of the first and second submodules are connected by connecting lines. This means that one end of the fourth bridge arm of the first submodule is connected to the same end of the fourth bridge arm of the second submodule. For example, the two endpoints on the Q1 and Q3 side of the two submodules are connected, and the two endpoints on the Q2 and Q4 side are connected. After the connection, two connecting lines can be formed. The two interfaces led out from the two connecting lines serve as the interfaces for mutual connection between the complementary submodule pairs. The corresponding interfaces are connected to the third and fourth wiring respectively. Among the corresponding interfaces, the interfaces led out from the connecting lines on the same side of the fourth bridge arm are connected to the same wiring. For example, the interfaces led out from the connecting lines between the two endpoints on the Q1 and Q3 side are both connected to the third wiring, and the interfaces led out from the connecting lines between the two endpoints on the Q2 and Q4 side are both connected to the fourth wiring.

[0029] In specific implementation, in the submodule, the first wire drawn from the midpoint of the first bridge arm of the first submodule and the second wire drawn from the midpoint of the capacitor bridge arm of the second submodule are used to connect with other complementary submodules, thereby realizing the cascading of complementary submodules to the input stage; connecting lines are drawn from the midpoint of the first bridge arm and the midpoint of the second bridge arm respectively, and connected to the high-frequency transformer to realize the power transmission, transformation and isolation from the medium voltage side to the low voltage side.

[0030] In practical implementation, the DAB complementary submodule pair (SM-DAB) consists of three parts: the input stage MMC (front-end circuit section), the intermediate stage DAB (transformer section), and the output stage (back-end circuit section). The input stage MMC provides an MVAC port (medium-voltage AC terminal) and an MVDC port (medium-voltage DC terminal), with the voltage and current on the MVAC side being u... a u b u c and i a i b i c The voltage and current on the MVDC side are u mvdc and i mvdc The intermediate-stage DABs implement voltage conversion, power transfer, and high-frequency isolation functions. The outputs of each DAB are connected in parallel to provide LVDC ports (low-voltage DC terminals), with port voltage and port current u respectively. lvdc and i lvdc The LVDC port can be connected to a three-phase / single-phase inverter according to actual needs, and an LVAC port (low-voltage AC terminal) is provided with a port voltage of u. lvac In a hybrid AC / DC distribution network, the MVAC port is used to connect to the three-phase AC distribution network for the interaction of active and reactive power; the MVDC port can be directly connected to the DC distribution network or connected to the MVDC ports of other SSTs, thereby realizing flexible interconnection between regional power grids, enabling flexible power allocation between regions and the consumption of new energy sources at the distribution network level; the LVDC port and LVAC port can connect to low-voltage AC / DC loads and also enable the access of low-voltage distributed energy sources of different forms.

[0031] In practical implementation, the subsequent circuits of the first submodule (SM-DAB1) and the second submodule (SM-DAB2) are connected in parallel. Since the topology of the complementary submodule pair is exactly the same, only the modulation wave is different, when analyzing the topology of the complementary submodule pair, it is only necessary to analyze one of the submodules.

[0032] In this embodiment of the invention, a protection diode Df is provided on the second wiring of each submodule. The positive terminal of the protection diode is connected to the first wiring of the adjacent submodule, and the negative terminal of the protection diode is connected to the midpoint of the capacitor bridge arm of the submodule.

[0033] In this embodiment of the invention, each submodule further includes a protection switch Sf. One end of the protection switch is connected to the corresponding endpoint of the first bridge arm of the submodule, and the other end is connected to the positive terminal of the protection diode Df of the submodule. The current conduction direction is opposite to the current conduction direction of the first bridge arm of the submodule.

[0034] In practice, during normal operation, the protection switch Sf is always on and the protection diode Df is always off.

[0035] In practical implementation, within each submodule, the first bridge arm, protection switch Sf, and protection diode Df can be considered part of the input-stage MMC submodule, used to achieve energy exchange between the MVAC and MVDC ports and maintain capacitor voltage stability. The first and second bridge arms can be seen as part of the primary-side H-bridge circuit of the intermediate-stage DAB, which is used to achieve energy transfer from the input stage to the intermediate stage. Under normal operation, the input-stage MMC submodule operates very similarly to the half-bridge submodule. Therefore, the main power devices S1 and S2 can fully adopt the modulation method and balancing control strategy of the half-bridge submodule.

[0036] In specific implementation, it can be seen from the topology construction that the first bridge arm belongs to both the input stage MMC and the intermediate stage DAB. When the MMC-SST is working normally, the input stage MMC needs to be connected to a low-frequency AC current and voltage, while the DAB contains a high-frequency transformer and must work in high-frequency mode. Therefore, in the complementary submodule pair (SM-DAB), the first bridge arm contains both high-frequency modulation signals and low-frequency modulation signals. For the complementary submodule pair, it is necessary to ensure that the input stage MMC outputs a low-frequency AC voltage and that the high-frequency transformer in the intermediate stage DAB works normally. Under this premise, the MMC-SST proposed in this paper needs to meet the following two conditions at the same time: (1) For the input stage MMC of the SST, the output voltage of the MMC port is determined only by the low-frequency modulation signal, or the output voltage of the MMC bridge arm is determined only by the low-frequency modulation signal; (2) For the intermediate stage DAB of the SST, the DAB port must output a high-frequency voltage, and the voltage signal of the port is determined only by the high-frequency modulation signal.

[0037] This invention also provides a fault blocking method for a solid-state transformer topology based on complementary submodule pairs. For the solid-state transformer topology based on complementary submodule pairs in the embodiments provided by this invention, the method includes: in the event of a DC short-circuit fault: shutting off the pulses of all switching transistors in each submodule; the capacitors in the capacitor bridge arms are introduced into the current path, and the capacitor voltage is used to reverse-bias the conducting diodes to cut off, thereby interrupting the current path; under normal operating conditions: in the complementary submodule pair, the first submodule is designated as the high-frequency submodule (SM-DAB1), and the second submodule is designated as the corresponding high-frequency cancellation submodule (SM-DAB2); the modulation signal of the high-frequency cancellation submodule (SM-DAB2) has the same DC component and fundamental frequency component as the high-frequency submodule (SM-DAB1), and the high-frequency component is opposite to that of the high-frequency submodule (SM-DAB1).

[0038] In this embodiment of the invention, under normal operating conditions: the common-mode low-frequency modulation signal and the differential-mode high-frequency modulation signal of the first bridge arm are used in the second bridge arm of the submodule.

[0039] In practical implementation, the baseband modulation signal is obtained by controlling the input stage MMC, specifically including three aspects: circulating current suppression, overall energy control, and capacitor voltage balance control. The switching signals of the complementary submodule for the subsequent stage switches Q1 to Q4 are obtained by delaying the high-frequency modulation signal of the previous stage and then performing PWM modulation. The delay time t between the high-frequency modulation signals of the previous and subsequent stages can be obtained by subtracting the reference voltage value and the actual voltage value at the LVDC port and then controlling it with a PI controller.

[0040] See Figure 3 This is a schematic diagram illustrating the principle of differential mode elimination of high-frequency interference signals in the output voltage by the complementary submodule provided by the present invention. According to... Figure 2 In the complementary submodule pair topology, the first bridge arm contains both high-frequency and low-frequency modulation signals. Therefore, the MMC port output voltage of a single submodule cannot be determined solely by the low-frequency modulation signal. It must work in conjunction with the MMC port output voltages of other submodules in the MMC bridge arm to ensure that the MMC bridge arm output voltage is determined only by the low-frequency modulation signal. Therefore, to eliminate the high-frequency baseband harmonic components generated by the first submodule (SM-DAB1), a complementary submodule pair is proposed. Specifically, a high-frequency cancellation submodule (SM-DAB2) is defined in the MMC bridge arm. Its DC and fundamental frequency components are the same as SM-DAB1, while its high-frequency components are opposite to those of SM-DAB1, thus achieving the elimination of the high-frequency modulation frequency components in the bridge arm output voltage.

[0041] See Figure 4 This is a schematic diagram illustrating the principle of common-mode cancellation of low-frequency interference signals in the output voltage by the complementary submodule provided by the present invention. According to... Figure 2In the complementary submodule topology, the DAB port is connected to the high-frequency transformer. To ensure the normal operation of the high-frequency transformer, the DAB port needs to output a high-frequency voltage. The DAB port is formed by connecting lines from the midpoint of the first and second bridge arms. Since the first bridge arm contains both high-frequency and low-frequency modulation signals, the modulation signal of the second bridge arm must also contain both high-frequency and low-frequency modulation signals. The DAB port output voltage is a differential-mode voltage, which is equal to the output voltage of the first bridge arm minus the output voltage of the second bridge arm. Therefore, by using the common-mode low-frequency modulation signal and the differential-mode high-frequency modulation signal of the first bridge arm in the second bridge arm, the DAB port can output only a high-frequency voltage signal.

[0042] See Figure 5 and Figure 6 These are simulation verification diagrams of high-frequency and low-frequency modulation signal decoupling under normal operating conditions of the solid-state transformer topology provided by this invention. Figure 5 The verification was performed using the output voltage waveform of the upper arm of the a-phase line of the input stage MMC. As can be seen from the figure, using the mixing modulation method provided by this invention, the output voltage of the SST input stage bridge arm is a multi-level waveform with a fundamental frequency variation, consistent with the voltage waveform obtained by using only the fundamental frequency modulation signal on the bridge arm. This indicates that the high-frequency submodule (SM-DAB1) and high-frequency cancellation submodule (SM-DAB2) inside the bridge arm can effectively cancel the high-frequency modulation signal at the input stage. Figure 6 The input voltage waveform across the high-frequency transformer was used for verification. As shown in the figure, the input voltage across the high-frequency transformer is a high-frequency sinusoidal pulse waveform, with a frequency consistent with the high-frequency modulation wave, and does not contain low-frequency components. Based on... Figure 5 and Figure 6 As can be seen from the waveform, the mixing modulation method provided by the present invention can separate high and low frequency modulation signals without any frequency selection network, based on the common-mode and differential-mode decoupling principle.

[0043] See Figures 7 to 9The figures show simulated waveforms of the solid-state transformer topology provided by this invention during a DC short-circuit fault. When a DC fault occurs, the voltage and current states at the MVDC and MVAC ports are shown. At 0.699s, a DC short-circuit fault is simulated, immediately blocking the pulses of all switches (S1, S2, S3, S4, and Sf). When the bridge arm current is less than 0, the current path inside the submodule consists of diode S2, protection diode Df, and capacitor C2. Since the total voltage of capacitor C2 is higher than the peak AC voltage, the diode will withstand reverse voltage. Similarly, when the bridge arm current is greater than 0, the current path inside the submodule consists of diode S1, protection switch Sf, capacitor C1, and capacitor C2. Since the total voltage of capacitors C1 and C2 connected in series is higher than the peak AC voltage, the diode conducting at the fault time will withstand reverse voltage, thus cutting off the fault current path. The simulated waveforms show that this topology has fault-blocking capability.

Claims

1. A solid-state transformer topology based on complementary submodule pairs, characterized in that, include: Medium-voltage AC terminal, medium-voltage DC terminal, low-voltage AC terminal, low-voltage DC terminal, and three-phase circuit topology, wherein: The three-phase circuit topology includes three identical single-phase lines, and each single-phase line includes multiple pairs of complementary sub-modules. The complementary submodule pair includes a first submodule and a second submodule with identical structures. Each submodule includes a front-end circuit, a back-end circuit, and a transformer. The front-end circuit includes a first bridge arm, a second bridge arm, and a capacitor bridge arm connected in parallel. The first and second bridge arms each include two series-connected switching transistors, and the capacitor bridge arm includes two series-connected capacitors. The back-end circuit includes a third and fourth bridge arm connected in parallel. The third and fourth bridge arms each include two series-connected switching transistors. The midpoints of the first and second bridge arms are connected to the primary side of the transformer, and the midpoints of the third and fourth bridge arms are connected to the secondary side of the transformer. The midpoint of the first bridge arm... The first wiring point is led out from the midpoint of the capacitor bridge arm, and the second wiring point is led out from the midpoint of the capacitor bridge arm; the second wiring point of the first submodule is connected to the first wiring point of the second submodule; the first wiring point of the first submodule and the second wiring point of the second submodule serve as interfaces for mutual connection between complementary submodule pairs; the corresponding endpoints in the fourth bridge arms of the first submodule and the second submodule are respectively connected through connecting lines, and the two interfaces led out from the two connecting lines serve as interfaces for mutual connection between complementary submodule pairs, and the corresponding interfaces are respectively connected to the third wiring point and the fourth wiring point; the endpoint refers to the parallel connection point between the two bridge arms; the midpoint refers to the connection point between the two switching transistors or the two capacitors; The medium-voltage AC terminal has a port led out from the connection line between the complementary sub-module pairs on each single-phase line. The number of complementary sub-module pairs on both sides of the port is equal, and the medium-voltage AC terminal is formed by the three ports on the three single-phase lines. The medium-voltage DC terminal includes two ports. According to the position order of the complementary sub-module pairs in the single-phase lines, the first wiring of the first sub-module of the first complementary sub-module pair on the three single-phase lines is connected to each other to form one port, and the second wiring of the second sub-module of the last complementary sub-module pair on the three single-phase lines is connected to each other to form another port. The low-voltage AC terminal includes four parallel low-voltage bridge arms. Each low-voltage bridge arm includes two switching transistors connected in series. The two ends of the low-voltage bridge arm are respectively connected to the third and fourth terminals of a single-phase line. The midpoints of the four low-voltage bridge arms lead out to four ports. The low-voltage DC terminal includes two ports: one port is formed by connecting the third wiring of the three single-phase lines together, and the other port is formed by connecting the fourth wiring of the three single-phase lines together.

2. The solid-state transformer topology based on complementary submodule pairs according to claim 1, characterized in that, Each submodule has a protection diode on its second wiring terminal. The positive terminal of the protection diode is connected to the first wiring terminal of the adjacent submodule, and the negative terminal of the protection diode is connected to the midpoint of the capacitor bridge arm of the submodule.

3. The solid-state transformer topology based on complementary submodule pairs according to claim 2, characterized in that, Each submodule also includes a protection switch transistor, one end of which is connected to the corresponding endpoint of the first bridge arm of the submodule, and the other end is connected to the positive terminal of the protection diode of the submodule. The current conduction direction is opposite to the current conduction direction of the first bridge arm of the submodule.

4. The solid-state transformer topology based on complementary submodule pairs according to claim 3, characterized in that, Each submodule's subsequent circuitry includes a capacitor connected in parallel with the fourth bridge arm.

5. The solid-state transformer topology based on complementary submodule pairs according to claim 4, characterized in that, An inductor is installed on the connection line between the midpoint of the first bridge arm of each submodule and the primary side of the transformer.

6. The solid-state transformer topology based on complementary submodule pairs according to claim 4, characterized in that, Inductors are installed on both sides of the port where the medium-voltage AC terminal is led out on the connection line between the complementary submodules.

7. A fault-blocking method based on a solid-state transformer topology of complementary submodule pairs, characterized in that, The solid-state transformer topology based on complementary submodule pairs according to any one of claims 3 to 6 includes: In the event of a DC fault: the pulses of all switching transistors in each submodule are turned off; the capacitors in the capacitor bridge arm are introduced into the current path, and the capacitor voltage is used to reverse-bias the conducting diodes to cut off, thereby cutting off the current path; Under normal operating conditions: In a pair of complementary submodules, the first submodule is a high-frequency submodule, and the second submodule is set as the corresponding high-frequency cancellation submodule; the modulation signal of the high-frequency cancellation submodule has the same DC component and fundamental frequency component as the high-frequency submodule, and the high-frequency component is opposite to that of the high-frequency submodule.

8. The fault-blocking method for solid-state transformer topology based on complementary submodule pairs according to claim 7, characterized in that, Under normal operating conditions: The second arm of the submodule uses the common-mode low-frequency modulation signal and the differential-mode high-frequency modulation signal of the first arm.

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