A multi-phase sampling proportional-integral dual-path phase-locked loop

Abstract

The present invention discloses a multi-phase sampling type proportional integral dual-path phase-locked loop, which includes n-path sampling type phase detectors, high-frequency parallel-to-serial high-pass filters, transconductance amplifiers, filter capacitors, voltage-controlled oscillators, and multi-phase frequency dividers; the high-frequency parallel-to-serial high-pass filters include n-path switching capacitors and a bias resistor, and the high-frequency information in the n-path phase detection information is parallel-to-serial into one path; the multi-phase frequency divider divides the high-frequency output signal of the voltage-controlled oscillator to generate n-path sampling clocks and holding clocks, which are used as the sampling clocks and holding clocks of the n-path sampling type phase detectors, and the n-path reference clock signals are sampled and phase-detected, and the obtained n-path phase detection results are passed through the high-frequency parallel-to-serial high-pass filters to realize the proportional control path in the high frequency band; at the same time, one of the phase detection results passes through the transconductance amplifier whose load is the filter capacitor to realize the integral control path; the two control paths respectively control the two control ends of the voltage-controlled oscillator. The present invention can realize the expansion of the loop bandwidth.

Description

Technical Field

[0001] The invention relates to the field of electronic circuits, and in particular to a multi-phase sampling proportional integral dual-path phase-locked loop. Background Art

[0002] The noise of a phase-locked loop is generally divided into two parts, one is in-band noise and the other is out-of-band noise. In-band noise is mainly contributed by phase detectors, charge pumps, etc., and the in-band noise of the two can be suppressed by high-gain sampling phase detectors. Out-of-band noise is mainly contributed by oscillator noise. By expanding the loop bandwidth of the phase-locked loop, more oscillator noise can be suppressed, thereby achieving lower out-of-band noise. However, the maximum working loop bandwidth that the phase-locked loop can achieve is limited by the reference clock frequency. Directly using high-frequency and expensive crystal oscillators can meet the requirements, but it greatly increases the cost of the system, so on-chip reference clock multiplication technology has become increasingly popular. However, in the existing reference clock multiplication technology, the phase of the multiplied reference clock signal often needs to be very accurate, otherwise it will deteriorate the reference clock spurious of the phase-locked loop output signal. Therefore, it is inevitable to calibrate the equivalent multiplied reference clock in the traditional reference clock multiplication phase-locked loop. Summary of the invention

[0003] In view of the shortcomings of the prior art, the present invention provides a multi-phase sampling proportional integral dual-path phase-locked loop, and the specific technical solution is as follows:

[0004] A multi-phase sampling proportional integral dual-path phase-locked loop, comprising n-path sampling phase detectors, high-frequency parallel-to-serial high-pass filters, transconductance amplifiers, filter capacitors, voltage-controlled oscillators and multi-phase frequency dividers; n is a positive integer;

[0005] The high-frequency parallel-to-serial high-pass filter comprises n-channel switching capacitors and a bias resistor, wherein one end of the n-channel switching capacitors is used as an input end of the n-channel phase-discrimination information, and the other end is connected to one end of the bias resistor; the other end of the bias resistor is connected to a bias voltage; wherein the n-channel switching capacitors are respectively turned on by n-channel non-overlapping holding clocks, so as to realize parallel-to-serial conversion of the high-frequency information in the n-channel phase-discrimination information into one channel;

[0006] The multi-phase frequency divider divides the frequency of the high-frequency output signal of the voltage-controlled oscillator to generate n sampling clock signals and n holding clock signals respectively, and respectively serve as the sampling clock and holding clock of the n sampling phase detectors to perform sampling phase detection on the n reference clock signals to obtain n phase detection results; the n phase detection results are filtered out by the high-frequency parallel-to-serial high-pass filter to remove the DC mismatch in the n phase detection results, to obtain high-frequency phase detection information with low loop delay, and to achieve the effect of the proportional control path in the high frequency band; at the same time, one of the phase detection results is passed through the transconductance amplifier whose load is the filter capacitor to achieve the effect of the integral control path; the proportional control path and the integral control path respectively control the two control ends of the voltage-controlled oscillator.

[0007] Furthermore, the transconductance amplifier is a transconductance amplifier using a gain boost technology.

[0008] Furthermore, the sampling phase detector is a switching current sampling phase detector.

[0009] The beneficial effects of the present invention are as follows:

[0010] (1) In the multi-phase sampling proportional integral dual-path phase-locked loop of the present invention, the parallel-to-serial high-frequency filter combines the high-frequency information in the multi-path phase-locked loop information into one path, realizing the effect of the proportional control path in the high-frequency band; one path of the phase-locked loop results passes through the transconductance amplifier whose load is the filter capacitor, realizing the effect of the integral control path; that is, the proportional integral dual-path control is adopted, which greatly reduces the area of ​​the loop filter. And because the bias voltage of the high-frequency parallel-to-serial high-pass filter is determined, the proportional path basically does not affect the locking point of the loop, and the loop locking point is determined by the integral path. In this way, the relatively inaccurate multi-phase reference clock input signal can be used to realize the equivalent frequency multiplication of the phase-locked loop phase-locked loop frequency, and the loop bandwidth can be expanded, while avoiding the deterioration of the output reference spurious caused by the input reference clock phase error.

[0011] (2) The present invention reduces the requirement for reference clock phase accuracy in traditional reference clock frequency multiplication technology, thereby greatly simplifying the design of multi-phase reference clock circuits.

[0012] (3) The present invention can expand the loop bandwidth of the phase-locked loop, thereby suppressing more oscillator noise.

[0013] (4) The present invention adopts a multi-phase sampling phase-locked loop, so that the timing requirements and power consumption in the multi-phase sampling phase-locked loop are relatively reduced compared to the traditional phase-locked loop with high-frequency reference clock signal input. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a system architecture diagram of the present invention.

[0015] Figure 2 It is a high-frequency parallel-to-series high-pass filter.

[0016] Figure 3 This is a schematic diagram of the waveform of a multi-phase sampling phase-locked loop (taking four phases as an example). DETAILED DESCRIPTION

[0017] The present invention will be described in detail below based on the accompanying drawings and preferred embodiments, and the purpose and effects of the present invention will become more clear. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0018] like Figure 1 As shown, the multi-phase sampling proportional integral dual-path phase-locked loop of the present invention includes a multi-path sampling phase detector, a high-frequency parallel-to-serial high-pass filter, a transconductance amplifier, a filter capacitor, a voltage-controlled oscillator and a multi-phase frequency divider. ref <n:1>is the n-way multi-phase reference clock signal, ck samp <n:1>is the n-channel multi-phase sampling clock signal, ck hold <n:1>is an n-way multi-phase non-overlapping clock signal, V C,I is the integral control path control signal of the voltage controlled oscillator, V C,P is the proportional control path control signal of the voltage controlled oscillator, ck VCO is the voltage controlled oscillator output clock signal, and n is a positive integer.

[0019] like Figure 2 As shown, the high-frequency parallel-to-serial high-pass filter includes n-channel switching capacitors and a bias resistor, one end of the n-channel switching capacitors serves as the input end of the n-channel phase-discrimination information, and the other end is connected to one end of the bias resistor; the other end of the bias resistor is connected to the bias voltage; wherein the n-channel switching capacitors are respectively turned on by n-channel non-overlapping holding clocks, so as to realize the parallel conversion of the high-frequency information in the n-channel phase-discrimination information into one channel.

[0020] like Figure 1 As shown, the multi-phase frequency divider divides the frequency of the high-frequency output signal of the voltage-controlled oscillator to generate n sampling clock signals and n holding clock signals respectively, and respectively serve as the sampling clock and holding clock of the n sampling phase detectors to perform sampling phase detection on the n reference clock signals to obtain n phase detection results; the n phase detection results are filtered out by a high-frequency parallel-to-serial high-pass filter to remove the DC mismatch in the n phase detection results, to obtain high-frequency phase detection information with low loop delay, and to achieve the effect of the proportional control path in the high frequency band; at the same time, one of the phase detection results is passed through the transconductance amplifier whose load is the filter capacitor to achieve the effect of the integral control path; the proportional control path and the integral control path respectively control the two control ends of the voltage-controlled oscillator.

[0021] Preferably, the transconductance amplifier is a transconductance amplifier using a gain enhancement technology. The sampling phase detector is a switching current sampling phase detector.

[0022] Here we take a four-phase clock input as an example, of course other numbers of multi-phase reference clock inputs are also possible.

[0023] The waveforms of each node of the four-phase sampling phase-locked loop are as follows Figure 3 As shown in the figure, here we take the falling edge sampling as an example, of course, the rising edge sampling is similar. Figure 3 It can be seen that in one reference clock cycle, the multi-channel sampling phase detectors perform phase detection multiple times, thus achieving an increase in the phase detection frequency. At the same time, after the sampling of each sampling phase detector is completed, the holding clock immediately holds the sampled signal and updates it to the high-frequency parallel-to-serial high-pass filter, thus avoiding loop delay. However, due to the characteristics of zero-order hold sampling, as the hold time increases, the phase shift of the loop will increase, so it is necessary to use the parallel-to-serial method to reduce the hold time in the multi-phase sampling phase-locked loop accordingly, which is achieved here by a high-frequency parallel-to-serial high-pass filter.

[0024] Ideally, the mismatch between multi-phase reference signals can be considered as an offset from DC to low frequency, and it changes slowly with non-ideal factors such as temperature. Due to this characteristic of mismatch, the low-frequency offset can be filtered out by high-pass filtering, so that only high-frequency useful signals can be obtained. Generally speaking, the output jitter of the phase-locked loop is mainly determined by the phase noise in the range of one-tenth of the loop bandwidth to ten times the loop bandwidth, so the high-frequency phase-locked information is the key. The deviation between the multi-channel phase-locked information of the low-frequency phase-locked results can be ignored, so it can be considered that the low-frequency signals of each phase-locked result are actually the same. And the bias voltage of each high-pass filter is the same, so the resistance of the high-frequency filter can be shared, so that each high-pass filter reuses the same bias resistor, and the high-frequency phase-locked information is converted from parallel to serial through multi-channel selection, which can greatly reduce the area of ​​the bias resistor. At the same time, the phase-locked loop also needs to provide a low-frequency loop gain to achieve frequency and phase locking of the phase-locked loop. Therefore, one of the multi-phase phase-locked loop results is taken out and passed through a transconductance amplifier to realize the integral path and provide a low-frequency loop gain. In this way, the relatively inaccurate multi-phase reference clock input signal can be used to achieve an equivalent frequency multiplication of the phase-locked loop phase-locked loop frequency, and the loop bandwidth can be expanded, while avoiding the deterioration of the output reference spurious caused by the input reference clock phase error.

[0025] At the same time, this design adopts proportional-integral dual-path control, which greatly reduces the area of ​​the loop filter. And because the bias voltage of the high-frequency parallel-to-series high-pass filter is determined, the proportional path basically does not affect the locking point of the loop, and the loop locking point is determined by the integral path.

[0026] Those skilled in the art can understand that the above are only preferred examples of the invention and are not intended to limit the invention. Although the invention is described in detail with reference to the above examples, those skilled in the art can still modify the technical solutions recorded in the above examples or replace some of the technical features therein with equivalents. Any modification, equivalent replacement, etc. made within the spirit and principle of the invention shall be included in the protection scope of the invention.

Claims

1. A multi-phase sampling proportional integral dual-path phase-locked loop, characterized in that: It includes n-channel sampling phase detector, high-frequency parallel-to-serial high-pass filter, transconductance amplifier, filter capacitor, voltage-controlled oscillator and multi-phase frequency divider; n is a positive integer; The high-frequency parallel-to-serial high-pass filter comprises n-channel switching capacitors and a bias resistor, wherein one end of the n-channel switching capacitors is used as an input end of the n-channel phase-discrimination information, and the other end is connected to one end of the bias resistor; the other end of the bias resistor is connected to a bias voltage; wherein the n-channel switching capacitors are respectively turned on by n-channel non-overlapping holding clocks, so as to realize parallel-to-serial conversion of the high-frequency information in the n-channel phase-discrimination information into one channel; The multi-phase frequency divider divides the frequency of the high-frequency output signal of the voltage-controlled oscillator to generate n sampling clock signals and n holding clock signals respectively, and respectively serve as the sampling clock and holding clock of the n sampling phase detectors to perform sampling phase detection on the n reference clock signals to obtain n phase detection results; the n phase detection results are filtered out by the high-frequency parallel-to-serial high-pass filter to remove the DC mismatch in the n phase detection results, to obtain high-frequency phase detection information with low loop delay, and to achieve the effect of the proportional control path in the high frequency band; at the same time, one of the phase detection results is passed through the transconductance amplifier whose load is the filter capacitor to achieve the effect of the integral control path; the proportional control path and the integral control path respectively control the two control ends of the voltage-controlled oscillator.

2. The multi-phase sampling proportional-integral dual-path phase-locked loop according to claim 1, characterized in that: The transconductance amplifier is a gain-enhanced transconductance amplifier.

3. The multi-phase sampling proportional-integral dual-path phase-locked loop according to claim 1, characterized in that: The sampling phase detector is a switching current sampling phase detector.

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