A bandgap reference circuit with self-buffered loop control technology

Abstract

The present invention claims a bandgap reference source circuit of self-buffered loop control technology, including a startup circuit, a bias circuit and a bandgap reference core circuit. The present invention utilizes PNP transistors Q5, PNP transistors Q6 and other related circuits to generate a positive temperature coefficient voltage and weights the base-emitter voltage of NPN transistor Q4 to generate a low-temperature drift bandgap reference output voltage, utilizes the negative feedback loop technology of self-buffered loop control to suppress the voltage change at the output end of the bandgap reference source circuit, improves the adjustment speed of the bandgap reference source circuit loop, utilizes the current compensation circuit to increase the current flowing through resistors R13 and R14, effectively suppresses the influence of mismatch caused by different current amplification factors of PNP transistors at different process angles and temperatures on the bandgap reference output voltage, and then obtains a high-performance bandgap reference voltage, thereby realizing a bandgap reference source circuit of self-buffered loop control technology.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a bandgap reference source circuit of a self-buffered loop control technology. Background Art

[0002] Bandgap reference voltage sources (BGR) are widely used in analog-to-digital converters (ADCs), low-dropout linear regulators (LDOs), DC-DC circuits, etc. due to their low temperature coefficient characteristics. As integrated circuit functions and applications become increasingly complex, traditional bandgap reference voltage sources are difficult to meet the requirements of modern high-precision systems.

[0003] Figure 1 It is a traditional bandgap reference circuit structure. All resistors are made of the same material. Resistor R3 is exactly the same as resistor R4. The emitter area of ​​NPN transistor Q1 is N times that of NPN transistor Q2. The low-frequency gain of amplifier A1 is A. d A d >>1, the output voltage V of the bandgap reference circuit bg for Among them, V BE2 is the base-emitter voltage of NPN transistor Q2, R 1 is the impedance of resistor R1, R 2 is the impedance of resistor R2, q is the electron charge, k is the Boltzmann constant, and T is the absolute temperature. By optimizing the resistance values ​​of resistors R1 and R2 and parameter N, at temperature T r Where to get Since the output voltage of the traditional first-order bandgap reference circuit has a high temperature drift coefficient problem, the application of the traditional first-order bandgap reference circuit in high-precision systems is limited. Summary of the invention

[0004] The present invention aims to solve the above problems of the prior art. A bandgap reference source circuit with a self-buffered loop control technology is proposed. The technical solution of the present invention is as follows:

[0005] A bandgap reference source circuit of a self-buffered loop control technology comprises: a start-up circuit, a bias circuit and a bandgap reference core circuit, wherein the signal output end of the start-up circuit is connected to the signal input end of the bias circuit, and the signal output end of the bias circuit is respectively connected to the signal input ends of the start-up circuit and the bandgap reference core circuit; the start-up circuit mainly uses a PMOS transistor MP1, a PMOS transistor MP2 and a resistor R1 to enable the bandgap reference source circuit to work normally and generate a bandgap reference voltage output; the bias circuit mainly uses an NPN transistor Q1, an NPN transistor Q2, a resistor R5, an NMOS transistor MN1, an NMOS transistor MN2 and a PMOS transistor MP5 to provide a bias voltage signal for the bandgap reference core circuit; and the bandgap reference core circuit mainly uses a PNP transistor Q5, a PNP transistor Q6, a resistor R15, a resistor R11, a resistor R9, an NPN transistor Q4, a resistor R8 and a resistor R16 to generate a bandgap reference voltage.

[0006] Furthermore, the startup circuit includes: a PMOS tube MP1, a PMOS tube MP2 and a resistor R1, wherein the source of the PMOS tube MP2 is respectively connected to the source of the PMOS tube MP1 and the external power supply VDD, the gate of the PMOS tube MP2 is respectively connected to the gate of the PMOS tube MP3, the gate of the PMOS tube MP4, the drain of the PMOS tube MP4 and the collector of the NPN transistor Q2, the drain of the PMOS tube MP2 is respectively connected to the gate of the PMOS tube MP1 and one end of the resistor R1, and the other end of the resistor R1 is connected to the external ground GND.

[0007] Further, the bias circuit includes: a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, an NMOS tube MN1, an NMOS tube MN2, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, an NPN transistor Q1, an NPN transistor Q2 and an NPN transistor Q3, wherein one end of the resistor R2 is respectively connected to one end of the resistor R6, one end of the resistor R7 and an external power supply VDD, the other end of the resistor R2 is connected to the source of the PMOS tube MP3, the drain of the PMOS tube MP3 is respectively connected to the drain of the PMOS tube MP1, the collector of the NPN transistor Q1, the base of the NPN transistor Q1 and the base of the NPN transistor Q2, the other end of the resistor R6 is connected to the source of the PMOS tube MP4, the collector of the NPN transistor Q2 is connected to the base of the NPN transistor Q1 and the base of the NPN transistor Q2. The emitter is connected to one end of the resistor R5, the other end of the resistor R5 is respectively connected to the emitter of the NPN transistor Q1, the drain of the NMOS transistor MN1, the gate of the NMOS transistor MN1 and the gate of the NMOS transistor MN2, the source of the NMOS transistor MN1 is connected to one end of the resistor R3, the other end of the resistor R7 is connected to the source of the PMOS transistor MP5, the gate of the PMOS transistor MP5 is respectively connected to the gate of the PMOS transistor MP6, the gate of the PMOS transistor MP7, the drain of the PMOS transistor MP5, the collector of the NPN transistor Q3 and the base of the NPN transistor Q3, the emitter of the NPN transistor Q3 is connected to the drain of the NMOS transistor MN2, the source of the NMOS transistor MN2 is connected to one end of the resistor R4, and the other end of the resistor R4 is respectively connected to the other end of the resistor R3 and the external electrical ground GND.

[0008] Further, the bandgap reference core circuit includes: an operational amplifier A1, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, an NPN transistor Q4, a PNP transistor Q5, a PNP transistor Q6, a PNP transistor Q7, a PNP transistor Q8, an NPN transistor Q9, a PMOS transistor MP6, a PMOS transistor MP7 and a PMOS transistor MP8, wherein the source of the PMOS transistor MP8 is respectively connected to one end of the resistor R19, one end of the resistor R20 and an external The gate of the PMOS tube MP8 is connected to the output end of the operational amplifier A1, the drain of the PMOS tube MP8 is respectively connected to the output end VREF of the bandgap reference, one end of the resistor R16, the collector of the NPN transistor Q4, the base of the NPN transistor Q9 and the collector of the NPN transistor Q9, the other end of the resistor R16 is respectively connected to one end of the resistor R8 and the base of the NPN transistor Q4, the emitter of the NPN transistor Q4 is respectively connected to one end of the resistor R11 and one end of the resistor R15, the other end of the resistor R15 is connected to the base of the PNP transistor Q5, the other end of the resistor R11 is respectively connected to the resistor R11 and ... One end of resistor R9 is connected to the base of PNP transistor Q6, the emitter of NPN transistor Q9 is respectively connected to the base of PNP transistor Q7, the base of PNP transistor Q8 and one end of resistor R12, the other end of resistor R19 is connected to the source of PMOS tube MP6, the drain of PMOS tube MP6 is respectively connected to the emitter of PNP transistor Q5 and the emitter of PNP transistor Q6, the collector of PNP transistor Q5 is respectively connected to the collector of PNP transistor Q7, one end of resistor R13 and the inverting input end of operational amplifier A1, the collector of PNP transistor Q6 is respectively connected to one end of resistor R14, the base of PNP transistor Q8 and one end of resistor R16. The collector of the P transistor Q8 is connected to the non-inverting input terminal of the operational amplifier A1, the other end of the resistor R13 is respectively connected to one end of the resistor R10 and the other end of the resistor R14, the other end of the resistor R10 is respectively connected to the other end of the resistor R8, the other end of the resistor R9, the other end of the resistor R12 and the external ground GND, the other end of the resistor R20 is connected to the source of the PMOS tube MP7, the drain of the PMOS tube MP7 is respectively connected to one end of the resistor R17 and one end of the resistor R18, the other end of the resistor R17 is connected to the emitter of the PNP transistor Q7, and the other end of the resistor R18 is connected to the emitter of the PNP transistor Q8.

[0009] Furthermore, in the bias circuit, the resistors R2, R3, R4, R5, R6, and R7 are made of the same material, the emitter area of ​​the NPN transistor Q2 is m times that of the NPN transistor Q1, and the PMOS transistor MP3 and the PMOS transistor MP4 have the same channel width-to-length ratio, so the NPN transistor Q1 and the NPN transistor Q2 have the same collector current, and the current I flowing through the resistor R5 is R5 For I R5 =(V T lnm) / R 5 , where R 5 is the resistance value of resistor R5, V T is the thermal voltage; NMOS tube MN1 and NMOS tube MN2 have the same channel width-to-length ratio, resistor R3 and resistor R4 are exactly the same, then the drain current I of PMOS tube MP5 P5 Yes P5 =2I R5 , which provides bias for the bandgap reference core circuit.

[0010] Furthermore, in the bandgap reference core circuit, all resistors R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19 and R20 are made of the same material, and the operational amplifier A1, PMOS tube MP8, resistor R16, resistor R8, NPN transistor Q4, resistor R11, resistor R9, resistor R15, PNP transistor Q5 and PNP transistor Q6 are made of the same material. A self-buffered loop control structure is formed. When the voltage VREF at the output terminal of the bandgap reference circuit increases, the base voltage of the NPN transistor Q4 increases, the base voltage of the PNP transistor Q5 increases, the collector voltage of the PNP transistor Q5 decreases, the voltage at the reverse input terminal of the operational amplifier A1 decreases, the gate voltage of the PMOS tube MP8 increases, and the voltage VREF at the output terminal of the bandgap reference circuit decreases, thereby suppressing the increase of the voltage VREF at the output terminal of the bandgap reference circuit, thereby realizing the negative feedback loop function of the self-buffered loop control.

[0011] Furthermore, in the bandgap reference core circuit, NPN transistor Q9, PNP transistor Q7, PNP transistor Q8, resistor R17, resistor R18, resistor R12, resistor R19, resistor R20, PMOS transistor MP6 and PMOS transistor MP7 constitute a current compensation circuit, wherein NPN transistor Q9 and resistor R12 provide bias voltage for PNP transistor Q7 and PNP transistor Q8, thereby increasing the current flowing through resistor R13 and resistor R14, thereby effectively suppressing the influence of mismatch caused by different current amplification factors of PNP transistors at different process angles and temperatures on the bandgap reference output voltage.

[0012] Furthermore, in the bandgap reference core circuit, the low-frequency gain of the amplifier A1 is much greater than 1, the emitter area of ​​the PNP transistor Q5 is n times that of the PNP transistor Q6, the resistor R13 is exactly the same as the resistor R14, the resistor R17 is exactly the same as the resistor R18, the PNP transistor Q7 is exactly the same as the PNP transistor Q8, the PNP transistor Q6 and the PNP transistor Q5 have the same current amplification factor, the current amplification factor of the NPN transistor Q4 is much greater than 1, the PNP transistor Q5, the PNP transistor Q6, the resistor R15 and the resistor R11 constitute a base current compensation circuit, and the resistance values ​​of the resistors R9, R11 and R15 are optimized to make R 9 -R 15 -(R 9 R 15 ) / R 11 =0, the circuit outputs the output voltage V of VREF REF V REF =(R 8 +R 16 )[(1+R 9 / R 11 )V T lnn+V BE4 ] / R 8 , where R 8 is the resistance value of resistor R8, R 9 is the resistance value of R9, R 11 is the resistance value of R1, R 15 is the resistance value of R15, R 16 is the resistance value of resistor R16, V BE4 is the base-emitter voltage of NPN transistor Q4, V T is the thermal voltage, the thermal voltage V T Positive temperature characteristic, voltage V BE4 It has negative temperature characteristics. By optimizing the resistance value of resistor R9, the resistance value of resistor R11 and the parameter n, at room temperature T r Where to get Thus, a high-performance bandgap reference voltage with low-temperature characteristics is achieved, wherein T is the absolute temperature.

[0013] The advantages and beneficial effects of the present invention are as follows:

[0014] The present invention provides a bandgap reference source circuit of a self-buffered loop control technology, utilizes PNP transistors Q5, PNP transistors Q6 and other related circuits to generate a positive temperature coefficient voltage and performs weighting with the base-emitter voltage of NPN transistor Q4 to generate a low-temperature drift bandgap reference output voltage, and adopts a negative feedback loop that realizes self-buffered loop control by an operational amplifier A1, a PMOS transistor MP8, a resistor R16, a resistor R8, an NPN transistor Q4, a resistor R11, a resistor R9, a resistor R15, a PNP transistor Q5 and a PNP transistor Q6 to suppress the bandgap reference circuit. The voltage at the output end VREF changes, and the adjustment speed of the bandgap reference circuit loop is improved. A current compensation circuit is formed by NPN transistor Q9, PNP transistor Q7, PNP transistor Q8, resistor R17, resistor R18, resistor R12, resistor R19, resistor R20, PMOS transistor MP6 and PMOS transistor MP7 to increase the current flowing through resistor R13 and resistor R14, thereby effectively suppressing the influence of mismatch caused by different current amplification factors of PNP transistors at different process angles and temperatures on the bandgap reference output voltage, thereby obtaining a high-performance bandgap reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is the schematic diagram of the traditional first-order bandgap reference circuit;

[0016] Figure 2 A schematic diagram of a bandgap reference source circuit of a self-buffered loop control technology for providing a preferred embodiment of the present invention;

[0017] Figure 3 The present invention provides a simulation diagram of the output voltage temperature characteristic of a bandgap reference source circuit of a self-buffered loop control technology according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will describe the technical solutions in the embodiments of the present invention in detail in conjunction with the accompanying drawings in the embodiments of the present invention. The described embodiments are only part of the embodiments of the present invention.

[0019] The technical solution of the present invention to solve the above technical problems is:

[0020] The embodiment of the present application utilizes PNP transistors Q5, PNP transistors Q6 and other related circuits to generate a positive temperature coefficient voltage and weights it with the base-emitter voltage of NPN transistor Q4 to generate a low-temperature drift bandgap reference output voltage, and adopts a negative feedback loop that realizes self-buffered loop control by operational amplifier A1, PMOS transistor MP8, resistor R16, resistor R8, NPN transistor Q4, resistor R11, resistor R9, resistor R15, PNP transistor Q5 and PNP transistor Q6 to suppress the voltage change of the output terminal VREF of the bandgap reference circuit. , improve the adjustment speed of the bandgap reference circuit loop, and use NPN transistor Q9, PNP transistor Q7, PNP transistor Q8, resistor R17, resistor R18, resistor R12, resistor R19, resistor R20, PMOS transistor MP6 and PMOS transistor MP7 to form a current compensation circuit to increase the current flowing through resistor R13 and resistor R14, thereby effectively suppressing the influence of mismatch caused by different current amplification factors of PNP transistors at different process angles and temperatures on the bandgap reference output voltage, thereby obtaining a high-performance bandgap reference voltage.

[0021] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0022] Example

[0023] A bandgap reference source circuit with self-buffered loop control technology, such as Figure 2 As shown, it includes a startup circuit 1, a bias circuit 2 and a bandgap reference core circuit 3;

[0024] Among them, the signal output end of the start-up circuit 1 is connected to the signal input end of the bias circuit 2, and the signal output end of the bias circuit 2 is respectively connected to the signal input ends of the start-up circuit 1 and the bandgap reference core circuit 3; the start-up circuit 1 enables the bandgap reference circuit to work normally and generate a bandgap reference voltage output, and the bias circuit 2 provides a bias voltage signal for the bandgap reference core circuit 3. The bandgap reference core circuit 3 adopts a technology of a self-buffered loop control structure composed of an operational amplifier A1, a PMOS tube MP8, a resistor R16, a resistor R8, an NPN transistor Q4, a resistor R11, a resistor R9, a resistor R15, a PNP transistor Q5 and a PNP transistor Q6 to obtain a high-performance bandgap reference voltage with a low temperature drift coefficient.

[0025] The startup circuit 1 works only when the bandgap reference circuit is powered on. When the bandgap reference circuit is started up, the startup circuit stops working, thereby avoiding the influence of the startup circuit on the subsequent circuits.

[0026] As a preferred technical solution, Figure 2As shown, the startup circuit 1 includes: a PMOS tube MP1, a PMOS tube MP2 and a resistor R1, wherein the source of the PMOS tube MP2 is respectively connected to the source of the PMOS tube MP1 and the external power supply VDD, the gate of the PMOS tube MP2 is respectively connected to the gate of the PMOS tube MP3, the gate of the PMOS tube MP4, the drain of the PMOS tube MP4 and the collector of the NPN transistor Q2, the drain of the PMOS tube MP2 is respectively connected to the gate of the PMOS tube MP1 and one end of the resistor R1, and the other end of the resistor R1 is connected to the external ground GND.

[0027] The bias circuit 2 includes: a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, an NMOS tube MN1, an NMOS tube MN2, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, an NPN transistor Q1, an NPN transistor Q2 and an NPN transistor Q3, wherein one end of the resistor R2 is respectively connected to one end of the resistor R6, one end of the resistor R7 and an external power supply VDD, the other end of the resistor R2 is connected to the source of the PMOS tube MP3, the drain of the PMOS tube MP3 is respectively connected to the drain of the PMOS tube MP1, the collector of the NPN transistor Q1, the base of the NPN transistor Q1 and the base of the NPN transistor Q2, the other end of the resistor R6 is connected to the source of the PMOS tube MP4, the emitter of the NPN transistor Q2 is connected to the emitter of the NPN transistor Q3 and the emitter of the NPN transistor Q4 is connected to the emitter of the NPN transistor Q5. The first transistor MN1 is connected to one end of the resistor R5, the other end of the resistor R5 is respectively connected to the emitter of the NPN transistor Q1, the drain of the NMOS transistor MN1, the gate of the NMOS transistor MN1 and the gate of the NMOS transistor MN2, the source of the NMOS transistor MN1 is connected to one end of the resistor R3, the other end of the resistor R7 is connected to the source of the PMOS transistor MP5, the gate of the PMOS transistor MP5 is respectively connected to the gate of the PMOS transistor MP6, the gate of the PMOS transistor MP7, the drain of the PMOS transistor MP5, the collector of the NPN transistor Q3 and the base of the NPN transistor Q3, the emitter of the NPN transistor Q3 is connected to the drain of the NMOS transistor MN2, the source of the NMOS transistor MN2 is connected to one end of the resistor R4, and the other end of the resistor R4 is respectively connected to the other end of the resistor R3 and the external electrical ground GND.

[0028] The bandgap reference core circuit 3 includes: an operational amplifier A1, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, an NPN transistor Q4, a PNP transistor Q5, a PNP transistor Q6, a PNP transistor Q7, a PNP transistor Q8, an NPN transistor Q9, a PMOS transistor MP6, a PMOS transistor MP7 and a PMOS transistor MP8, wherein the source of the PMOS transistor MP8 is respectively connected to one end of the resistor R19, one end of the resistor R20 and an external power supply VDD is connected, the gate of the PMOS tube MP8 is connected to the output end of the operational amplifier A1, the drain of the PMOS tube MP8 is respectively connected to the output end VREF of the bandgap reference, one end of the resistor R16, the collector of the NPN transistor Q4, the base of the NPN transistor Q9 and the collector of the NPN transistor Q9, the other end of the resistor R16 is respectively connected to one end of the resistor R8 and the base of the NPN transistor Q4, the emitter of the NPN transistor Q4 is respectively connected to one end of the resistor R11 and one end of the resistor R15, the other end of the resistor R15 is connected to the base of the PNP transistor Q5, the other end of the resistor R11 is respectively connected to the resistor R 9 is connected to one end of the PNP transistor Q6, the emitter of the NPN transistor Q9 is respectively connected to the base of the PNP transistor Q7, the base of the PNP transistor Q8 and one end of the resistor R12, the other end of the resistor R19 is connected to the source of the PMOS transistor MP6, the drain of the PMOS transistor MP6 is respectively connected to the emitter of the PNP transistor Q5 and the emitter of the PNP transistor Q6, the collector of the PNP transistor Q5 is respectively connected to the collector of the PNP transistor Q7, one end of the resistor R13 and the inverting input terminal of the operational amplifier A1, the collector of the PNP transistor Q6 is respectively connected to one end of the resistor R14, the PNP transistor Q8 and the base of the PNP transistor Q9, the emitter of the NPN transistor Q9 is respectively connected to the base of the PNP transistor Q7, the base of the PNP transistor Q8 and one end of the resistor R12, the other end of the resistor R19 is respectively connected to the source of the PMOS transistor MP6, the drain of the PMOS transistor MP6 is respectively connected to the emitter of the PNP transistor Q5 and the emitter of the PNP transistor Q6, the collector of the PNP transistor Q5 is respectively connected to the collector of the PNP transistor Q7, one end of the resistor R13 and the inverting input terminal of the operational amplifier A1, the collector of the PNP transistor Q6 is respectively connected to one end of the resistor R14, the PNP transistor Q8 and the base of the PNP transistor Q9. The collector of the transistor Q8 is connected to the non-inverting input terminal of the operational amplifier A1, the other end of the resistor R13 is respectively connected to one end of the resistor R10 and the other end of the resistor R14, the other end of the resistor R10 is respectively connected to the other end of the resistor R8, the other end of the resistor R9, the other end of the resistor R12 and the external ground GND, the other end of the resistor R20 is connected to the source of the PMOS tube MP7, the drain of the PMOS tube MP7 is respectively connected to one end of the resistor R17 and one end of the resistor R18, the other end of the resistor R17 is connected to the emitter of the PNP transistor Q7, and the other end of the resistor R18 is connected to the emitter of the PNP transistor Q8.

[0029] The operational amplifier A1 in the bandgap reference core circuit 3 is prior art.

[0030] In the bias circuit 2, all resistors are made of the same material, the emitter area of ​​the NPN transistor Q2 is m times that of the NPN transistor Q1, and the PMOS transistor MP3 and the PMOS transistor MP4 have the same channel width-to-length ratio, so the NPN transistor Q1 and the NPN transistor Q2 have the same collector current. Then, the current I flowing through the resistor R5 R5 for

[0031]

[0032] Among them, R 5 is the resistance value of resistor R5, V T is the thermal voltage. NMOS tube MN1 and NMOS tube MN2 have the same channel width-to-length ratio, and resistor R3 and resistor R4 are exactly the same, then the drain current I of PMOS tube MP5 P5 Yes P5 =2I R5 , which provides bias for the bandgap reference core circuit 3.

[0033] In the bandgap reference core circuit 3, all resistors are made of the same material, and the operational amplifier A1, the PMOS tube MP8, the resistor R16, the resistor R8, the NPN transistor Q4, the resistor R11, the resistor R9, the resistor R15, the PNP transistor Q5 and the PNP transistor Q6 constitute a self-buffered loop control structure. When the voltage at the output end VREF of the bandgap reference circuit increases, the base voltage of the NPN transistor Q4 increases, the base voltage of the PNP transistor Q5 increases, the collector voltage of the PNP transistor Q5 decreases, the reverse input terminal voltage of the operational amplifier A1 decreases, the gate voltage of the PMOS tube MP8 increases, and the voltage at the output end VREF of the bandgap reference circuit decreases, thereby suppressing the increase of the voltage at the output end VREF of the bandgap reference circuit, thereby realizing the negative feedback loop function of the self-buffered loop control and improving the adjustment speed of the circuit loop; the NPN transistor Q9, the PNP transistor The transistor Q7, the PNP transistor Q8, the resistor R17, the resistor R18, the resistor R12, the resistor R19, the resistor R20, the PMOS transistor MP6 and the PMOS transistor MP7 constitute a current compensation circuit, wherein the NPN transistor Q9 and the resistor R12 provide bias voltages for the PNP transistor Q7 and the PNP transistor Q8, thereby increasing the current flowing through the resistor R13 and the resistor R14, thereby effectively suppressing the influence of the mismatch caused by the different current amplification factors of the PNP transistors at different process angles and temperatures on the bandgap reference output voltage; the emitter area of ​​the PNP transistor Q5 is n times that of the PNP transistor Q6, the resistor R13 is exactly the same as the resistor R14, the amplifier A1 is the prior art and the low-frequency gain is much greater than 1, the PNP transistor Q5, the PNP transistor Q6, the resistor R15 and the resistor R11 constitute a base current compensation circuit, then the base voltage V B5And the base voltage V of PNP tube Q6 B6 have

[0034] V B5 -V B6 =V T lnn (2)

[0035] Among them, V T is the thermal voltage; the emitter voltage V E4 have

[0036]

[0037] Among them, R 9 is the resistance value of resistor R9, I B6 is the base current of PNP transistor Q6, I B5 is the base current of PNP transistor Q5, R 11 is the resistance value of resistor R11, R 15 is the resistance value of resistor R15; resistor R17 is exactly the same as resistor R18, PNP transistor Q7 is exactly the same as PNP transistor Q8, PNP transistor Q6 and PNP transistor Q5 have the same current amplification factor, then PNP transistor Q6 and PNP transistor Q5 have the same base current (i.e., I B6 =I B5 ), by optimizing the resistance values ​​of resistors R9, R11 and R15, R 9 -R 15 -(R 9 R 15 ) / R 11 =0, then the emitter voltage V E4 Approximately

[0038]

[0039] The current amplification factor of NPN transistor Q4 is much greater than 1, so the output voltage V REF for

[0040]

[0041] Among them, R 8 is the resistance value of resistor R8, R 16 is the resistance value of resistor R16, V BE4 is the base-emitter voltage of NPN transistor Q4. In formula (5), the thermal voltage V T With positive temperature characteristics, the base-emitter voltage V BE4It has a negative temperature characteristic, so by optimizing the resistance value of the resistor R9, the resistance value of the resistor R11 and the parameter n, a bandgap reference voltage with a low temperature characteristic can be obtained.

[0042] Figure 3 The output voltage V of the bandgap reference source circuit of the self-buffered loop control technology of the present invention is ref The temperature characteristic simulation curve of the bandgap reference circuit is shown in Figure 1, where the horizontal axis is the temperature T and the vertical axis is the output voltage of the bandgap reference circuit. The simulation results show that within the temperature range of -45℃ to 125℃, the output voltage V REF The temperature coefficient is only 1.807ppm / ℃.

[0043] In the above embodiment of the present application, a bandgap reference source circuit of self-buffered loop control technology includes a startup circuit, a bias circuit and a bandgap reference core circuit. The embodiment of the present application utilizes PNP transistor Q5, PNP transistor Q6 and other related circuits to generate a positive temperature coefficient voltage and weights it with the base-emitter voltage of NPN transistor Q4 to generate a low-temperature drift bandgap reference output voltage, and adopts a negative feedback loop that realizes self-buffered loop control by operational amplifier A1, PMOS tube MP8, resistor R16, resistor R8, NPN transistor Q4, resistor R11, resistor R9, resistor R15, PNP transistor Q5 and PNP transistor Q6 to suppress the voltage change of the output terminal VREF of the bandgap reference circuit. , improve the adjustment speed of the bandgap reference circuit loop, and use NPN transistor Q9, PNP transistor Q7, PNP transistor Q8, resistor R17, resistor R18, resistor R12, resistor R19, resistor R20, PMOS transistor MP6 and PMOS transistor MP7 to form a current compensation circuit to increase the current flowing through resistor R13 and resistor R14, thereby effectively suppressing the influence of mismatch caused by different current amplification factors of PNP transistors at different process angles and temperatures on the bandgap reference output voltage, thereby obtaining a high-performance bandgap reference voltage.

[0044] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0045] The above embodiments should be understood to be only used to illustrate the present invention and not to limit the protection scope of the present invention. After reading the contents of the present invention, technicians can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A bandgap reference source circuit of self-buffered loop control technology, characterized in that: include: A start-up circuit (1), a bias circuit (2) and a bandgap reference core circuit (3), wherein the signal output end of the start-up circuit (1) is connected to the signal input end of the bias circuit (2), and the signal output end of the bias circuit (2) is respectively connected to the signal input ends of the start-up circuit (1) and the bandgap reference core circuit (3); the start-up circuit (1) mainly uses a PMOS transistor MP1, a PMOS transistor MP2 and a resistor R1 to enable the bandgap reference source circuit to work normally and generate a bandgap reference voltage output; the bias circuit (2) mainly uses an NPN transistor Q1, an NPN transistor Q2, a resistor R5, an NMOS transistor MN1, an NMOS transistor MN2 and a PMOS transistor MP5 to provide a bias voltage signal for the bandgap reference core circuit (3); and the bandgap reference core circuit (3) mainly uses a PNP transistor Q5, a PNP transistor Q6, a resistor R15, a resistor R11, a resistor R9, an NPN transistor Q4, a resistor R8 and a resistor R16 to generate a bandgap reference voltage; The bandgap reference core circuit (3) comprises: an operational amplifier A1, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, an NPN transistor Q4, a PNP transistor Q5, a PNP transistor Q6, a PNP transistor Q7, a PNP transistor Q8, an NPN transistor Q9, a PMOS transistor MP6, a PMOS transistor MP7 and a PMOS transistor MP8, wherein the source of the PMOS transistor MP8 is connected to one end of the resistor R19, one end of the resistor R20 and an external The power supply VDD is connected, the gate of the PMOS tube MP8 is connected to the output end of the operational amplifier A1, the drain of the PMOS tube MP8 is respectively connected to the output end VREF of the bandgap reference, one end of the resistor R16, the collector of the NPN transistor Q4, the base of the NPN transistor Q9 and the collector of the NPN transistor Q9, the other end of the resistor R16 is respectively connected to one end of the resistor R8 and the base of the NPN transistor Q4, the emitter of the NPN transistor Q4 is respectively connected to one end of the resistor R11 and one end of the resistor R15, the other end of the resistor R15 is connected to the base of the PNP transistor Q5, the other end of the resistor R11 is respectively connected to the resistor One end of R9 is connected to the base of PNP transistor Q6, the emitter of NPN transistor Q9 is respectively connected to the base of PNP transistor Q7, the base of PNP transistor Q8 and one end of resistor R12, the other end of resistor R19 is connected to the source of PMOS transistor MP6, the drain of PMOS transistor MP6 is respectively connected to the emitter of PNP transistor Q5 and the emitter of PNP transistor Q6, the collector of PNP transistor Q5 is respectively connected to the collector of PNP transistor Q7, one end of resistor R13 and the inverting input end of operational amplifier A1, the collector of PNP transistor Q6 is respectively connected to one end of resistor R14, the drain of PMOS transistor MP6 is respectively connected to the emitter of PNP transistor Q5 and the emitter of PNP transistor Q6, the collector of PNP transistor Q5 is respectively connected to the collector of PNP transistor Q7, one end of resistor R13 and the inverting input end of operational amplifier A1, the collector of PNP transistor Q6 is respectively connected to one end of resistor R14, the drain of PNP transistor MP6 is respectively connected to the emitter of PNP transistor Q5 and the emitter of PNP transistor Q6. The collector of transistor Q8 is connected to the non-inverting input terminal of operational amplifier A1, the other end of resistor R13 is respectively connected to one end of resistor R10 and the other end of resistor R14, the other end of resistor R10 is respectively connected to the other end of resistor R8, the other end of resistor R9, the other end of resistor R12 and external ground GND, the other end of resistor R20 is connected to the source of PMOS transistor MP7, the drain of PMOS transistor MP7 is respectively connected to one end of resistor R17 and one end of resistor R18, the other end of resistor R17 is connected to the emitter of PNP transistor Q7, and the other end of resistor R18 is connected to the emitter of PNP transistor Q8; In the bandgap reference core circuit (3), all resistors R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19 and R20 are made of the same material, and the operational amplifier A1, PMOS tube MP8, resistor R16, resistor R8, NPN transistor Q4, resistor R11, resistor R9, resistor R15, PNP transistor Q5 and PNP transistor Q6 are constructed. A self-buffered loop control structure is formed. When the voltage of VREF at the output end of the bandgap reference circuit increases, the base voltage of the NPN transistor Q4 increases, the base voltage of the PNP transistor Q5 increases, the collector voltage of the PNP transistor Q5 decreases, the voltage of the reverse input end of the operational amplifier A1 decreases, the gate voltage of the PMOS tube MP8 increases, and the voltage of VREF at the output end of the bandgap reference circuit decreases, thereby suppressing the increase of the voltage of VREF at the output end of the bandgap reference circuit, thereby realizing the negative feedback loop function of the self-buffered loop control; In the bandgap reference core circuit (3), the NPN transistor Q9, the PNP transistor Q7, the PNP transistor Q8, the resistor R17, the resistor R18, the resistor R12, the resistor R19, the resistor R20, the PMOS transistor MP6 and the PMOS transistor MP7 constitute a current compensation circuit, wherein the NPN transistor Q9 and the resistor R12 provide a bias voltage for the PNP transistor Q7 and the PNP transistor Q8, thereby increasing the current flowing through the resistor R13 and the resistor R14, thereby effectively suppressing the influence of the mismatch caused by the different current amplification factors of the PNP transistors at different process angles and temperatures on the bandgap reference output voltage; In the bandgap reference core circuit (3), the low-frequency gain of the amplifier A1 is much greater than 1, the emitter area of ​​the PNP transistor Q5 is n times that of the PNP transistor Q6, the resistor R13 is completely identical to the resistor R14, the resistor R17 is completely identical to the resistor R18, the PNP transistor Q7 is completely identical to the PNP transistor Q8, the PNP transistor Q6 and the PNP transistor Q5 have the same current amplification factor, the current amplification factor of the NPN transistor Q4 is much greater than 1, the PNP transistor Q5, the PNP transistor Q6, the resistor R15 and the resistor R11 form a base current compensation circuit, and by optimizing the resistance values ​​of the resistors R9, R11 and R15, the R9-R 15 -(R9R 15 ) / R 11 =0, the circuit outputs the output voltage V of VREF REF V REF =(R8+R 16 )[(1+R9 / R 11 )V T lnn+V BE4 ] / R8, where R8 is the resistance value of resistor R8, R9 is the resistance value of resistor R9, R 11 is the resistance value of R1, R 15 is the resistance value of R15, R 16 is the resistance value of resistor R16, V BE4 is the base-emitter voltage of NPN transistor Q4, V T is the thermal voltage, the thermal voltage V T Positive temperature characteristic, voltage V BE4 It has negative temperature characteristics. By optimizing the resistance value of resistor R9, the resistance value of resistor R11 and the parameter n, at room temperature T r Where to get Thus, a high-performance bandgap reference voltage with low-temperature characteristics is achieved, wherein T is the absolute temperature.

2. The bandgap reference source circuit of the self-buffered loop control technology according to claim 1, characterized in that: The startup circuit (1) comprises: a PMOS tube MP1, a PMOS tube MP2 and a resistor R1, wherein the source of the PMOS tube MP2 is respectively connected to the source of the PMOS tube MP1 and an external power supply VDD, the gate of the PMOS tube MP2 is respectively connected to the gate of the PMOS tube MP3, the gate of the PMOS tube MP4, the drain of the PMOS tube MP4 and the collector of the NPN triode Q2, the drain of the PMOS tube MP2 is respectively connected to the gate of the PMOS tube MP1 and one end of the resistor R1, and the other end of the resistor R1 is connected to an external ground GND.

3. The bandgap reference source circuit of the self-buffered loop control technology according to claim 1, characterized in that: The bias circuit (2) comprises: a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, an NMOS tube MN1, an NMOS tube MN2, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, an NPN transistor Q1, an NPN transistor Q2 and an NPN transistor Q3, wherein one end of the resistor R2 is respectively connected to one end of the resistor R6, one end of the resistor R7 and an external power supply VDD, the other end of the resistor R2 is connected to the source of the PMOS tube MP3, the drain of the PMOS tube MP3 is respectively connected to the drain of the PMOS tube MP1, the collector of the NPN transistor Q1, the base of the NPN transistor Q1 and the base of the NPN transistor Q2, the other end of the resistor R6 is connected to the source of the PMOS tube MP4, the emitter of the NPN transistor Q2 is connected to the emitter of the NPN transistor Q3 and the collector of the NPN transistor Q4 is connected to the collector of the NPN transistor Q5. The first electrode of the resistor R7 is connected to one end of the resistor R5, the other end of the resistor R5 is respectively connected to the emitter of the NPN transistor Q1, the drain of the NMOS transistor MN1, the gate of the NMOS transistor MN1 and the gate of the NMOS transistor MN2, the source of the NMOS transistor MN1 is connected to one end of the resistor R3, the other end of the resistor R7 is connected to the source of the PMOS transistor MP5, the gate of the PMOS transistor MP5 is respectively connected to the gate of the PMOS transistor MP6, the gate of the PMOS transistor MP7, the drain of the PMOS transistor MP5, the collector of the NPN transistor Q3 and the base of the NPN transistor Q3, the emitter of the NPN transistor Q3 is connected to the drain of the NMOS transistor MN2, the source of the NMOS transistor MN2 is connected to one end of the resistor R4, and the other end of the resistor R4 is respectively connected to the other end of the resistor R3 and the external ground GND.

4. The bandgap reference source circuit of the self-buffered loop control technology according to claim 3, characterized in that: In the bias circuit (2), the resistors R2, R3, R4, R5, R6 and R7 are made of the same material, the emitter area of ​​the NPN transistor Q2 is m times that of the NPN transistor Q1, the PMOS transistor MP3 and the PMOS transistor MP4 have the same channel width-to-length ratio, so the NPN transistor Q1 and the NPN transistor Q2 have the same collector current, and the current I flowing through the resistor R5 is R5 For I R5 =(V T lnm) / R5, where R5 is the resistance value of resistor R5, V T is the thermal voltage; NMOS tube MN1 and NMOS tube MN2 have the same channel width-to-length ratio, resistor R3 and resistor R4 are exactly the same, then the drain current I of PMOS tube MP5 P5 Yes P5 =2I R5 , which provides bias for the bandgap reference core circuit (3).

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