Pressure-resistant IGBT device and channel pushing method and gate preparation method thereof

Abstract

The application provides a pressure-resistant IGBT device and a channel pushing method and a gate preparation method thereof. When the IGBT device is prepared by using the channel pushing method, after dry etching an N-type doped polycrystal layer, a furnace tube process is used to perform P-well pushing to form a channel. In the process, the distance between the wafers is increased to at least 2 times the distance in the original process by adjusting the distance between each wafer in the furnace tube, and oxygen is provided in the nitrogen protective atmosphere of the furnace process, so that an oxide layer is formed on the front surface of the wafer. By combining the two ways of increasing the distance between the wafers and increasing the oxide layer, the influence of the N-type impurity doping of the adjacent wafers on the P-well pushing is reduced, thereby avoiding the pressure failure of the device, improving the yield of the wafer, better converging the yield stability, and improving the reliability of the device product.

Description

Technical Field

[0001] This specification relates to the field of semiconductor technology, specifically to a voltage-resistant IGBT device and its channel drive-up method and gate fabrication method. Background Technology

[0002] In semiconductor manufacturing, the P-well process of IGBTs primarily forms the channel region of the MOSFET, which can be achieved using a furnace-driven process. This P-type deep junction region is crucial to the device's breakdown voltage performance. If N-type impurities are present within this region, it can easily lead to a low breakdown voltage of the IGBT, resulting in device failure. During the manufacturing process, since both the front and back sides of the wafer are deposited with heavily doped N-type polysilicon, when using the P-well drive process, the wafers are arranged sequentially in the same direction, with the front side of the next wafer facing the back side of the previous wafer. The N-type impurities from the back side of the previous wafer diffuse out and affect the front side of the next wafer, resulting in N-type doping during P-well drive. This significantly reduces the breakdown voltage of the manufactured device below the design standard, causing leakage current and device failure, impacting wafer yield. Device failure is particularly severe at the wafer edges. Summary of the Invention

[0003] In view of this, embodiments of this specification provide a voltage-bearing IGBT device, a channel drive-up method thereon, and a gate fabrication method. The channel drive-up method can improve wafer yield, reduce the breakdown voltage failure rate of the fabricated device, and improve device reliability.

[0004] The embodiments in this specification provide the following technical solutions:

[0005] A channel drive-up method for a voltage-resistant IGBT device involves forming the channel by performing P-well drive-up using a furnace tube process after dry etching of an N-type doped polycrystalline layer.

[0006] In this process, the wafers in the furnace tube are set to be at least 4.76 mm apart, and oxygen and nitrogen are provided simultaneously during the furnace tube process to form an oxide protective layer on the front side of the wafer.

[0007] The aforementioned channel advance method uses P-well advance to fabricate the channel of the IGBT device in the furnace tube. By adjusting the spacing between the wafers in the furnace tube, the distance between the wafers is increased to at least twice the spacing used in the original process. In addition, oxygen is provided in the nitrogen protective atmosphere during the furnace entry process, so that an oxide layer is formed on the front side of the wafer. By combining the increase in the distance between the wafers and the increase in the oxide layer, the influence of N-type impurity doping on adjacent wafers is reduced during P-well advance, thereby avoiding device breakdown failure, improving wafer yield, improving yield stability convergence, and enhancing the reliability of the device product.

[0008] This specification also provides an embodiment in which the oxygen to nitrogen supply rate ratio during the furnace feeding process is 6:5.

[0009] This specification also provides an embodiment in which the oxygen supply rate is 18 liters / minute and the nitrogen supply rate is 15 liters / minute.

[0010] This specification also provides an embodiment in which oxygen and nitrogen are continuously supplied during the heating process between the furnace feeding process and the low-temperature oxidation process.

[0011] This specification also provides an embodiment in which the oxygen and nitrogen are supplied at the same rate during the heating process.

[0012] This specification also provides an embodiment in which the oxygen supply rate and nitrogen supply rate during the heating process are both 15 liters / minute.

[0013] This specification also provides an embodiment of a method for forming the trench by performing a furnace tube process at 1150 degrees Celsius for 90 minutes.

[0014] This specification also provides an embodiment that includes the following steps:

[0015] A gate oxide layer is grown using a furnace tube process, followed by the deposition of a polycrystalline silicon layer.

[0016] The polycrystalline silicon layer is doped with phosphorus by using a furnace tube process to dope POCl3;

[0017] Photolithography forms a pre-defined pattern;

[0018] The P-well region is exposed, and the polysilicon layer in the region is dry-etched to remove the resist.

[0019] A trench is formed using the trenching method as described in any one of claims 1 to 7.

[0020] The embodiments of this specification also provide a scheme in which the thickness of the gate oxide layer is 1000 angstroms, and / or the thickness of the polysilicon layer is 10000 angstroms.

[0021] This specification also provides an embodiment of an IGBT withstand voltage device fabricated using the IGBT device gate fabrication method as described in claim 8 or 9, wherein the withstand voltage is greater than 1250 volts.

[0022] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above-mentioned technical solutions adopted in the embodiments of this specification include at least the following: The channel drive method provided by the present invention, by adjusting the wafer arrangement and gas intake process of the P-well drive process, specifically by increasing the wafer arrangement spacing and providing oxygen during the furnace entry stage, reduces the influence of N-type doping from the back side of adjacent wafers on the P-well region of the wafer, thereby avoiding breakdown voltage failure of various fabricated devices on the wafer, so that the breakdown voltage of most devices meets the design requirements, especially improving the breakdown voltage failure problem at the contact position with the boat, thereby improving the wafer yield, and making the yield stability tend to converge, thus improving product stability. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the channel region of a MOSFET;

[0025] Figure 2 This is a schematic diagram illustrating the withstand voltage performance of a wafer manufactured using existing channel drive methods.

[0026] Figure 3 This is a process parameter diagram of a prior art trench propulsion method;

[0027] Figure 4 This is a photograph of the wafer arrangement of the furnace tubes in one embodiment of the present invention;

[0028] Figure 5 This is a process parameter diagram of a trench propulsion method according to one embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram showing the withstand voltage performance of a wafer manufactured using the channel drive method provided by this invention.

[0030] Figure 7 yes Figure 4 A schematic diagram of wafer yield comparison in the corresponding embodiment;

[0031] Figure 8 This is a flowchart of an IGBT device gate fabrication method according to one embodiment of the present invention. Detailed Implementation

[0032] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0033] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] It should be noted that the following description covers various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0035] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0036] It should be understood that "the connection between component A and component B" means that component A is directly connected to component B, or that component A is indirectly connected to component B through other components. The directional terms such as "upper," "lower," "inner," "outer," and "side" described in the exemplary embodiments of this specification are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this specification.

[0037] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0038] The P-well process in IGBTs is mainly used to form the channel region of MOSFETs. The P-well process often employs a furnace-driven process, advancing the transistor at high temperatures for a predetermined time, such as approximately 1150°C for about 90 minutes to form the channel region. Figure 1 As shown, the P-well (P-type deep junction region) is crucial to the breakdown voltage parameters of the fabricated device. If it is mixed with N-type impurities, it can easily cause the IGBT's breakdown voltage to be too low, leading to device failure, especially for high-voltage devices.

[0039] Taking the fabrication of a 6-inch planar IGBT gate as an example, the process steps include: gate oxide growth – polysilicon deposition – POCl3 doping – photolithography – dry etching of polysilicon – resist removal – P-well drive-up. Since gate oxide, polysilicon, POCl3 doping, and P-well drive-up all employ furnace-tube technology, both the front and back sides of the wafer are deposited with heavily doped N-type polysilicon during these three processes. Furthermore, during the subsequent P-well drive-up, due to the sequential arrangement of wafers, the front side of the next wafer faces the back side of the previous wafer. The N-type impurities from the back side of the previous wafer diffuse out, affecting the front side of the next wafer. This results in N-type doping in the deep junction region of the P-type wafer during P-well drive-up, leading to device breakdown voltage failure and poor yield. Figure 2 As shown, the design requires a withstand voltage greater than 1250 volts. The number 5 in the figure indicates a withstand voltage failure. The withstand voltage level of the devices at these locations is only 300-500 volts. Furthermore, the failure is more severe and more susceptible to N-type doping at the lower left and lower right corners of the figure, which are close to the boat.

[0040] The inventors propose a channel drive-up method that reduces the impact of N-type doping, a gate fabrication method for IGBT devices using this method, and an IGBT device fabricated using this method. The aforementioned channel drive-up method achieves the effect of reducing N-type doping by combining two control methods: first, optimizing the wafer arrangement in the furnace tube during the P-well drive-up process to increase the spacing between wafers; second, optimizing the gas supply process during the P-well drive-up process by simultaneously supplying oxygen when the wafer enters the furnace, allowing an oxide protective layer to form on the wafer surface. The combined use of these two methods effectively reduces the impact of N-type doping on the P-type deep junction region during P-well drive-up, thereby ensuring the quality of the channel fabrication and enabling the device to achieve the preset withstand voltage level.

[0041] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0042] A channel drive-up method for a high-voltage IGBT device, comprising, after a dry etching step of the N-type doped polycrystalline layer, using a furnace tube process to perform P-well drive-up to form the channel region of the IGBT device; during P-well drive-up, the wafers in the furnace tube are arranged with a minimum spacing of 4.76 mm, i.e., wafers are arranged sequentially with a minimum spacing of 4.76 mm between them. Figure 4 As shown in region A, during the furnace tube process, oxygen and nitrogen are simultaneously supplied to the furnace, causing an oxide protective layer to form on the front side of the wafer (i.e., the side where the P-type deep junction region is located).

[0043] It should be noted that, Figure 3 and Figure 5 The gas process parameters of the prior art and the trench propulsion method of the present invention are shown respectively for comparison. Figure 3 and Figure 5 Based on the existing process parameters, in the furnace feeding process, while maintaining the provision of nitrogen atmosphere protection to the furnace, an additional process step is added to provide oxygen to the furnace, simultaneously providing nitrogen and oxygen to the furnace, thereby enabling the formation of an oxide protective layer on the front side of the wafer.

[0044] It should also be noted that in the prior art, the spacing between wafers in the furnace tube is 2.38 mm (i.e., 1 / 2 IMS), such as... Figure 4 The wafer arrangement shown on the right side of the image indicates that the wafer spacing used in this invention is 4.76 mm (i.e., 1 IMS). Figure 4 As shown in area A on the left side of the image. This area A can directly utilize the fixed positions in existing furnace tubes (such as grooves, slots, etc.). If the wafers are sequentially placed into these fixed positions, the spacing between the wafers will be 1 / 2 IMS (2.38 mm). Therefore, the wafers can be arranged with one, two, or even more fixed positions skipped to achieve a spacing of at least 1 IMS (4.76 mm) between the wafers.

[0045] In the above scheme, not only is the spacing between the wafers in the furnace tube adjusted to increase the distance between wafers to at least twice that of the original process, but oxygen is also provided during the furnace entry process to form an oxide layer on the front side of the wafer. This combination of methods reduces the impact of N-type impurity doping on the back side of adjacent wafers during P-well advancement, thereby preventing device breakdown voltage failure. Figure 6 The voltage withstand data shown is based on products with a rated withstand voltage greater than 1250 volts. Products with a rated withstand voltage lower than 1250 volts on the wafer are compared to... Figure 1 This significantly reduces the number of products failing to meet withstand voltage standards at the contact points with the wafer carrier, thereby improving overall wafer yield and device reliability. Furthermore, wafer yield stability converges better, for example... Figure 4and Figure 7 As shown, Figure 7 The diagram shows two different wafer spacing arrangements used in the same P-well drive-through process. (See reference below.) Figure 4 The wafer pitch is 1 IMS (4.76 mm) in the left-hand A region and 1 / 2 IMS (2.38 mm) in the right-hand region. With the increased spacing between wafers, the product’s withstand voltage fluctuation range is smaller and the convergence is better.

[0046] In some implementation schemes, the oxygen and nitrogen supply during the furnace feeding process is set according to a process parameter setting of 6:5 ratio of oxygen supply rate to nitrogen supply rate.

[0047] Preferred, such as Figure 5 As shown, during the furnace feeding process, the oxygen supply rate is 18 liters / minute and the nitrogen supply rate is 15 liters / minute.

[0048] In some implementation schemes, such as Figure 5 As shown, a low-temperature oxidation process is set after the furnace entry process, and its process temperature is lower than the temperature of the subsequent P-well push (the high-temperature push process shown in Figure 5). A heating process is set between the furnace entry process and the low-temperature oxidation process to increase the furnace temperature. In this heating process, just like in the furnace entry process, oxygen and nitrogen are supplied to the furnace at the same time, which helps to better form an oxide protective layer on the front side of the wafer.

[0049] Preferred, such as Figure 5 As shown, during the heating process described above, the oxygen supply rate is the same as the nitrogen supply rate.

[0050] More preferably, such as Figure 5 As shown, during the heating process described above, the supply rate of both oxygen and nitrogen was 15 liters per minute.

[0051] In some implementations, in the channel drive method for fabricating high-voltage IGBT devices, the P-well drive employs a furnace tube process with the following parameters: process temperature 1150°C and process duration 90 minutes (e.g., Figure 5 As shown, a channel is formed for the IGBT device.

[0052] It should be noted that in some other implementations, the process temperature can be approximately 1150°C and the process duration can be approximately 90 minutes.

[0053] Based on the same inventive concept, this specification also provides a method for fabricating the gate of an IGBT device, such as... Figure 8 As shown, the preparation method includes the following steps:

[0054] Step 1: Using furnace tube technology, grow the gate oxide layer.

[0055] Step 2: Deposit a polycrystalline silicon layer using a furnace tube process;

[0056] Step 3: POCl3 doping is performed using a furnace tube process to dope the polycrystalline silicon layer with phosphorus;

[0057] Step 4: Photolithography is used to create the preset pattern;

[0058] Step 5: Expose the P-well region and dry etch the polysilicon layer in the region;

[0059] Step 6, remove the glue;

[0060] Step 7: Form the channel of the IGBT device using the channel drive method in any of the above implementation schemes.

[0061] The beneficial effects of the above-mentioned gate fabrication method for IGBT devices can be referred to the effects of the channel drive method for the voltage-resistant IGBT devices in the foregoing embodiments, and will not be repeated here.

[0062] In some implementation schemes of IGBT device gate fabrication methods, during the process described in step 1 above, the process parameters of the via are adjusted so that the growth thickness of the gate oxide layer is 1000 angstroms; preferably, the above gate fabrication method is performed on a 6-inch wafer.

[0063] In some implementation schemes of the gate fabrication method for IGBT devices, during the process described in step 2 above, the process parameters of the via are adjusted so that the deposition thickness of the polysilicon layer is 10,000 angstroms; preferably, the deposition thickness of the polysilicon layer is 10,000 angstroms.

[0064] Based on the same inventive concept, this specification also provides an IGBT withstand voltage device, which is fabricated using the IGBT device gate fabrication method in any of the above embodiments, and has a withstand voltage greater than 1250 volts.

[0065] In this specification, the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments.

[0066] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A channel drive method for a voltage-resistant IGBT device, characterized in that, After dry etching of the N-type doped polycrystalline layer, the channel is formed by P-well advancement using a furnace tube process; In this process, the wafers in the furnace tube are set to be at least 4.76 mm apart. Oxygen and nitrogen are continuously supplied during the heating process between the furnace entry process and the low-temperature oxidation process. Oxygen and nitrogen are also supplied simultaneously during the furnace entry process of the furnace tube process so that an oxide protective layer is formed on the front side of the wafer. The oxygen to nitrogen supply rate ratio during the furnace feeding process is 6:5; the oxygen supply rate is 18 liters / minute, and the nitrogen supply rate is 15 liters / minute; the oxygen and nitrogen supply rates are the same during the heating process.

2. The channel drive method for the IGBT device according to claim 1, characterized in that, During the heating process, the oxygen supply rate and the nitrogen supply rate are both 15 liters / minute.

3. The channel drive method for the IGBT device according to claim 1, characterized in that, The channel is formed by performing a furnace tube process at 1150 degrees Celsius for 90 minutes.

4. A method for fabricating the gate of an IGBT device, characterized in that, Includes the following steps: A gate oxide layer is grown using a furnace tube process, followed by the deposition of a polycrystalline silicon layer. The polycrystalline silicon layer is doped with phosphorus by using a furnace tube process to dope POCl3; Photolithography forms a pre-defined pattern; The P-well region is exposed, and the polysilicon layer in the region is dry-etched to remove the resist. A trench is formed using the trenching method as described in any one of claims 1 to 3.

5. The IGBT device gate fabrication method according to claim 4, characterized in that, The gate oxide layer has a growth thickness of 1000 angstroms, and / or the polysilicon layer has a deposition thickness of 10000 angstroms.

6. An IGBT withstand voltage device, characterized in that, The IGBT withstand voltage device is fabricated using the IGBT device gate fabrication method as described in claim 4 or 5, and its withstand voltage is greater than 1250 volts.

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