A reverse charging protection circuit

Abstract

The embodiment of the present invention provides a reverse charging protection circuit, which improves the reverse charging circuit structure from the circuit structure, greatly reduces the use of high-voltage devices, reduces the use of large-size devices, uses the least devices and the least power consumption, and reliably realizes the reverse charging protection function. At the same time, the adjustment scheme is also modified to effectively expand the adjustment range, thereby reducing the requirements for comparator accuracy without affecting the current threshold accuracy of the reverse charging protection circuit, thereby reducing the size of the comparator, increasing the reaction speed of the comparator to prevent reverse charging in time, increasing the reliability of the protection circuit, and reducing the area of ​​the circuit.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of protection circuits, and in particular to a reverse charging protection circuit. Background Art

[0002] With the development of information technology, mobile phones have become the core devices for people to exchange information. As the internal hardware performance of mobile phones becomes stronger, the screen becomes larger, and the software operation becomes more complex, the power consumption of mobile phones is also getting faster and faster. In addition to increasing the capacity of mobile phone batteries, improving charging power is also a top priority for manufacturers to improve battery life. Although the charge pump fast charging chip can achieve high-current and high-efficiency charging, helping mobile phone charging chips to break through physical limitations, it has a disadvantage in principle. The charge pump charging circuit can be charged both forward and reverse at the same time. Reverse charging will cause serious safety hazards. Therefore, a reverse charging protection circuit is required in the charge pump charging chip. Once reverse charging is detected, the charge pump fast charging chip is immediately turned off to block the charging path, protect the input source and battery, and ensure charging safety. Existing technologies such as Figure 1As shown, the reverse charging path is that the power supply VBAT passes through the charge pump charging path to the intermediate power supply PMID, and then from the intermediate power supply PMID through the protection switch Qb to the input power supply VBUS. The switch Qb_sns is the mirror transistor of the switch Qb. The ratio of the on-resistance of the switch Qb_sns to that of the switch transistor Qb is X:1. A voltage VBUS_sns is generated by the variable pull-down current source Iref flowing through the on-resistance of Qb_sns, and VBUS_sns = PMID - Iref * RQb_sns (RQb_sns is the on-resistance of Qb_sns). The voltage of VBUS is PMID - Iload * RQb (RQb is the on-resistance of Qb). When VBUS = VBUS_sns, that is, Iref * RQb_sns = Iload * RQb, we can get Iload = X * Iref. When Iload > X * Iref, VBUS < VBUS_sns. Iload is the current of the input power supply. The positive pole of the high-precision comparison circuit > the negative pole, and the output signal RCP of the comparison circuit changes from low to high, indicating that the current from the intermediate power supply PMID to the input power supply VBUS exceeds the protection threshold of X * Iref, and the charge pump charging circuit needs to be turned off to prevent reverse charging. As the battery charging current increases, for efficiency considerations, the on-resistance of Qb needs to be smaller and smaller (less than 6 mΩ), while the threshold of the reverse charging current is generally relatively small (less than about 0.2 A), so there will be a situation where Iref * RQb_sns is relatively small, such as 0.2 A * 5 mΩ = 1 mV. The adjustment of the threshold of the reverse current protection circuit is generally to correct the threshold deviation by adjusting the current of the adjustment circuit Iref, which makes the maximum forward adjustment range of VBUS_sns the situation when Iref = 0, that is, Iref * RQbsns = 0. The largest source of the threshold deviation is the input offset voltage of the comparison circuit. If the input offset voltage Vos of the comparison circuit is 2 mV, then the current threshold deviation of the reverse charging protection circuit is Vos / RQb = 2 mV / 5 mΩ = 0.4 A. In order to make the input offset voltage of the comparison circuit be covered by the adjustment range and make the thresholds of most chips be corrected back to the center point, the offset voltage Vos of the comparison circuit itself needs to be less than Iref * RQbsns, that is, 1 mV. This requires the design of the comparison circuit to be designed according to the requirements of a high-precision comparison circuit. Usually, it is necessary to ensure that the 3σ offset voltage of the comparison circuit is less than 1 mV, that is, 1σ is less than 0.33 mV. This requires the use of many particularly large-sized devices to ensure that the mismatch of the comparison circuit is small enough. However, the use of large-sized devices will not only increase the area but also introduce a large parasitic capacitance, thus seriously affecting the response speed of the comparison circuit. When the reverse current changes rapidly to a large value, the reverse protection circuit reacts slowly and cannot turn off the reverse charging circuit in time, which will introduce a safety risk and damage the input source or the battery. Summary of the Invention

[0003] To this end, an embodiment of the present invention provides a reverse charging protection circuit to solve the technical problems in the prior art such as the safety risk introduced by the slow reaction of the reverse protection circuit and the failure to shut down the reverse charging circuit in time, which damages the input source or the battery.

[0004] In a first aspect, an embodiment of the present application provides a reverse charging protection circuit, comprising: a first switch, a second switch, a trimming circuit and a comparison circuit;

[0005] The first end of the first switch is connected to the input power supply and the first end of the trimming circuit, and the first end of the second switch is connected to the first end of the trimming circuit;

[0006] The second end of the first switch and the second end of the second switch are both connected to an intermediate power supply;

[0007] The third end of the first switch and the third end of the second switch are both connected to the first bias circuit;

[0008] The second end of the trimming circuit is connected to the first end of the comparison circuit, and the third end of the trimming circuit is connected to the reference ground;

[0009] The comparison circuit includes a first comparison circuit branch, a second comparison circuit branch, a level conversion circuit and a driving circuit. The first comparison circuit branch and the second comparison circuit branch are arranged in parallel. The first end of the first comparison circuit branch and the first end of the second comparison circuit branch are connected to the second end of the adjustment circuit. The second end of the first comparison circuit branch and the second end of the second comparison circuit branch are connected to the reference ground. The third end of the second comparison circuit branch is connected to the first end of the level conversion circuit. The second end of the level conversion circuit is connected to the first end of the driving circuit. The second end of the driving circuit is connected to the first ends of the first switch and the second switch. The first switch is closed by the control signal of the driving circuit to prevent reverse charging.

[0010] As a preferred embodiment of the present application, the circuit further includes a hysteresis generating circuit;

[0011] The second end of the driving circuit is connected to the first end of the hysteresis generating circuit, the second end of the hysteresis generating circuit is connected to the first end of the second switch, the third end of the hysteresis generating circuit is connected to the reference ground, and the hysteresis generating circuit is used to avoid unstable output logic level of the comparison circuit when the voltages of the two input ends of the comparison circuit are close.

[0012] As a preferred embodiment of the present application, the trimming circuit includes: a trimming branch and a first current source; the first end of the trimming branch is respectively connected to the first end of the first switch and the first end of the second switch; the first end of the first current source is connected to the second end of the trimming branch, and the second end of the first current source is connected to the reference ground.

[0013] As a preferred embodiment of the present application, the trimming branch includes a first resistor and a second resistor;

[0014] The first end of the first resistor is connected to the first end of the first switch, the first end of the second resistor is connected to the first end of the second switch, and the second end of the first resistor is connected to the first end of the first comparison circuit branch and the first end of the first current source respectively.

[0015] The second end of the second resistor is connected to the first end of the second comparison circuit branch and the first end of the first current source.

[0016] As a preferred embodiment of the present application, the trimming circuit includes: a first capacitor is arranged between the second end of the first resistor and the second end of the second resistor.

[0017] As a preferred embodiment of the present application, the first comparison circuit branch includes a first PMOS transistor and a second current source connected in series, and the second comparison circuit branch includes a second PMOS transistor and a second current source connected in series;

[0018] The gate and drain of the first PMOS tube are connected, and the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the source of the first PMOS tube is connected to the second end of the first resistor, the drain of the first PMOS tube is connected to the first end of the second current source, and the second end of the second current source is connected to the reference ground;

[0019] The source of the second PMOS tube is connected to the second end of the second resistor, the drain of the second PMOS tube is connected to the first end of the third current source, and the second end of the third current source is connected to the reference ground.

[0020] As a preferred embodiment of the present application, a first NMOS transistor is further provided on the first comparison circuit branch, the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, the gate of the first NMOS transistor is connected to the second bias circuit, and the source of the first NMOS transistor is connected to the first end of the second current source;

[0021] A third PMOS tube is also provided on the first comparison circuit branch, the source of the third PMOS tube is connected to the drain of the second PMOS tube, the gate of the third PMOS tube is connected to the third bias circuit, and the drain of the third PMOS tube is connected to the first end of the third current source.

[0022] As a preferred embodiment of the present application, the level conversion circuit includes a second NMOS transistor, a third NMOS transistor and a fourth current source;

[0023] The drain of the second NMOS tube is connected to the drain of the third PMOS tube, the source of the second NMOS tube is connected to the first end of the third current source, the common end between the source of the second NMOS tube and the first end of the third current source is connected to the gate of the third NMOS tube, the source of the third NMOS tube is connected to the reference ground, and the drain of the third NMOS tube is connected to the first end of the fourth current source.

[0024] As a preferred embodiment of the present application, the first end of the driving circuit is connected to a common end between the first end of the fourth current source and the drain of the third NMOS tube.

[0025] As a preferred embodiment of the present application, the hysteresis generating circuit is a fifth current source.

[0026] Compared with the prior art, the embodiment of the present application provides a reverse charging protection circuit, which improves the reverse charging circuit structure from the circuit structure, greatly reduces the use of high-voltage devices, reduces the use of large-size devices, uses the least devices and the least power consumption, and reliably realizes the reverse charging protection function. At the same time, the adjustment scheme is also modified to effectively expand the adjustment range, thereby reducing the requirements for comparator accuracy without affecting the current threshold accuracy of the reverse charging protection circuit, thereby reducing the size of the comparison circuit, increasing the reaction speed of the comparison circuit, and thus preventing reverse charging in time. The reliability of the protection circuit is increased and the area of ​​the circuit is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the implementation methods of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the implementation methods or the description of the prior art. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other implementation drawings can be derived from the provided drawings without creative work.

[0028] The structures, proportions, sizes, etc. illustrated in this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with the technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantial technical significance. Any structural modification, change in proportion or adjustment of size shall still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and purposes that can be achieved by the present invention.

[0029] Figure 1 A schematic diagram of a reverse charging protection circuit structure provided in the prior art;

[0030] Figure 2 A schematic diagram of a reverse charging protection circuit structure provided in an embodiment of the present application;

[0031] Figure 3 A schematic diagram of a reverse charging protection circuit structure provided in an embodiment of the present application;

[0032] Figure 4 This is a working waveform diagram of a reverse charging protection circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The following is a description of the implementation of the present invention by specific embodiments. People familiar with the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] like Figure 2 As shown, the embodiment of the present application provides a reverse charging protection circuit, including: a first switch 02, a second switch 07, a trimming circuit 05 and a comparison circuit 04;

[0035] The first switch 02 is equivalent to the prior art Figure 1 The switch Qb in the second switch 07 is equivalent to the prior art Figure 1 The switch Qb_sns in the circuit, the second switch 07 is a mirror image tube of the first switch 02, the first switch 02 and the second switch 07 are both NMOS tubes, the first end of the first switch 02 and the first end of the second switch 07 are both sources, the second end of the first switch 02 and the second end of the second switch 07 are both drains, the third end of the first switch 02 and the third end of the second switch 07 are both gates, in the embodiment of the present application, the first end of the first switch 02 is connected to the input power supply 01 and the first end of the trimming circuit 05, the first end of the second switch 07 is connected to the first end of the trimming circuit 05, and the first end of the second switch 07 is connected to the first end of the trimming circuit 05; the second end of the first switch 02 and the second end of the second switch 07 are both connected to the intermediate power supply 03; the third end of the first switch 02 and the third end of the second switch 07 are both connected to the first bias circuit 08 so that the first switch 02 and the second switch 07 can be turned on by the first bias circuit 08.

[0036] The second end of the adjustment circuit 05 is connected to the first end of the comparison circuit 04, and the third end of the adjustment circuit 05 is connected to the reference ground. The comparison circuit 04 includes a first comparison circuit branch 04-1, a second comparison circuit branch 04-2, a level conversion circuit 04-3 and a drive circuit 04-4. The first comparison circuit branch 04-1 and the second comparison circuit branch 04-2 are arranged in parallel.

[0037] The first end of the first comparison circuit branch 04-1 and the first end of the second comparison circuit branch 04-2 are connected to the second end of the adjustment circuit 05, the second end of the first comparison circuit branch 04-1 and the second end of the second comparison circuit branch 04-2 are connected to the reference ground, the third end of the second comparison circuit branch 04-2 is connected to the first end of the level conversion circuit 04-3, the second end of the level conversion circuit 04-3 is connected to the first end of the drive circuit 04-4, the second end of the drive circuit 04-4 is connected to the first ends of the first switch 02 and the second switch 07, and the first switch 02 is closed by the control signal of the drive circuit 04-4 to prevent reverse charging.

[0038] Preferably, the trimming circuit 05 includes: a trimming branch and a first current source 05-3, the first end of the trimming branch is respectively connected to the first end of the first switch 02 and the first end of the second switch 07; the first end of the first current source 05-3 is connected to the second end of the trimming branch; the second end of the first current source 05-3 is connected to the reference ground.

[0039] In the embodiment of the present application, the trimming branch includes a first resistor 05-1 and a second resistor 05-2; wherein the first end of the first resistor 05-1 is connected to the first end of the first switch 02, the first end of the second resistor 05-2 is connected to the first end of the second switch 07, the second end of the first resistor 05-1 is respectively connected to the first end of the first comparison circuit branch 04-1 and the first end of the first current source 05-3, the second end of the second resistor 05-2 is connected to the first end of the second comparison circuit branch 04-2 and the first end of the first current source 05-3, wherein the resistance of the first resistor 05-1 is less than the resistance of the second resistor 05-2. The trimming circuit 05 of the present application can expand the trimming range, thereby reducing the requirements for the accuracy of the comparison circuit without affecting the current threshold accuracy of the reverse charging protection circuit, thereby reducing the size of the comparison circuit, increasing the reaction speed of the comparison circuit to prevent reverse charging in time, and then increasing the reliability of the protection circuit and reducing the area of ​​the circuit.

[0040] Specifically, the ratio of the resistance value R1 of the first resistor 05-1 to the resistance value R2 of the second resistor 05-2 is set to β, β=0.5, and the current Itrim of the first current source 05-3 is set equal to the current I1 of the second current source 04-1-2. Voltage v1=PMID-(Iload+Itrim+I1)*RQb-(Itrim+I1)*R1, voltage v2=PMID-(I2+Ihys)*RQb_sns-I2*R2, wherein v1 is the source voltage of the first PMOS tube 04-1-1 or the input voltage of the comparison circuit, v2 is the source voltage of the second PMOS tube 04-2-1 or the input voltage of the comparison circuit, Iload is the current of the input power supply 01, PMID is the output voltage of the intermediate power supply 03, RQb is the on-resistance of the first switch 02, Ihys is the current of the first current source 05-3, RQb_sns is the on-resistance of the second switch 07, I1 is the current of the second current source 04-1-2, and I2 is the current of the third current source 04-2-2.

[0041] In the above formula, Itrim and I1 are both currents of tens of microamperes, and when the comparator flips, ILoad is a current of hundreds of milliamperes, so Itrim and I1 are much smaller than Iload, so they can be ignored in the formula, that is: v1=PMID-Iload*RQb-(Itrim+I1)*R1, v2=PMID-(I2+Ihys)*RQb_sns-I2*R2; in the above formula, I1=I2, RQb_sns=X*RQb, R1=0.5*R2; the ratio of the on-resistance of the second switch 07Qb_sns to the first switch 02Qb is X:1. When v1=v2, Iload*RQb+(Itrim+I1)*R1=(I2+Ihys)*X*RQb+I1*2*R1, when Itrim=I1, Iload*RQb+I1*2*R1=(I2+Ihys)*X*RQb+I1*2*R1, and Iload=(I2+Ihys)*X. That is, (I2+Ihys) realizes the function of Iref in the prior art.

[0042] When Itrim=0, the v1 voltage is higher than the target v1 voltage value by I1*R1.

[0043] When Itrim=2*I1, the v1 voltage is lower than the target v1 voltage value by I1*R1.

[0044] The voltage of v1 has the ability to adjust from -I1*R1 to +I1*R1. For example, if I1=20uA and R1=500Ω, v1 has the ability to adjust by ±10mV. If the first current source 05-3 is used for adjustment, the comparator offset voltage of ±10mV can be covered.

[0045] In the embodiment of the present application, a first capacitor C1 is disposed between the second end of the first resistor 05 - 1 and the second end of the second resistor 05 - 2 . The first capacitor C1 is a filter capacitor for reducing an AC ripple coefficient.

[0046] like Figure 3 As shown, in the embodiment of the present application, the first comparison circuit branch 04-1 includes a first PMOS tube 04-1-1 and a second current source 04-1-2 connected in series, and the second comparison circuit branch 04-2 includes a second PMOS tube 04-2-1 and a third current source 04-2-2 connected in series.

[0047] The gate and drain of the first PMOS tube 04-1-1 are connected, and the gate of the first PMOS tube 04-1-1 is connected to the gate of the second PMOS tube 04-2-1, the source of the first PMOS tube 04-1-1 is connected to the second end of the first resistor 05-1, the drain of the first PMOS tube 04-1-1 is connected to the first end of the second current source 04-1-2, and the second end of the second current source 04-1-2 is connected to the reference ground. The first NMOS tube 04-1-3 can ensure that the voltage drops of the second current source 04-1-2 and the third current source 04-2-2 are equal, because the consistent voltage drops can reduce or eliminate the current deviation, thereby reducing the offset voltage of the comparison circuit.

[0048] The source of the second PMOS transistor 04-2-1 is connected to the second end of the second resistor 05-2, the drain of the second PMOS transistor 04-2-1 is connected to the first end of the third current source 04-2-2, and the second end of the third current source 04-2-2 is connected to the reference ground.

[0049] In the embodiment of the present application, a first NMOS tube 04-1-3 is also provided on the first comparison circuit branch 04-1, the drain of the first NMOS tube 04-1-3 is connected to the drain of the first PMOS tube 04-1-1, the gate of the first NMOS tube 04-1-3 is connected to the second bias circuit 04-1-4, and the source of the first NMOS tube 04-1-3 is connected to the first end of the second current source 04-1-2.

[0050] A third PMOS tube 04-2-3 is also provided on the second comparison circuit branch 04-2, the source of the third PMOS tube 04-2-3 is connected to the drain of the second PMOS tube 04-2-1, the gate of the third PMOS tube 04-2-3 is connected to the third bias circuit 04-2-4, the drain of the third PMOS tube 04-2-3 is connected to the first end of the third current source 04-2-2, the second bias circuit 04-1-4 is used to turn on the first NMOS tube 04-1-3, the third bias circuit 04-2-4 is used to turn on the third PMOS tube 04-2-3, in the embodiment of the present application, the level conversion circuit 04-3 includes a second NMOS tube 04-3-1, a third NMOS tube 04-3-2 and a fourth current source 04-3-3; the third PMOS tube 04-2-3 can ensure that the drain voltage of the first PMOS tube 04-1-1 is equal to the drain voltage of the second PMOS tube 04-2-1.

[0051] The drain of the second NMOS tube 04-3-1 is connected to the drain of the third PMOS tube 04-2-3, the source of the second NMOS tube 04-3-1 is connected to the first end of the third current source 04-2-2, the common end between the source of the second NMOS tube 04-3-1 and the first end of the third current source 04-2-2 is connected to the gate of the third NMOS tube 04-3-2, the source of the third NMOS tube 04-3-2 is connected to the reference ground, the drain of the third NMOS tube 04-3-2 is connected to the first end of the fourth current source 04-3-3, the second NMOS tube 04-3-1 is equivalent to a switch, when the source voltage v3 of the second NMOS tube 04-3-1 exceeds the preset value, the second NMOS tube 04-3-1 is turned off, so that the source voltage V3 of the second NMOS tube 04-3-1 can be a relatively low voltage.

[0052] In the embodiment of the present application, the first terminal of the driving circuit 04 - 4 is connected to the common terminal between the first terminal of the fourth current source 04 - 3 - 3 and the drain of the third NMOS transistor 04 - 3 - 2.

[0053] The core of the comparison circuit 04 is composed of a first PMOS transistor 04-1-1, a second PMOS transistor 04-2-1, a third PMOS transistor 04-2-3, a first NMOS transistor 04-1-3, a second NMOS transistor 04-3-1, a third NMOS transistor 04-3-2, a second current source 04-1-2, a third current source 04-2-2, and a fourth current source 04-3-3. Its working principle is:

[0054] Set I1=I2, the width-to-length ratio of the first PMOS tube 04-1-1 is equal to the width-to-length ratio of the second PMOS tube 04-2-1, wherein the first PMOS tube 04-1-1 and the second PMOS tube 04-2-1 are low-voltage PMOS tubes, and the third PMOS tube 04-2-3 is a high-voltage PMOS tube, and set the voltage vb1 of the second bias circuit 04-1-4 to VBUS-2*Vthp. Vthp is the turn-on threshold voltage of the PMOS. Through such a design, the Vds of the second PMOS tube 04-2-1 and the Vds of the first PMOS tube 04-1-1 are both around VBUS-Vthp, so that on the one hand, the Vds of the second PMOS tube 04-2-1 can be protected from overvoltage, and on the other hand, the Vds of the second PMOS tube 04-2-1 and the first PMOS tube 04-1-1 can be equal, thereby eliminating the failure voltage introduced by the channel length modulation effect, wherein Vds is the voltage between the gate and the source of the PMOS tube. The voltage vb2 of the second bias circuit 04-1-4 is set to 2*Vthn, where Vthn is the turn-on threshold voltage of NMOS. When the comparison circuit is at the flip point, the voltage of v3 is equal to Vthn, and the source voltage of the first NMOS tube 04-1-3 is also Vthn, so that the current imbalance introduced by the different voltage drops of the second current source 04-1-2 and the third current source 04-2-2 can be eliminated. The gate of the second NMOS tube 04-3-1 is connected to the low-voltage power supply vdd, so that the voltage of v3 can be limited to not exceed vdd-Vthn. The common source amplifier composed of the third NMOS tube 04-3-2 and the fourth current source 04-3-3 is used as the second stage of the comparison circuit to convert the logic high level of v3 from vdd-Vthn to vdd, and vdd is a low-voltage power supply. Through the inverting drive circuit DRV04-4, the RCP control signal is output to the charging control circuit to control the shutdown of the charge pump charging circuit.

[0055] When v1>v2, the gate-source voltage Vds of the second PMOS transistor 04-2-1 is greater than the gate-source voltage Vds of the first PMOS transistor 04-1-1, so the current IP2 flowing through the second PMOS transistor P2 04-2-1 is greater than the current IP1 flowing through the first PMOS transistor P1 04-1-1, and I1=I2=IP2. Therefore, I2>IP1, the pull-down current is greater than the pull-up current for point v3, v3 is pulled down, the gate of the third NMOS transistor 04-3-2 is pulled down, the third NMOS transistor 04-3-2 is turned off, v4 is pulled up by the fourth current source 04-3-3, and the comparison circuit output control signal RCP=0 is obtained through the reverse of the driving circuit 04-4DRV, and the charge pump charging circuit works normally.

[0056] When v1<v2, the gate-source voltage Vds of the second PMOS tube 04-2-1 is less than the gate-source voltage Vds of the first PMOS tube 04-1-1, so the current IP2 flowing through the second PMOS tube P2 04-2-1 is less than the current IP1 flowing through the first PMOS tube P1 04-1-1, and I1=I2=IP1. Therefore, I2<IP1, the pull-down current is less than the pull-up current for the v3 point, and v3 is pulled up. When v3 is pulled up to vdd-Vthn, the gate-source voltage Vds of the second NMOS tube 04-3-1 is less than Vthn, the second NMOS tube 04-3-1 is turned off, and the gate of the third NMOS tube 04-3-2 cannot continue to rise. The gate voltage of the third NMOS transistor 04-3-2 exceeds Vthn, the third NMOS transistor 04-3-2 is turned on, v4 is pulled low, and the comparator output signal RCP=1 is obtained inversely through the drive circuit DRV 04-4, and the charge pump charging circuit is turned off.

[0057] As described above, the functions of the comparison circuit, floating ground generation circuit and level conversion circuit in the prior art are all implemented in this patent.

[0058] Preferably, the reverse charging protection circuit provided in the embodiment of the present application also includes a hysteresis generating circuit 06; the second end of the driving circuit 04-4 is connected to the first end of the hysteresis generating circuit 06, the third end of the hysteresis generating circuit 06 is connected to the reference ground, the second end of the hysteresis generating circuit 06 is connected to the first end of the second switch 07, and the hysteresis generating circuit 06 is used to avoid the comparison circuit output logic level being unstable when the voltages of the two input ends of the comparison circuit are similar. In the embodiment of the present application, the hysteresis generating circuit 06 is a fifth current source. When RCP=0, the fifth current source is turned on, and when RCP=1, the fifth current source is turned off, and VBUS_sns rises by Ihys*RQb_sns, that is, after the input power supply 01 increases to make RCP=1, the input power supply 01 needs to drop to a current lower than the threshold of RCP changing from 0 to 1 by X*Ihys before RCP can be restored from 1 to 0. The role of the comparator hysteresis is to prevent the comparison circuit 04 from flipping back and forth and failing to output a stable logic level when VBUS and VBUS_sns are close.

[0059] In summary, the Iref circuit function in the prior art is implemented in the comparison circuit 04 of this patent, and the adjustment range is effectively expanded. The expansion of the adjustment range greatly reduces the difficulty of the comparison circuit precision design. The device size and design complexity will be greatly reduced, and the use of small-sized devices instead of large-sized devices will also greatly improve the speed of the comparator.

[0060] The working principle and waveform of the reverse charging protection circuit are as follows: Figure 4 As shown:

[0061] When the current Iload of the input power supply 01 increases, the voltage VBUS of the input power supply 01 decreases, and the voltage of v1 also decreases. Because the voltage drops of the first resistor R1 05-1 and the second resistor R2 05-2 are the same, when VBUS drops to a voltage lower than VBUS_sns, the voltage of v1 is lower than v2, the gate-source voltage of the second PMOS tube 04-2-1 increases, the pull-up current of the second PMOS tube 04-2-1 increases, the pull-up current at point v3 is greater than the pull-down current, v3 becomes higher, but is clamped to vdd-vthn by the third NMOS tube 04-3-1, the gate voltage of the third NMOS tube 04-3-2 increases, the third NMOS tube 04-3-2 turns on to make v4 lower, and through the reverse drive circuit 04-4DRV, the RCP output is high. This indicates that the reverse charging protection is working, the charge pump charging circuit is turned off, the fifth current source is turned off, VBUS_sns rises, and the Iload current threshold of the RCP control signal from high to low decreases.

[0062] When the input power supply 01Iload current decreases, the input power supply 01 voltage VBUS increases, and the v1 voltage also increases. Because the voltage drops of R1 and R2 are the same, when it rises to a voltage greater than VBUS_sns, the v1 voltage is greater than v2, the gate-source voltage of the second PMOS tube 04-2-1 decreases, the pull-up current of the second PMOS tube 04-2-1 decreases, the pull-up current of point v3 is less than the pull-down current, v3 becomes low, the third NMOS tube 04-3-2 is cut off, and the fourth current source 04-3-3 pulls up to make v4 high. After the reverse drive circuit 04-4DRV, the RCP control signal output is low, indicating that the reverse charging protection does not work, and the charge pump charging circuit can work. The fifth current source is turned on, and VBUS_sns decreases. The input power supply 01Iload current threshold of the RCP control signal changes from low to high rises.

[0063] The protection circuit provided in the embodiment of the present application has a simple structure, a small area (the area saved is greater than 50%), a low implementation cost, reliable functions, low power consumption (less than 50% of the prior art), and an increased adjustment range. Without affecting the accuracy of the comparison circuit 04, the area of ​​the comparison circuit 04 is reduced to the maximum extent, and the speed of the comparison circuit 04 is improved (the response time is less than 20%), so that the reverse charging protection can quickly and reliably block the reverse charging path from the powered device VBAT to the input source VBUS, thereby improving safety.

[0064] Although the present invention has been described in detail above by general description and specific embodiments, it is obvious to those skilled in the art that some modifications or improvements can be made to the present invention. Therefore, these modifications or improvements made without departing from the spirit of the present invention all belong to the scope of protection claimed by the present invention.

Claims

1. A reverse charging protection circuit, characterized in that: include: A first switch, a second switch, a trimming circuit and a comparison circuit; The first end of the first switch is connected to the input power supply and the trimming circuit, and the first end of the second switch is connected to the trimming circuit; the second end of the first switch and the second end of the second switch are connected to the intermediate power supply; the third end of the first switch and the third end of the second switch are connected to the first bias circuit; The comparison circuit comprises a first comparison circuit branch, a second comparison circuit branch, a level conversion circuit and a driving circuit; The trimming circuit comprises: a trimming branch and a first current source; The trimming branch includes a first resistor and a second resistor; a first end of the first resistor is connected to a first end of a first switch, a first end of the second resistor is connected to a first end of a second switch, a second end of the first resistor is connected to a first end of a first comparison circuit branch and a first end of a first current source, respectively, and a second end of the second resistor is connected to a first end of a second comparison circuit branch and a first end of a first current source; A first capacitor is provided between the second end of the first resistor and the second end of the second resistor; The second terminal of the first current source is connected to the reference ground; The first comparison circuit branch includes a first PMOS tube and a second current source connected in series, and the second comparison circuit branch includes a second PMOS tube and a third current source connected in series; the gate and drain of the first PMOS tube are connected, and the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the source of the first PMOS tube is connected to the second end of the first resistor, the drain of the first PMOS tube is connected to the first end of the second current source, and the second end of the second current source is connected to the reference ground; the source of the second PMOS tube is connected to the second end of the second resistor, the drain of the second PMOS tube is connected to the first end of the third current source, and the second end of the third current source is connected to the reference ground; A first NMOS tube is further provided on the first comparison circuit branch, the drain of the first NMOS tube is connected to the drain of the first PMOS tube, the gate of the first NMOS tube is connected to the second bias circuit, and the source of the first NMOS tube is connected to the first end of the second current source; a third PMOS tube is further provided on the second comparison circuit branch, the source of the third PMOS tube is connected to the drain of the second PMOS tube, the gate of the third PMOS tube is connected to the third bias circuit, and the drain of the third PMOS tube is connected to the first end of the third current source; The level conversion circuit includes a second NMOS tube, a third NMOS tube and a fourth current source; the drain of the second NMOS tube is connected to the drain of the third PMOS tube, the source of the second NMOS tube is connected to the first end of the third current source, the common end between the source of the second NMOS tube and the first end of the third current source is connected to the gate of the third NMOS tube, the source of the third NMOS tube is connected to the reference ground, and the drain of the third NMOS tube is connected to the first end of the fourth current source; The first end of the driving circuit is connected to a common end between the first end of the fourth current source and the drain of the third NMOS tube.

2. A reverse charging protection circuit as claimed in claim 1, characterized in that: The circuit also includes a hysteresis generating circuit; the second end of the driving circuit is connected to the first end of the hysteresis generating circuit, the second end of the hysteresis generating circuit is connected to the first end of the second switch, and the third end of the hysteresis generating circuit is connected to the reference ground. The hysteresis generating circuit is used to avoid unstable output logic level of the comparison circuit when the voltages of the two input ends of the comparison circuit are close.

3. A reverse charging protection circuit as claimed in claim 2, characterized in that: The hysteresis generating circuit is a fifth current source.

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