A programmable delay line circuit for high-speed, low-jitter DLL

Abstract

The present invention relates to a programmable delay line circuit for a high-speed, low-jitter DLL, comprising a variable delay line circuit, a logic control circuit, and a clock drive circuit. The variable delay line circuit can flexibly change the transmission delay of the input clock by adjusting the delay line length; at the same time, the variable delay line circuit can finely change the transmission delay of the input clock by changing the single-stage delay bias voltage; the logic control circuit decodes the external input programming code into a delay line length control signal; the clock drive circuit can restore the clock to a full-amplitude square wave clock signal and correct the duty cycle and crossover point of the clock signal for use by subsequent circuits. The present invention can accurately and flexibly implement high-speed, low-jitter differential clock delay adjustment. By increasing the delay chain length, the delay accuracy of the single-stage delay unit is continuously improved, and the requirements of high-speed, low-jitter DLLs for variable delay line width delay adjustment range and high delay adjustment accuracy can be met.

Description

Technical Field

[0001] The present invention relates to a programmable delay line circuit for high-speed low-jitter DLL, belonging to the technical field of digital-analog hybrid circuits such as high-speed digital-analog converters and high-speed clock signal processing. Background Art

[0002] Military equipment such as wireless communication devices and radars often include mixed-analog circuits such as high-speed digital-to-analog converters and high-speed clock signal processing. These circuits require high-speed clock signals, and the quality of these clock signals directly impacts system performance. Low-jitter multi-phase high-speed clocks are typically implemented using delay-locked loop (DLL) circuits, offering advantages such as low noise, high speed, and reduced power consumption and area. As the core circuit of the delay-locked loop (DLL), the delay line directly determines the DLL's operating frequency and jitter performance. The delay line's delay adjustment range and accuracy directly determine the DLL's locking range and accuracy, thus determining its noise performance and frequency range. However, traditional delay lines based on analog circuits are susceptible to fluctuations in process technology, power supply voltage, and temperature, making them unable to meet the high-reliability requirements of military applications. Furthermore, the delay adjustment accuracy and delay adjustment range are mutually constrained, making it difficult to meet the requirements of a wide frequency range and high delay accuracy. Therefore, realizing a variable delay line suitable for high-speed differential clock signals, which can not only meet the requirements of high delay adjustment accuracy but also meet the requirements of wide delay adjustment range, while also having low noise performance and high reliability, is the key to ensuring high-speed and low-jitter DLL circuits. Summary of the Invention

[0003] The technical problem solved by the present invention is to overcome the shortcomings of the existing technology and provide a programmable delay line circuit for high-speed, low-jitter DLLs. This programmable delay line circuit uses a logic control circuit to control the variable delay line length, flexibly changing the input clock transmission delay. Furthermore, the variable delay line circuit can finely change the input clock transmission delay by varying the single-stage delay bias voltage. The present invention enables precise and flexible high-speed, low-jitter differential clock delay adjustment. By increasing the delay chain length, the delay accuracy of the single-stage delay unit is continuously improved, meeting the high-speed, low-jitter DLL requirements for a variable delay line width delay adjustment range and high delay adjustment accuracy.

[0004] The purpose of the present invention is achieved through the following technical solutions:

[0005] A programmable delay line circuit for high-speed, low-jitter DLL, comprising: a variable delay line circuit, a logic control circuit, and a clock drive circuit;

[0006] The logic control circuit converts the external input n-bit delay line length programming code W <n-1:0>Decoded as 2 n -1-bit delay line length control signal T<2 n -2:0> and output to the variable delay line circuit to configure the delay line length;

[0007] The input end of the variable delay line circuit is connected to the external input differential clock signal CKIP, CKIN, and the delay line length control signal T<2 is output by the logic control circuit. n -2:0> Under the control of the delay line length, the input clock delay can be roughly adjusted. In addition, the input clock delay can be finely adjusted by changing the external input bias voltage PVB. After the delay is adjusted, the differential clock signals CKP and CKN are output and transmitted to the clock drive circuit.

[0008] The clock driving circuit receives the differential clock signals CKP and CKN output from the variable delay line circuit, amplifies the CKP and CKN clocks to restore them to full-amplitude square wave clock signals, and corrects the duty cycle and cross point; and outputs the adjusted differential clock signals CLKP and CLKN.

[0009] Preferably: the variable delay line circuit includes 2 n +1 basic delay unit with the same structure; 2 n +1 level basic delay units connected end to end;

[0010] By outputting the delay line length control signal T<2 in the logic control circuit n -2:0> control, change the number of accesses to the basic delay unit and roughly adjust the input clock delay.

[0011] Preferably, the basic delay unit includes: a forward path and a reverse path;

[0012] The forward path input of the k-th basic delay unit receives the forward differential clock signal FP output from the forward path of the k-1-th basic delay unit. <k>、FN <k>After the forward path delay transmission, the output forward differential signal FP is generated<k+1> 、FN<k+1> ; 2 n +1 basic delay units are numbered starting from 0, k∈[0,2 n ];

[0013] At the same time, the reverse path input of the kth level basic delay unit receives the reverse differential clock signal BP output from the reverse path of the k+1th level basic delay unit.<k+1> , BN<k+1> , after delayed transmission through the reverse path, an output reverse differential signal BP is generated <k>、BN <k>;

[0014] 0≤k≤2 n ; Among them, the forward path input FP of the 0th level basic delay unit <0> 、FN <0> As the differential input CKIP and CKIN of the variable delay line, the reverse path output BP of the 0th level basic delay unit <0> , BN <0> The differential outputs CKP and CKN of the variable delay line are n The reverse path input BP of the basic delay unit is less than 2 n +1>、BN<2 n +1> Connect the power supply level and ground level separately.

[0015] Preferably, the control signals S0<2:0> of the 0th level basic delay unit are connected to T <0> , 0, 0; the first level basic delay unit control signal S1<2:0> is connected to T <1> 、T <0> , 0; k-th level basic delay unit control signal S k <2:0> are connected to T <k:k-2>, 2≤k≤2 n -2; 2nd n -1st level basic delay unit control signal S2 n -1 <2:0> are connected to 1, T<2 n -2>、T<2 n -3> 2nd n Level basic delay unit control signal S2 n <2:0> are connected to 1, 1, T<2 respectively n -2>.

[0016] Preferably: the k-th level basic delay unit includes: a forward path, a reverse path and a control circuit; 2 n +1 basic delay units are numbered starting from 0, k∈[0,2 n ];

[0017] The control circuit includes: an inverter I5 and a two-input NOR gate N0, a two-input NOR gate N1 and a two-input NOR gate N2;

[0018] The two input terminals of the two-input NOR gate N0 are connected to the control signal S <2> and S <1> The output is connected to the input of the inverter I5 and one input of the two-input NOR gate N1; the other input of the two-input NOR gate N1 is connected to one input of the two-input NOR gate N2, and the control signal S is connected together. <0> , the output end of the two-input NOR gate N1 generates a control signal KN; the other input end of the two-input NOR gate N2 is connected to the output end of the inverter I5, and the output end of the two-input NOR gate N2 generates a control signal K;

[0019] The forward path includes: inverter I1, inverter I2, inverter I3 and inverter I4;

[0020] The input of inverter I1 is connected to FP <k>, output terminal connected to FN<k+1> ;Inverter I2 input terminal connected to FN <k>, output terminal connected to FP<k+1> ;Inverter I3 input terminal connected to FN<k+1> , output terminal connected to FP<k+1> ;Inverter I4 input terminal connected to FP<k+1> , output terminal connected to FN<k+1> ;

[0021] The reverse path includes NMOS transistor M0, NMOS transistor M1, NMOS transistor M2, NMOS transistor M3, NMOS transistor M4, NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, and PMOS transistor M8, PMOS transistor M9, PMOS transistor M10, and PMOS transistor M11;

[0022] The source of the NMOS transistor M0 is connected to the ground potential, and the gate is connected to the reverse input differential clock BP<k+1> , the drain is connected to the source of NMOS transistor M4; the gate of NMOS transistor M4 is connected to the control signal K, the drain is connected to the drain of NMOS transistor M6, the drain of PMOS transistor M8, the drain of PMOS transistor M10, and the gate of PMOS transistor M11, and generates the output clock BN <k>; The source of NMOS transistor M1 is grounded, and the gate is connected to the reverse input clock BN<k+1> , the drain is connected to the source of NMOS transistor M5; the gate of NMOS transistor M5 is connected to the control signal K, the drain is connected to the drain of NMOS transistor M7, the drain of PMOS transistor M9, the drain of PMOS transistor M11, and the gate of PMOS transistor M10, and generates the output clock BP <k>; The source of NMOS transistor M2 is grounded, and the gate is connected to the forward output clock FP<k+1> , the drain is connected to the source of the NMOS transistor M6; the gate of the NMOS transistor M6 is connected to the control signal KN; the source of the NMOS transistor M3 is grounded, and the gate is connected to the forward output clock FN<k+1> , the drain is connected to the source of the NMOS transistor M7; the gate of the NMOS transistor M7 is connected to the control signal KN; the source of the PMOS transistor M8 is connected to the power supply potential, and the gate is connected to the external input bias voltage PVB; the source of the PMOS transistor M9 is connected to the power supply potential, and the gate is connected to the external input bias voltage PVB; the source of the PMOS transistor M10 is connected to the power supply potential; the source of the PMOS transistor M11 is connected to the power supply potential.

[0023] Preferably, when the control signal S<2:0>=111, the control signals K and KN are both at the ground level, the NMOS transistors M4 to M7 are all turned off, and the FP <k>、FN <k>Delay output to FN<k+1> , FP<k+1> , the forward path is connected; BP <k>、BN <k>Maintain level output and cut off the reverse path.

[0024] Preferably, when the control signal S<2:0>=110 or 100, the control signal K is at the ground level, KN is at the power supply level, the NMOS transistors M4 and M5 are turned off, the NMOS transistors M6 and M7 are turned on, and the FP <k>、FN <k>Delay output to FN<k+1> FP<k+1> , forward path is connected; FP<k+1> 、FN<k+1> Delay output to BN <k>、BP <k>; The forward path and the reverse path are short-circuited.

[0025] Preferably, when the control signal S<2:0>=000, the control signal K is at the power supply level, KN is at the ground level, the NMOS transistors M4 and M5 are turned on, the NMOS transistors M6 and M7 are turned off, and the FP <k>、FN <k>Delay output to FN<k+1> FP<k+1> , the forward path is connected; BP<k+1> , BN<k+1> Delay output to BN <k>、BP <k>, the reverse path is connected; at this time, the forward path and the reverse path independently delay the transmission clock signal.

[0026] Preferably: when the n-bit binary programming code W <n-1:0>When the corresponding decimal value is i, 0≤i≤2 n -1;

[0027] When i=0, the delay line length control signal T<2 n -2:0> all are logic "1" level;

[0028] when i=2 n -1, the delay line length control signal T<2 n -2:0> all are logic "0" level;

[0029] When 1≤i≤2 n -2, the delay line length control signal T<2 n -2:i> is logic "1" level, delay line length control signal T <i-1:0>is logic "0" level.

[0030] Preferably, n is a positive integer greater than or equal to 2.

[0031] The advantages of the present invention compared with the prior art are:

[0032] (1) The programmable delay line circuit for high-speed, low-jitter DLL provided by the present invention flexibly changes the length of the variable delay line through an innovative logic control circuit decoding method, thereby achieving flexible adjustment of the input clock delay.

[0033] (2) The programmable delay line circuit for high-speed, low-jitter DLL provided by the present invention can arbitrarily extend the delay line length, thereby reducing the delay of the basic delay unit, which can meet both a wide delay adjustment range and high delay adjustment accuracy.

[0034] (3) The programmable delay line for high-speed, low-jitter DLL provided by the present invention is generated by repeated cascading of basic delay units. The basic delay unit circuit structure is simple, which facilitates layout and device matching and is suitable for high-speed differential clock and low-jitter delay application requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of the programmable delay line circuit structure for a high-speed, low-jitter DLL provided by the invention;

[0036] Figure 2 A schematic diagram of the variable delay line circuit structure provided for the invention;

[0037] Figure 3 Schematic diagram of the basic delay unit structure provided by the invention. DETAILED DESCRIPTION

[0038] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that, unless there is a conflict, the embodiments of the present disclosure and the features described in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0039] like Figure 1 As shown, a programmable delay line circuit for high-speed and low-jitter DLL includes: a variable delay line circuit, a logic control circuit and a clock driving circuit.

[0040] The logic control circuit converts the external input n-bit delay line length programming code W <n-1:0>Decoded as 2 n -1-bit delay line length control signal T<2 n -2:0> and output to the variable delay line circuit to configure the delay line length;

[0041] The input end of the variable delay line circuit is connected to the external input differential clock signal CKIP, CKIN, and the delay line length control signal T<2 is output by the logic control circuit. n By changing the delay line length under the control of -2:0>, the input clock delay can be roughly adjusted. In addition, by changing the external input bias voltage PVB, the transmission delay of the delay line basic delay unit to the input clock can be finely adjusted, thereby achieving fine adjustment of the input clock delay. After the delay is adjusted by the above two mechanisms, the differential clock signals CKP and CKN are output and transmitted to the clock drive circuit.

[0042] The clock driving circuit receives the differential clock signals CKP and CKN output from the variable delay line circuit, amplifies the CKP and CKN clocks to restore them to full-amplitude square wave clock signals, and corrects the duty cycle and cross point; and outputs the adjusted differential clock signals CLKP and CLKN.

[0043] like Figure 2 As shown, the variable delay line circuit includes 2 n +1 basic delay unit with the same structure; 2 n +1 level basic delay units connected end to end;

[0044] By outputting the delay line length control signal T<2 in the logic control circuit n -2:0> control, change the number of accesses to the basic delay unit and roughly adjust the input clock delay.

[0045] The basic delay unit includes: a forward path and a reverse path; the forward path input of the kth level basic delay unit receives the forward differential clock signal FP output from the forward path of the k-1th level basic delay unit <k>、FN <k>After the forward path delay transmission, the output forward differential signal FP is generated<k+1> 、FN<k+1> ; 2 n +1 basic delay units are numbered starting from 0, k∈[0,2 n ]; At the same time, the reverse path input of the kth level basic delay unit receives the reverse differential clock signal BP from the reverse path output of the k+1th level basic delay unit<k+1> , BN<k+1> , after delayed transmission through the reverse path, an output reverse differential signal BP is generated <k>、BN <k>The k-th level basic delay unit receives the external input bias voltage PVB and adjusts the transmission delay of the basic delay unit to the input clock;

[0046] 0≤k≤2 n ; Among them, the forward path input FP of the 0th level basic delay unit <0> 、FN <0> As the differential input CKIP and CKIN of the variable delay line, the reverse path output BP of the 0th level basic delay unit <0> , BN <0> The differential outputs CKP and CKN of the variable delay line are n The reverse path input BP of the basic delay unit is less than 2 n +1>、BN<2 n +1> Connect the power supply level and ground level separately.

[0047] The variable delay line circuit receives the 2 output of the logic control circuit n -1 bit delay line length control signal T<2 n -2:0>, to configure the variable delay line length;

[0048] Among them, the control signals S0<2:0> of the 0th level basic delay unit are connected to T <0> , 0, 0; the first level basic delay unit control signal S1<2:0> is connected to T <1> 、T <0> , 0; k-th level basic delay unit control signal S k <2:0> are connected to T <k:k-2>, 2≤k≤2 n -2; 2nd n -1st level basic delay unit control signal S2 n -1 <2:0> are connected to 1, T<2 n -2>、T<2 n -3> 2nd n Level basic delay unit control signal S2 n <2:0> are connected to 1, 1, T<2 respectively n -2>.

[0049] like Figure 3 As shown, the k-th level basic delay unit includes: forward path, reverse path and control circuit; n +1 basic delay units are numbered starting from 0, k∈[0,2 n ];

[0050] The control circuit includes: an inverter I5 and a two-input NOR gate N0, a two-input NOR gate N1 and a two-input NOR gate N2;

[0051] The two input terminals of the two-input NOR gate N0 are connected to the control signal S <2> and S <1> The output is connected to the input of the inverter I5 and one input of the two-input NOR gate N1; the other input of the two-input NOR gate N1 is connected to one input of the two-input NOR gate N2, and the control signal S is connected together. <0> , the output end of the two-input NOR gate N1 generates a control signal KN; the other input end of the two-input NOR gate N2 is connected to the output end of the inverter I5, and the output end of the two-input NOR gate N2 generates a control signal K;

[0052] The forward path includes: inverter I1, inverter I2, inverter I3 and inverter I4;

[0053] The input of inverter I1 is connected to FP <k>, output terminal connected to FN<k+1> ;Inverter I2 input terminal connected to FN <k>, output terminal connected to FP<k+1> ;Inverter I3 input terminal connected to FN<k+1> , output terminal connected to FP<k+1> ;Inverter I4 input terminal connected to FP<k+1> , output terminal connected to FN<k+1> ;

[0054] The reverse path includes NMOS transistor M0, NMOS transistor M1, NMOS transistor M2, NMOS transistor M3, NMOS transistor M4, NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, and PMOS transistor M8, PMOS transistor M9, PMOS transistor M10, and PMOS transistor M11;

[0055] The source of the NMOS transistor M0 is connected to the ground potential, and the gate is connected to the reverse input differential clock BP<k+1> , the drain is connected to the source of NMOS transistor M4; the gate of NMOS transistor M4 is connected to the control signal K, the drain is connected to the drain of NMOS transistor M6, the drain of PMOS transistor M8, the drain of PMOS transistor M10, and the gate of PMOS transistor M11, and generates the output clock BN <k>; The source of NMOS transistor M1 is grounded, and the gate is connected to the reverse input clock BN<k+1> , the drain is connected to the source of NMOS transistor M5; the gate of NMOS transistor M5 is connected to the control signal K, the drain is connected to the drain of NMOS transistor M7, the drain of PMOS transistor M9, the drain of PMOS transistor M11, and the gate of PMOS transistor M10, and generates the output clock BP <k>; The source of NMOS transistor M2 is grounded, and the gate is connected to the forward output clock FP<k+1> , the drain is connected to the source of the NMOS transistor M6; the gate of the NMOS transistor M6 is connected to the control signal KN; the source of the NMOS transistor M3 is grounded, and the gate is connected to the forward output clock FN<k+1> , the drain is connected to the source of the NMOS transistor M7; the gate of the NMOS transistor M7 is connected to the control signal KN; the source of the PMOS transistor M8 is connected to the power supply potential, and the gate is connected to the external input bias voltage PVB; the source of the PMOS transistor M9 is connected to the power supply potential, and the gate is connected to the external input bias voltage PVB; the source of the PMOS transistor M10 is connected to the power supply potential; the source of the PMOS transistor M11 is connected to the power supply potential;

[0056] When the control signal S<2:0>=111, the control signals K and KN are both at ground level, and the NMOS transistors M4 to M7 are all turned off. <k>、FN <k>Delay output to FN<k+1> FP<k+1> , the forward path is connected; BP <k>、BN <k>Maintain level output and cut off the reverse path.

[0057] When the control signal S<2:0>=110 or 100, the control signal K is at the ground level, KN is at the power supply level, NMOS transistors M4 and M5 are turned off, NMOS transistors M6 and M7 are turned on, and FP <k>、FN <k>Delay output to FN<k+1> FP<k+1> , forward path is connected; FP<k+1> 、FN<k+1> Delay output to BN <k>、BP <k>; Forward path and reverse path are short-circuited;

[0058] When the control signal S<2:0>=000, the control signal K is the power supply level, KN is the ground level, NMOS transistors M4 and M5 are turned on, NMOS transistors M6 and M7 are turned off, and FP <k>、FN <k>Delay output to FN<k+1> , FP<k+1> , the forward path is connected; BP<k+1> , BN<k+1> Delay output to BN <k>、BP <k>, the reverse path is connected; at this time, the forward path and the reverse path independently delay the transmission clock signal.

[0059] The logic control circuit is programmed by an external input n-bit delay line length programming code W <n-1:0>, decoded to 2 n -1 bit delay line length control signal T<2 n -2:0>, you can change the delay chain length and thus change the output clock delay;

[0060] When the n-bit binary programming code W <n-1:0>When the corresponding decimal value is i, 0≤i≤2 n -1;

[0061] When i=0, the delay line length control signal T<2 n -2:0> all are logic "1" level;

[0062] when i=2 n -1, the delay line length control signal T<2 n -2:0> all are logic "0" level;

[0063] When 1≤i≤2 n -2, the delay line length control signal T<2 n -2:i> is logic "1" level, delay line length control signal T <i-1:0>is logic "0" level.

[0064] n is a positive integer greater than or equal to 2. When n is 3, the decoding truth table of the logic control circuit is shown in Table 1.

[0065] Table 1 Truth table of logic control circuit

[0066]

[0067]

[0068] As shown in Table 1, when the n-bit programming code sets the delay chain length to i, T<2 n -2:i-2>=1, T <i-3:0>=0,3≤i≤2 n Therefore, when the 3-bit programming code W<2:0>=100, T<6:4>=1, T<3:0>=0; the control signal S<2:0> of the 6th to 8th level basic delay unit is 111; the control signal S<2:0> of the 5th level basic delay unit is 110; the control signal S<2:0> of the 4th level basic delay unit is 100; the control signal S<2:0> of the 0th to 3rd level basic delay unit is 000; at this time, the 0th to 3rd level delay units are in the state of independently delaying the transmission clock signal in the forward path and the reverse path respectively; the 6th to 8th level basic delay units are in the reverse path off state; the 4th to 5th level delay units are in the state of short-circuiting the forward path and the reverse path, and the delay line is cut off here; a total of 5 levels of basic delay units are connected to the delay chain.

[0069] Thus, it can be seen that the programmable delay line circuit for a high-speed, low-jitter DLL provided by the present invention flexibly changes the variable delay line length through an innovative logic control circuit decoding method, thereby achieving flexible adjustment of the input clock delay; the programmable delay line circuit for a high-speed, low-jitter DLL provided by the present invention can arbitrarily extend the delay line length, thereby reducing the delay of the basic delay unit, and can meet both a wide delay adjustment range and high delay adjustment accuracy; the programmable delay line for a high-speed, low-jitter DLL provided by the present invention is generated by repeatedly cascading basic delay units, and the basic delay unit circuit structure is simple, which facilitates layout and device matching, and is suitable for high-speed differential clock and low-jitter delay application requirements.

[0070] Although the present invention has been disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the scope of protection of the technical solutions of the present invention. < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k>

Claims

1. A programmable delay line circuit for a high-speed, low-jitter DLL, characterized in that: include: Variable delay line circuit, logic control circuit and clock drive circuit; The logic control circuit converts the external input n-bit delay line length programming code W <n-1:0>Decoded as 2 n -1-bit delay line length control signal T<2 n -2:0> and output to the variable delay line circuit to configure the delay line length; The input end of the variable delay line circuit is connected to the external input differential clock signal CKIP, CKIN, and the delay line length control signal T<2 is output by the logic control circuit. n -2:0> control to change the delay line length, thereby achieving coarse adjustment of the input clock delay; in addition, by changing the external input bias voltage PVB, the input clock delay can be finely adjusted; After adjusting the delay, the differential clock signals CKP and CKN are output and transmitted to the clock driving circuit; The clock driving circuit receives the differential clock signals CKP and CKN output from the variable delay line circuit, amplifies the CKP and CKN clocks to restore them to full-amplitude square wave clock signals, and corrects the duty cycle and cross point; and outputs the adjusted differential clock signals CLKP and CLKN.

2. The programmable delay line circuit for a high-speed, low-jitter DLL according to claim 1, wherein: The variable delay line circuit comprises 2 n +1 basic delay unit with the same structure; 2 n +1 level basic delay units connected end to end; By outputting the delay line length control signal T<2 in the logic control circuit n -2:0> control, change the number of accesses to the basic delay unit and roughly adjust the input clock delay.

3. A programmable delay line circuit for a high-speed, low-jitter DLL according to claim 2, characterized in that: The basic delay unit includes: a forward path and a reverse path; The forward path input of the k-th basic delay unit receives the forward differential clock signal FP output from the forward path of the k-1-th basic delay unit. <k>、FN <k>After the forward path delay transmission, the output forward differential signal FP is generated<k+1> 、FN<k+1> ; 2 n +1 basic delay units are numbered starting from 0, k∈[0,2 n ];< / k> < / k> At the same time, the reverse path input of the kth level basic delay unit receives the reverse differential clock signal BP output from the reverse path of the k+1th level basic delay unit.<k+1> , BN<k+1> , after delayed transmission through the reverse path, an output reverse differential signal BP is generated <k>、BN <k> ；< / k> < / k> 0≤k≤2 n ; Among them, the forward path input FP of the 0th level basic delay unit <0> 、FN <0> As the differential input CKIP and CKIN of the variable delay line, the reverse path output BP of the 0th level basic delay unit <0> , BN <0> The differential outputs CKP and CKN of the variable delay line are n The reverse path input BP of the basic delay unit is less than 2 n +1>、BN<2 n +1> Connect the power supply level and ground level separately.

4. The programmable delay line circuit for a high-speed, low-jitter DLL according to claim 3, wherein: The control signals S0<2:0> of the 0th level basic delay unit are connected to T <0> , 0, 0; the first level basic delay unit control signal S1<2:0> is connected to T <1> 、T <0> , 0; k-th level basic delay unit control signal S k <2:0> are connected to T <k:k-2>, 2≤k≤2 n -2; 2nd n -1st level basic delay unit control signal S2 n -1 <2:0> are connected to 1, T<2 n -2>、T<2 n -3> 2nd n Level basic delay unit control signal S2 n <2:0> are connected to 1, 1, T<2 respectively n -2>.

5. The programmable delay line circuit for a high-speed, low-jitter DLL according to claim 4, wherein: The k-th level basic delay unit also includes: a control circuit; n +1 basic delay units are numbered starting from 0, k∈[0,2 n ]; The control circuit includes: an inverter I5 and a two-input NOR gate N0, a two-input NOR gate N1 and a two-input NOR gate N2; The two input terminals of the two-input NOR gate N0 are connected to the control signal S <2> and S <1> The output is connected to the input of the inverter I5 and one input of the two-input NOR gate N1; the other input of the two-input NOR gate N1 is connected to one input of the two-input NOR gate N2, and the control signal S is connected together. <0> , the output end of the two-input NOR gate N1 generates a control signal KN; the other input end of the two-input NOR gate N2 is connected to the output end of the inverter I5, and the output end of the two-input NOR gate N2 generates a control signal K; The forward path includes: inverter I1, inverter I2, inverter I3 and inverter I4; The input of inverter I1 is connected to FP <k>, output terminal connected to FN<k+1> ;Inverter I2 input terminal connected to FN <k> , output terminal connected to FP<k+1> ;Inverter I3 input terminal connected to FN<k+1> , output terminal connected to FP<k+1> ;Inverter I4 input terminal connected to FP<k+1> , output terminal connected to FN<k+1> ;< / k> < / k> The reverse path includes NMOS transistor M0, NMOS transistor M1, NMOS transistor M2, NMOS transistor M3, NMOS transistor M4, NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, and PMOS transistor M8, PMOS transistor M9, PMOS transistor M10, and PMOS transistor M11; The source of the NMOS transistor M0 is connected to the ground potential, and the gate is connected to the reverse input differential clock BP<k+1> , the drain is connected to the source of NMOS transistor M4; the gate of NMOS transistor M4 is connected to the control signal K, the drain is connected to the drain of NMOS transistor M6, the drain of PMOS transistor M8, the drain of PMOS transistor M10, and the gate of PMOS transistor M11, and generates the output clock BN <k>; The source of NMOS transistor M1 is grounded, and the gate is connected to the reverse input clock BN<k+1> , the drain is connected to the source of NMOS transistor M5; the gate of NMOS transistor M5 is connected to the control signal K, the drain is connected to the drain of NMOS transistor M7, the drain of PMOS transistor M9, the drain of PMOS transistor M11, and the gate of PMOS transistor M10, and generates the output clock BP <k> ; The source of NMOS transistor M2 is grounded, and the gate is connected to the forward output clock FP<k+1> , the drain is connected to the source of the NMOS transistor M6; the gate of the NMOS transistor M6 is connected to the control signal KN; the source of the NMOS transistor M3 is grounded, and the gate is connected to the forward output clock FN<k+1> , the drain is connected to the source of the NMOS transistor M7; the gate of the NMOS transistor M7 is connected to the control signal KN; the source of the PMOS transistor M8 is connected to the power supply potential, and the gate is connected to the external input bias voltage PVB; the source of the PMOS transistor M9 is connected to the power supply potential, and the gate is connected to the external input bias voltage PVB; the source of the PMOS transistor M10 is connected to the power supply potential; the source of the PMOS transistor M11 is connected to the power supply potential.< / k> < / k> 6. A programmable delay line circuit for a high-speed, low-jitter DLL according to claim 5, characterized in that: When the control signal S<2:0>=111, the control signals K and KN are both at ground level, and the NMOS transistors M4 to M7 are all turned off. <k>、FN <k>Delay output to FN<k+1> , FP<k+1> , the forward path is connected; BP <k>、BN <k> Maintain level output and cut off the reverse path.< / k> < / k> < / k> < / k> 7. A programmable delay line circuit for a high-speed, low-jitter DLL according to claim 5, characterized in that: When the control signal S<2:0>=110 or 100, the control signal K is at the ground level, KN is at the power supply level, NMOS transistors M4 and M5 are turned off, NMOS transistors M6 and M7 are turned on, and FP <k>、FN <k>Delay output to FN<k+1> FP<k+1> , forward path is connected; FP<k+1> 、FN<k+1> Delay output to BN <k>、BP <k> ; The forward path and the reverse path are short-circuited.< / k> < / k> < / k> < / k> 8. The programmable delay line circuit for a high-speed, low-jitter DLL according to claim 5, wherein: When the control signal S<2:0>=000, the control signal K is the power supply level, KN is the ground level, NMOS transistors M4 and M5 are turned on, NMOS transistors M6 and M7 are turned off, and FP <k>、FN <k>Delay output to FN<k+1> FP<k+1> , the forward path is connected; BP<k+1> , BN<k+1> Delay output to BN <k>、BP <k> , the reverse path is connected; at this time, the forward path and the reverse path independently delay the transmission clock signal.< / k> < / k> < / k> < / k> 9. A programmable delay line circuit for a high-speed, low-jitter DLL according to any one of claims 1 to 8, characterized in that: When the n-bit binary programming code W <n-1:0>When the corresponding decimal value is i, 0≤i≤2 n -1; When i=0, the delay line length control signal T<2 n -2:0> all are logic "1" level; when i=2 n -1, the delay line length control signal T<2 n -2:0> all are logic "0" level; When 1≤i≤2 n -2, the delay line length control signal T<2 n -2:i> is logic "1" level, delay line length control signal T <i-1:0>is logic "0" level.< / i-1:0> 10. The programmable delay line circuit for a high-speed, low-jitter DLL according to claim 9, wherein: n is a positive integer greater than or equal to 2.

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