Cache water level control device, method, electronic device and storage medium

Abstract

The embodiment of the present application provides a control device, method, electronic device and storage medium for the cache water level, and relates to the field of data cache technology. The device includes: a water level adjustment module, which is used to adjust the current water level of the cache based on the currently executed frequency chasing mode; a water level detection module, which is used to detect in real time the current water level of the cache adjusted based on the currently executed frequency chasing mode; a mode switching module, which is used to switch the currently executed frequency chasing mode to the active frequency chasing mode if it is determined that the currently executed frequency chasing mode is a passive frequency chasing mode and the current water level does not meet the first preset condition, until it is determined that the current water level is at a balanced water level; the embodiment of the present application can always maintain the dynamic balance of the cache water level, even if the write clock frequency provided by the source end has a certain unidirectional deviation, the read clock frequency on the other side of the cache can also cope with this deviation, so that the cache will not overflow or the data volume will be insufficient, which greatly improves the scope of application of the cache.

Description

Technical Field

[0001] The present application relates to the technical field of data caching, and in particular to a cache water level control device, method, electronic device and storage medium. Background Art

[0002] HDMI (High Definition Multimedia Interface) is a fully digital video and audio interface that can transmit uncompressed multimedia data, such as audio data, video data, etc. When multimedia data is transmitted through HDMI, the sending end of the multimedia data is the source end, and the receiving end of the multimedia data is the sink end. The sink end includes a fifo buffer and a phase-locked loop PLL (Phase Locked Loop). The fifo (First in first out) buffer can temporarily store the multimedia data sent by the source end. The premise for the normal playback of multimedia data is that the speed of writing multimedia data to the fifo buffer and the speed of reading multimedia data from the fifo buffer are in a dynamic balance, which requires that the clock frequencies at both ends of the fifo buffer are the same, that is, the write clock frequency corresponding to the write pointer and the read clock frequency corresponding to the read pointer are the same. The write clock frequency is provided by the source end, and the read clock is generated by the PLL in the sink end according to the write clock frequency sent by the source end and related parameters (such as the cycle time counter CTS). In order to ensure the read-write balance at both ends of the fifo buffer, the generated read clock frequency needs to be adjusted in real time, that is, frequency tracking.

[0003] The traditional frequency tracking method strictly depends on the write clock frequency and related parameters sent by the source end. The write clock frequency and related parameters sent by the source end need to meet the preset requirements, which places high requirements on the source end. This type of frequency tracking is passive frequency tracking. However, there are a variety of corresponding source products on the market, and not all sources can strictly meet the requirements. If passive frequency tracking is performed when the write clock frequency and related parameters of the source end do not meet the preset requirements, the fifo cache will be empty for a short time or overflow temporarily, resulting in poor audio or video playback. Summary of the invention

[0004] The present application provides a control device and method for a cache water level, an electronic device, a computer-readable storage medium, and a computer program product, which can solve the problems in the background technology. The technical solution is as follows:

[0005] According to a first aspect of an embodiment of the present application, a buffer water level control device is provided.

[0006] Application sink, the device includes:

[0007] A water level adjustment module, used to adjust the current water level of the cache based on the currently executed frequency tracking mode;

[0008] A water level detection module, used for real-time detection of the current water level of the cache adjusted based on the currently executed frequency tracking mode;

[0009] A mode switching module, configured to switch the currently executed frequency chasing mode to an active frequency chasing mode if it is determined that the currently executed frequency chasing mode is a passive frequency chasing mode and the current water level does not meet the first preset condition, until it is determined that the current water level is at a balanced water level;

[0010] Among them, the active frequency tracking mode is used to iteratively update the cached read clock frequency based on the changing first parameter, the first parameter of the current iteration cycle is determined based on the water level of the previous iteration cycle, and the passive frequency tracking mode is used to generate the cached read clock frequency based on the fixed second parameter.

[0011] In a possible implementation, the mode switching module determines the first parameter of the current iteration cycle in the following manner:

[0012] Determine each sampling period in the historical period corresponding to the current iteration period; each sampling period is an iteration period;

[0013] Determine the water level difference of each sampling period, the water level difference being the difference between the high water level warning line and the water level of the corresponding sampling period or the difference between the water level of the corresponding sampling period and the low water level warning line;

[0014] Based on the water level difference in each sampling period, determine the distribution of water level difference in the historical period;

[0015] The first parameter of the current iteration cycle is determined according to the distribution of water level differences in the historical period.

[0016] In a possible implementation, the water level adjustment module includes an active frequency tracking submodule for executing an active frequency tracking mode;

[0017] The active frequency tracking submodule is specifically used to determine a first target frequency division coefficient according to a first parameter of a current iteration cycle, and send the first target frequency division coefficient to a phase-locked loop corresponding to the cache to instruct the phase-locked loop to generate a read clock frequency according to the first target frequency division coefficient.

[0018] In a possible implementation, the active frequency tracking submodule includes:

[0019] A frequency division coefficient acquisition unit, used to acquire a first target frequency division coefficient of a previous iteration cycle, and determine a first integer frequency division coefficient and a first decimal frequency division coefficient in the first target frequency division coefficient of the previous iteration cycle;

[0020] A step value determination unit, used to determine a first step value corresponding to a first integer frequency division coefficient and a second step value corresponding to a first decimal frequency division coefficient according to a first parameter of a current iteration cycle;

[0021] A frequency division coefficient updating unit, configured to update the first integer frequency division coefficient according to the first step value to obtain the second integer frequency division coefficient of the current iteration cycle; and update the first decimal frequency division coefficient according to the second step value to obtain the second decimal frequency division coefficient of the current iteration cycle;

[0022] The frequency division coefficient determination unit is used to obtain a first target frequency division coefficient of a current iteration cycle according to the second integer frequency division coefficient and the second decimal frequency division coefficient.

[0023] In a possible implementation, the step value determination unit is specifically used to determine the step level corresponding to the first parameter of the current iteration cycle and the step parameter value corresponding to the step level; the step level is used to characterize the step degree;

[0024] Get the reference read clock frequency in the phase-locked loop and the third parameter sent by the source end;

[0025] According to the reference read clock frequency, the third parameter and the step parameter value, a first step value corresponding to the integer frequency division coefficient of the previous iteration cycle and a second step value corresponding to the fractional frequency division coefficient of the previous iteration cycle are obtained.

[0026] In a possible implementation, the current water level not meeting the first preset condition includes the current water level being higher than a high water level warning line;

[0027] The frequency division coefficient update unit is specifically used to determine the first sum between the first integer frequency division coefficient and the first step value if it is determined that the current water level is higher than the high water level warning line, and use the first sum as the second integer frequency division coefficient of the current iteration cycle; determine the second sum between the first decimal frequency division coefficient and the second step value, and use the second sum as the second decimal frequency division coefficient of the current iteration cycle.

[0028] In a possible implementation, the current water level not meeting the first preset condition includes the current water level being lower than a low water level warning line;

[0029] Specifically, if it is determined that the current water level is lower than the low water level warning line, the frequency division coefficient update unit determines a first difference between the first integer frequency division coefficient and the first step value, and uses the first difference as the second integer frequency division coefficient of the current iteration cycle; determines a second difference between the first decimal frequency division coefficient and the second step value, and uses the second difference as the second decimal frequency division coefficient of the current iteration cycle.

[0030] In a possible implementation, the device further includes:

[0031] The acquisition module is used to obtain the clock quality of the source end and the maximum rated water level of the cache; the clock quality is used to characterize the fluctuation of the write clock frequency;

[0032] The warning line setting module is used to determine the high water level warning line and the low water level warning line of the cache according to the maximum rated water level and the clock quality.

[0033] In a possible implementation, the water level adjustment module further includes a passive frequency tracking submodule for executing an active frequency tracking mode;

[0034] The passive frequency tracking submodule is specifically used to determine a second target frequency division coefficient of the phase-locked loop according to the second parameter, send the second target frequency division coefficient to the phase-locked loop, and instruct the phase-locked loop to determine the read clock frequency according to the second target frequency division coefficient.

[0035] According to a second aspect of an embodiment of the present application, a method for controlling a cache water level is provided, using a sink end, the method comprising:

[0036] Adjust the current water level of the cache based on the currently executed frequency tracking mode;

[0037] Real-time detection of the current water level of the cache based on the currently executed frequency tracking mode adjustment;

[0038] If it is determined that the currently executed frequency chasing mode is the passive frequency chasing mode and the current water level does not meet the first preset condition, the currently executed frequency chasing mode is switched to the active frequency chasing mode until it is determined that the current water level is at the balanced water level;

[0039] Among them, the active frequency tracking mode is used to iteratively update the cached read clock frequency based on the changing first parameter, the first parameter of the current iteration cycle is determined based on the water level of the previous iteration cycle, and the passive frequency tracking mode is used to generate the cached read clock frequency based on the fixed second parameter.

[0040] According to a third aspect of the embodiments of the present application, an electronic device is provided, and the electronic device is the device provided in the first aspect.

[0041] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method provided in the second aspect are implemented.

[0042] According to the fifth aspect of the embodiment of the present application, a computer program product is provided, which includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. When a processor of a computer device reads the computer instructions from the computer-readable storage medium, the processor executes the computer instructions, so that the computer device executes the steps of implementing the method provided in the second aspect.

[0043] The beneficial effects of the technical solution provided by the embodiment of the present application are:

[0044] The embodiment of the present application can adjust the current water level of the cache based on the currently executed frequency chasing mode. If it is determined that the currently executed frequency chasing mode is a passive frequency chasing mode and the current water level does not meet the first preset condition, the currently executed frequency chasing mode is switched to an active frequency chasing mode until the current water level is determined to be at a balanced water level, wherein the active frequency chasing mode is used to iteratively update the read clock frequency of the cache based on a changed first parameter, and the first parameter of the current iteration cycle is determined based on the water level of the previous iteration cycle. The embodiment of the present application can always maintain the dynamic balance of the cache water level. Even if there is a certain unidirectional deviation in the write clock frequency provided by the source end, the read clock frequency on the other side of the cache can also cope with this deviation, so that the cache will not overflow or the amount of data will be insufficient, which greatly improves the scope of application of the cache, and thus improves the scope of use of the sink end. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in describing the embodiments of the present application.

[0046] Figure 1 A schematic diagram of the structure of a buffer water level control device provided in an embodiment of the present application;

[0047] Figure 2 A schematic diagram of various water level lines set for a fifo cache is provided for an embodiment of the present application;

[0048] Figure 3 A flow chart of a method for controlling a cache water level provided in an embodiment of the present application;

[0049] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0051] It will be understood by those skilled in the art that, unless specifically stated, the singular forms "one", "an" and "the" used herein may also include plural forms. It should be further understood that the terms "including" and "comprising" used in the embodiments of the present application refer to that the corresponding features can be implemented as the presented features, information, data, steps, operations, elements and / or components, but do not exclude the implementation as other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. It should be understood that when we call an element "connected" or "coupled" to another element, the one element can be directly connected or coupled to the other element, or it can refer to that the one element and the other element establish a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used here may include wireless connection or wireless coupling. The term "and / or" used here indicates at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or as "B", or as "A and B".

[0052] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0053] First, several terms involved in this application are introduced and explained:

[0054] Write clock frequency. In the embodiment of the present application, the frequency corresponding to the write clock is referred to as the write clock frequency.

[0055] Read clock frequency. In the embodiment of the present application, the frequency corresponding to the read clock is referred to as the read clock frequency.

[0056] The following describes several exemplary embodiments to illustrate the technical solutions of the embodiments of the present application and the technical effects produced by the technical solutions of the present application. It should be noted that the following embodiments can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different embodiments will not be described repeatedly.

[0057] The present application provides a cache water level control device 10, which uses a sink end, such as Figure 1 As shown, the cache water level control device 10 includes:

[0058] A water level adjustment module 110, configured to adjust a current water level of the cache based on a currently executed frequency tracking mode;

[0059] A water level detection module 120, for detecting in real time the current water level of the cache adjusted based on the currently executed frequency tracking mode;

[0060] A mode switching module 130, configured to switch the currently executed frequency chasing mode to an active frequency chasing mode if it is determined that the currently executed frequency chasing mode is a passive frequency chasing mode and the current water level does not meet the first preset condition, until it is determined that the current water level is at a balanced water level;

[0061] Among them, the active frequency tracking mode is used to iteratively update the cached read clock frequency based on the changing first parameter, the first parameter of the current iteration cycle is determined based on the water level of the previous iteration cycle, and the passive frequency tracking mode is used to generate the cached read clock frequency based on the fixed second parameter.

[0062] The cache in the embodiment of the present application can be any type of cache that can temporarily store data, such as a fifo cache. The fifo cache is a storage device that implements first-in-first-out data and is generally used as a data buffer. It can also be used for buffering sequential data, such as buffering multimedia data. The multimedia data can be, for example, audio data, video data, image data, etc.

[0063] The basic unit of the fifo cache is a register. As a storage device, the storage capacity of the fifo cache is determined by the number of storage registers defined internally. The number of storage registers is characterized by the maximum rated water level, that is, the maximum rated water level of the fifo cache represents the storage capacity of the fifo cache.

[0064] The fifo cache is located at the sink end. The sink end receives multimedia data sent from the source end and stores the multimedia data in the fifo cache. The fifo cache itself is a first-in-first-out device. The multimedia data can be written into the fifo cache through the write pointer and read from the fifo cache through the read pointer.

[0065] The current water level is the difference between the address of the write pointer and the address of the read pointer; the write pointer is used to write multimedia data to the cache according to the write clock frequency, and the read pointer is used to read multimedia data from the cache according to the read clock frequency; the first preset condition includes that the current water level is between the high water level warning line and the low water level warning line;

[0066] The speed at which the write pointer writes multimedia data into the fifo buffer is determined by the write clock frequency, and the speed at which the read pointer reads multimedia data from the fifo buffer is determined by the read clock frequency. To ensure normal playback of multimedia data, the read clock frequency and the write clock frequency at both ends of the fifo buffer need to be in a dynamic balance.

[0067] If the read clock frequency is greater than the write clock frequency, that is, the read pointer reads multimedia data faster than the write pointer writes multimedia data, it is likely that the amount of data in the cache is insufficient and the cache may be empty at certain times; if the read clock frequency is less than the write clock frequency, that is, the read pointer reads multimedia data slower than the write pointer writes multimedia data, it is likely that the amount of data in the cache is excessive and data overflow occurs. Both situations will cause abnormal multimedia data playback. Therefore, it is crucial that the read clock frequency and the write clock frequency are in a dynamic balance.

[0068] The embodiment of the present application uses the current water level of the cache to characterize the current amount of data in the cache. The data in the cache is first-in-first-out. The current water level is the difference between the address of the write pointer and the address of the read pointer. When the cache is initialized, the cache can be set to write from a low address to a high address. When the address of the write pointer meets the requirements, the read pointer is allowed to read data from the cache. Specifically, for example, at the time of initialization, the address at which the write pointer starts writing audio data is 0. When the address of the write pointer is 128, the read pointer is allowed to read data from the cache. The current water level can be determined later by the difference between the address of the write pointer and the address of the read pointer.

[0069] The cache generally has a corresponding overflow water level, including an upper overflow water level (overflow) and a lower overflow water level (underflow). The upper overflow water level is lower than the maximum rated water level. If the current water level exceeds the upper overflow water level, it indicates that there is too much data in the cache, which will cause data overflow. When the overflow occurs, data loss will cause playback abnormalities. If the current water level is lower than the lower overflow water level, it indicates that there is insufficient data in the cache, which will also cause playback abnormalities when the cache is empty.

[0070] The embodiment of the present application sets a balance water level for the cache, and the balance water level is located near the middle water level (the middle water level is half of the maximum rated water level, and the middle water level also belongs to the balance water level). The water level that fluctuates up and down near the middle water level is called the balance water level. Assuming that the maximum rated water level is 256, the middle water level is 128, and the balance water level can fluctuate within the range of 5, that is, the water level within the range of 128-5 to 128+5 can be called the balance water level.

[0071] It can be understood that when the current water level exceeds the upper overflow water level, in order to avoid data overflow, the read clock frequency needs to be increased to make the read clock read data from the cache faster, thereby pulling the current water level toward the equilibrium water level; when the current water level is lower than the lower overflow water level, in order to avoid the cache being empty, the read clock frequency needs to be lowered to make the read clock read data from the cache slower, also to pull the current water level toward the equilibrium water level.

[0072] However, when the current water level exceeds the upper overflow water level, adjusting the read clock frequency may not be able to effectively avoid data overflow. When the current water level is lower than the lower overflow water level, adjusting the read clock frequency may not be able to effectively avoid data shortage. To avoid the above situation, the embodiment of the present application sets a water level warning line for the cache. When the current water level exceeds the high warning line or is lower than the low warning line, the read clock frequency is immediately adjusted. The specific process of setting the water level warning line is shown in the subsequent embodiments.

[0073] The water level warning line in the embodiment of the present application includes a high water level warning line and a low water level warning line. The high water level warning line is located between the upper overflow water level and the balance water level; the low water level warning line is located between the balance water level and the lower overflow water level.

[0074] like Figure 2 As shown, it exemplarily shows a schematic diagram of the various water level lines set for the cache in an embodiment of the present application, the maximum rated water level of the cache is 256, the write pointer starts writing multimedia data from 0, the middle water level is 128, the balance water level is a water level in the range of 123 to 133, the upper overflow water level is 224, the lower overflow water level is 32, the high water level warning line is 192, and the low water level warning line is 64.

[0075] After obtaining the current water level, in the embodiment of the present application, if the current water level is between the high water level warning line and the low water level warning line, it is determined that the current water level meets the first preset condition; if the current water level exceeds the high water level warning line or is lower than the low water level warning line, it is determined that the current water level does not meet the first preset condition.

[0076] The embodiment of the present application provides two frequency tracking modes, an active frequency tracking mode and a passive frequency tracking mode. In the process of adjusting the current water level of the cache in the passive frequency tracking mode, if the current water level does not meet the first preset condition, the currently executed frequency tracking mode is switched to the active frequency tracking mode until it is determined that the current water level is at a balanced water level. After determining that the current water level is at a balanced water level, the frequency tracking mode is switched to the passive frequency tracking mode. In actual development, the frequency tracking mode can be switched through an enable signal. For example, when the enable signal is 1, it indicates that the frequency tracking mode is switched to the active frequency tracking mode. When the enable signal is 0, it indicates that the frequency tracking mode is switched to the passive frequency tracking mode.

[0077] The read clock frequency is generated by the phase-locked loop PLL. The PLL can generate the read clock frequency according to the division coefficient. The division coefficient is a parameter recognizable by the PLL. Whether it is passive frequency tracking or active frequency tracking, the parameters involved need to be converted into division coefficients recognizable by the PLL so that the PLL can generate the read clock frequency according to the division coefficient. In the embodiment of the present application, the division coefficient generated in the active frequency tracking mode is referred to as the first target division coefficient, and the division coefficient generated in the passive frequency tracking mode is referred to as the second target division coefficient.

[0078] The active frequency tracking mode of the embodiment of the present application is used to iteratively update the cached read clock frequency based on a changed first parameter, and the first parameter of the current iteration cycle is determined based on the water level of the previous iteration cycle.

[0079] The process of active frequency tracking continuously adjusts the read clock frequency. The read clock frequency is not static. When the current water level exceeds the high water level warning line, the read clock frequency is continuously increased. The read clock frequency is increased step by step during the iterative update process. In the process of continuously increasing the read clock frequency, the current water level is continuously adjusted to the balanced water level; when the current water level is lower than the low water level warning line, the read clock frequency is continuously reduced. The read clock frequency is reduced step by step during the iterative update process. In the process of continuously reducing the read clock frequency, the current water level is continuously adjusted to the balanced water level.

[0080] In the active frequency tracking mode, the iterative update of the read clock frequency is essentially an iterative update of the first target frequency division coefficient. The first target frequency division coefficient is in the iterative update. The PLL implements the iterative update of the read clock frequency according to the first target frequency division coefficient of each iteration cycle.

[0081] In the embodiment of the present application, the first target frequency division coefficient of each iteration cycle is determined by iterative updating based on the changed first parameter, and the first parameter of the current iteration cycle is determined based on the water level of the previous iteration cycle.

[0082] The passive frequency tracking mode of the embodiment of the present application is used to generate a second target frequency division coefficient of the phase-locked loop based on a fixed second parameter, and send the second target frequency division coefficient to the phase-locked loop, and instruct the phase-locked loop to determine the read clock frequency according to the second target frequency division coefficient. The fixed second parameter is a parameter sent by the source end, such as the write clock frequency (TMDS CLK) sent by the source end, CTS (Cycle time counter), a pre-set multiple parameter N and other parameters. The detailed process is shown in the subsequent content.

[0083] When the embodiment of the present application determines that the currently executed frequency chasing mode is the passive frequency chasing mode and the current water level does not meet the first preset condition, the currently executed frequency chasing mode is switched to the active frequency chasing mode until it is determined that the current water level is at the equilibrium water level. The dynamic balance of the cache water level can always be maintained. Even if there is a certain unidirectional deviation in the write clock frequency provided by the source end, the read clock frequency on the other side of the cache can cope with this deviation, so that the cache will not overflow or the data volume will be insufficient, which greatly improves the scope of application of the cache, and further improves the scope of use of the sink end.

[0084] A possible implementation method is provided in an embodiment of the present application. The mode switching module specifically determines the first parameter of the current iteration cycle in the following manner:

[0085] Determine each sampling period in the historical period corresponding to the current iteration period; each sampling period is an iteration period;

[0086] Determine the water level difference of each sampling period, the water level difference being the difference between the high water level warning line and the water level of the corresponding sampling period or the difference between the water level of the corresponding sampling period and the low water level warning line;

[0087] Based on the water level difference in each sampling period, determine the distribution of water level difference in the historical period;

[0088] The first parameter of the current iteration cycle is determined according to the distribution of water level differences in the historical period.

[0089] In the embodiment of the present application, each iteration cycle has a corresponding historical period, each historical period includes multiple sampling periods, each sampling period is an iteration cycle, for example, each historical period includes 10 sampling periods, then the historical period actually includes the current iteration cycle and the 9 iteration cycles before the current iteration cycle.

[0090] In the embodiment of the present application, each sampling cycle includes multiple small cycles, and each small cycle is the time required to write a multimedia data into the cache and read a multimedia data from the cache. The time corresponding to each small cycle is relatively short. During this small cycle, the water level in the cache changes slightly. If a sampling cycle includes a small number of small cycles, the sampling cycle is short and cannot reflect the change in water level. If a sampling cycle includes a large number of small cycles, the sampling cycle is long and the water level may change significantly. In this case, it may be too late to adjust the water level. To avoid the above situation, the time of each sampling cycle needs to be reasonably set, for example, each sampling cycle is set to include 2048 small cycles.

[0091] In the embodiment of the present application, the duration corresponding to an iteration cycle and the duration corresponding to a sampling cycle are the same, each iteration cycle corresponds to a sampling cycle, and the historical time period corresponding to each iteration cycle is different. Taking a sampling cycle as 2048 small cycles and the historical time period of the current iteration cycle including 10 sampling cycles as an example, it can be determined that a historical time period includes 20480 small cycles, and each sampling cycle in the historical time period of the current iteration cycle includes a sampling cycle corresponding to the current iteration cycle and the sampling cycles corresponding to the 9 iteration cycles before the current iteration cycle.

[0092] The embodiment of the present application can determine the water level difference of each sampling period. The water level difference of each sampling period can be the average water level difference of each sampling period, which is the difference between the high water level warning line and the water level of a sampling period or the difference between the water level of a sampling period and the low water level warning line. The water level of a sampling period in the embodiment of the present application can be the average of the water levels of the sampling period.

[0093] The water level differences of each sampling period in the historical period corresponding to the current iteration period of the embodiment of the present application determine the distribution trend of the water level differences in the historical period. The distribution trend of the water level differences can be characterized by a target value obtained by dividing the root mean square value of the water level differences by the number of sampling periods, or can be characterized by other methods.

[0094] Specifically, assuming that the water level differences in each sampling period in the historical period are Δa1, Δa2Δa3, Δa4, Δa5, Δa6, Δa7, Δa8, Δa9 and Δa10 respectively, the target value k can be:

[0095]

[0096] The distribution trend of the water level difference can be characterized by the above target value k.

[0097] After determining the distribution of water level differences in historical time periods of the current iteration cycle, the embodiment of the present application can determine the first parameter of the current iteration cycle based on the distribution of water level differences in historical time periods. Specifically, for example, the distribution of water level differences can be used as the first parameter of the current iteration cycle.

[0098] In an embodiment of the present application, a possible implementation is provided, where the water level adjustment module includes an active frequency tracking submodule for executing an active frequency tracking mode;

[0099] The active frequency tracking submodule is specifically used to determine a first target frequency division coefficient according to a first parameter of a current iteration cycle, and send the first target frequency division coefficient to a phase-locked loop corresponding to the cache to instruct the phase-locked loop to generate a read clock frequency according to the first target frequency division coefficient.

[0100] After determining the distribution trend of the water level difference in the historical time period of the current iteration cycle, the embodiment of the present application determines the first parameter of the current iteration cycle according to the distribution of the water level difference in the historical time period, determines the first target division coefficient of the cached phase-locked loop according to the first parameter of the current iteration cycle, sends the first target division coefficient to the phase-locked loop, and instructs the phase-locked loop to iteratively update the read clock frequency according to the first target division coefficient. Since the read clock frequency is generated based on the distribution trend of the water level difference, the water level in the cache can be adjusted to avoid overflow or insufficient data.

[0101] A possible implementation method is provided in an embodiment of the present application, where the active frequency tracking submodule includes:

[0102] A frequency division coefficient acquisition unit, used to acquire a first target frequency division coefficient of a previous iteration cycle, and determine a first integer frequency division coefficient and a first decimal frequency division coefficient in the first target frequency division coefficient of the previous iteration cycle;

[0103] A step value determination unit, used to determine a first step value corresponding to a first integer frequency division coefficient and a second step value corresponding to a first decimal frequency division coefficient according to a first parameter of a current iteration cycle;

[0104] A frequency division coefficient updating unit, configured to update the first integer frequency division coefficient according to the first step value to obtain the second integer frequency division coefficient of the current iteration cycle; and update the first decimal frequency division coefficient according to the second step value to obtain the second decimal frequency division coefficient of the current iteration cycle;

[0105] The frequency division coefficient determination unit is used to obtain a first target frequency division coefficient of a current iteration cycle according to the second integer frequency division coefficient and the second decimal frequency division coefficient.

[0106] In the active frequency tracking mode, in the embodiment of the present application, the first target frequency division coefficient is continuously iteratively updated, and the first target frequency division coefficient of the current iteration cycle is generated based on the first target frequency division coefficient of the previous iteration cycle. The initial first target frequency division coefficient can be pre-set according to the clock quality of the source end, and the clock quality is used to characterize the fluctuation of the write clock frequency. The initial first target frequency division coefficient can also be the second target frequency division coefficient at the end of the passive frequency tracking mode.

[0107] In the embodiment of the present application, the target value obtained by dividing the root mean square by the sampling period can represent the first parameter of the current iteration period. If the first parameter is large, it represents the need to significantly adjust the read clock frequency. Correspondingly, the step value of the first target division coefficient is also large.

[0108] The division coefficient includes an integer division coefficient and a fractional division coefficient. In the embodiment of the present application, the integer division coefficient in the first target division coefficient of the previous iteration cycle is referred to as the first integer division coefficient, and the fractional division coefficient in the first target division coefficient of the previous iteration cycle is referred to as the first fractional division coefficient.

[0109] The embodiment of the present application can determine the first step value corresponding to the first integer division coefficient and the second step value corresponding to the first decimal division coefficient according to the first parameter of the current iteration cycle, update the first integer division coefficient according to the first step value to obtain the second integer division coefficient of the current iteration cycle; update the first decimal division coefficient according to the second step value to obtain the second decimal division coefficient of the current iteration cycle.

[0110] After determining the second integer frequency division coefficient and the second fractional frequency division coefficient, the sum of the second integer frequency division coefficient and the second fractional frequency division coefficient is used as the first target frequency division coefficient of the current iteration cycle.

[0111] In the next iteration cycle, the first target frequency division coefficient of the current iteration cycle will be used as the first target frequency division coefficient of the new previous iteration cycle, corresponding to the new first integer frequency division coefficient and the new first fractional frequency division coefficient.

[0112] A possible implementation manner is provided in the embodiments of the present application.

[0113] The step value determination unit is specifically configured to determine the step level corresponding to the first parameter of the current iteration cycle and the step parameter value corresponding to the step level; the step level is used to characterize the step degree.

[0114] Obtain the reference read clock frequency in the phase-locked loop and the third parameter sent by the source end.

[0115] According to the reference read clock frequency, the third parameter, and the step parameter value, obtain the first step value corresponding to the integer frequency division coefficient of the previous iteration cycle and the second step value corresponding to the fractional frequency division coefficient of the previous iteration cycle.

[0116] After determining the first parameter of the current iteration cycle in the embodiments of the present application, it is necessary to determine the step level to which the first parameter of the current iteration cycle belongs, and determine the step parameter value corresponding to the step level. The step level is used to characterize the step degree.

[0117] Specifically, the embodiments of the present application can set a preset number of step levels according to actual situations, and each step level has a corresponding step parameter value. For example, 7 step levels are set as step0, step1, step2, step3, step4, step5, and step6 respectively.

[0118] Assume that the first parameter of the current iteration cycle is characterized by the target value obtained by dividing the root mean square by the sampling period, and the target value is k. If 0 ≤ k ≤ 1, then determine the step level as step0; if 1 < k ≤ 10, then determine the step level as step1; if 10 < k ≤ 20, then determine the step level as step2; if 20 < k ≤ 30, then determine the step level as step3; if 30 < k ≤ 40, then determine the step level as step4; if 40 < k ≤ 50, then determine the step level as step5; if k > 50, then determine the step level as step6. Each step level has a corresponding step parameter value. The larger the step level, the larger the step parameter value, and the larger the obtained step value.

[0119] When the embodiments of the present application iteratively update the first target frequency division coefficient through the active frequency tracking mode, the first step value corresponding to the integer frequency division coefficient of the previous iteration cycle and the second step value corresponding to the fractional frequency division coefficient of the previous iteration cycle are generated based on the reference read clock frequency in the phase-locked loop, the third parameter sent by the source end, and the step parameter value. The type of the third parameter is related to the type of the multimedia data.

[0120] For audio data, the third parameter sampling rate fs and the preset frequency multiplication factor N can be specifically obtained by the following formula 1 to obtain the first step value, and the following formula 2 to obtain the second step value. Formula 1 is:

[0121]

[0122] Wherein, step_M represents the first step value corresponding to the integer frequency division coefficient, the initial value of step_M is 0, step_number represents the step parameter value, that is, the step parameter value corresponding to any one of the step levels of step0, step1, step2, step3, step4, step5 and step6, DIVB is the frequency division coefficient set by the phase-locked loop for the read clock frequency to be generated, fs represents the sampling rate, N represents the frequency multiplication coefficient, and Fref represents the preset read clock frequency in the phase-locked loop;

[0123] Formula 2 is:

[0124]

[0125] Wherein, step_K represents the second step value corresponding to the fractional frequency division coefficient, the initial value of step_K is 0.1*524288, step_number represents the step parameter value, that is, the step parameter value corresponding to any one of the step levels of step0, step1, step2, step3, step4, step5 and step6, DIVB is the frequency division coefficient set by the phase-locked loop for the read clock frequency to be generated, fs represents the sampling rate, N represents the frequency multiplication coefficient, and Fref represents the read clock frequency preset in the phase-locked loop;

[0126] For other multimedia data, they all have corresponding third parameters, and the embodiments of the present application will not give examples one by one here.

[0127] A possible implementation method is provided in an embodiment of the present application, where the current water level does not meet the first preset condition, including that the current water level is higher than the high water level warning line;

[0128] The frequency division coefficient update unit is specifically used to determine the first sum between the first integer frequency division coefficient and the first step value if the current water level is higher than the high water level warning line, and use the first sum as the second integer frequency division coefficient of the current iteration cycle; determine the second sum between the first decimal frequency division coefficient and the second step value, and use the second sum as the second decimal frequency division coefficient of the current iteration cycle.

[0129] In the embodiment of the present application, the current water level does not meet the first preset condition, including the current water level being higher than the high water level warning line. When the current water level is higher than the high water level warning line, it is necessary to continuously increase the read clock frequency. Since there is a positive correlation between the read clock frequency and the first target division coefficient, it is necessary to continuously increase the first target division coefficient.

[0130] When the current water level is higher than the high water level warning line, determine the first sum between the first integer frequency division coefficient and the first step value, and use the first sum as the second integer frequency division coefficient of the current iteration cycle; determine the second sum between the first decimal frequency division coefficient and the second step value, and use the second sum as the second decimal frequency division coefficient of the current iteration cycle.

[0131] A possible implementation method is provided in an embodiment of the present application, where the current water level does not meet the first preset condition, including that the current water level is lower than a low water level warning line;

[0132] The frequency division coefficient update unit is specifically used to determine the first sum between the first integer frequency division coefficient and the first step value if the current water level is higher than the high water level warning line, and use the first sum as the second integer frequency division coefficient of the current iteration cycle; determine the second sum between the first decimal frequency division coefficient and the second step value, and use the second sum as the second decimal frequency division coefficient of the current iteration cycle.

[0133] In the embodiment of the present application, the current water level does not meet the first preset condition, including that the current water level is lower than the low water level warning line. Since there is a positive correlation between the read clock frequency and the first target division coefficient, when the current water level is lower than the low water level warning line, the read clock frequency needs to be continuously reduced, that is, the first target division coefficient needs to be continuously reduced.

[0134] When the current water level is lower than the low water level warning line, determine the first difference between the first integer frequency division coefficient and the first step value, and use the first difference as the second integer frequency division coefficient of the current iteration cycle; determine the second difference between the first decimal frequency division coefficient and the second step value, and use the second difference as the second decimal frequency division coefficient of the current iteration cycle.

[0135] A possible implementation method is provided in an embodiment of the present application, and the device further includes:

[0136] The acquisition module is used to obtain the clock quality of the source end and the maximum rated water level of the cache; the clock quality is used to characterize the fluctuation of the write clock frequency;

[0137] The warning line setting module is used to determine the high water level warning line and the low water level warning line of the cache according to the maximum rated water level and the clock quality.

[0138] In the embodiment of the present application, the high water level warning line and the low water level warning line of the cache can be determined according to the clock quality of the source end and the maximum rated water level of the cache. The clock quality is used to characterize the fluctuation of the write clock frequency. The middle water level line, the balance water level line, the overflow water level and the underflow water level of the cache can be determined according to the maximum rated water level. The high water level warning line is located between the upper overflow water level and the balance water level, and the low water level warning line is located between the lower overflow water level and the balance water level. The range between the high water level warning line and the low water level warning line is called an alarm. If the write clock frequency fluctuates greatly, the high water level warning line is set slightly away from the balance water level, but not exceeding the overflow water level, and the low water level warning line is set slightly away from the balance water level, but not lower than the overflow water level. That is, when the write clock frequency fluctuates greatly, the alarm range is larger, so that the active frequency chasing mode can be started quickly; if the write clock frequency fluctuates slightly, the high water level warning line and the low water level warning line are set slightly close to the balance water level, that is, when the write clock frequency fluctuates slightly, the alarm range is smaller, so that the passive frequency chasing mode can be started quickly.

[0139] In an embodiment of the present application, a possible implementation method is provided, where the water level adjustment module further includes a passive frequency tracking submodule for executing an active frequency tracking mode;

[0140] The passive frequency tracking submodule is specifically used to determine a second target frequency division coefficient of the phase-locked loop according to the second parameter, send the second target frequency division coefficient to the phase-locked loop, and instruct the phase-locked loop to determine the read clock frequency according to the second target frequency division coefficient.

[0141] In the process of determining the read clock frequency through the passive frequency tracking mode, if the current water level meets the first preset condition, the frequency tracking mode will not be switched, that is, the passive frequency tracking mode will always be maintained. In the process of iteratively updating the read clock frequency through the active frequency tracking mode, if it is determined that the current water level is at a balanced water level, the frequency tracking mode will be switched to the passive frequency tracking mode.

[0142] In the embodiment of the present application, when performing passive frequency tracking, the second target frequency division coefficient can be directly determined according to the second parameter pre-input at the source end, and the second target frequency division coefficient can be sent to the phase-locked loop, and the phase-locked loop can be instructed to determine the read clock frequency according to the second target frequency division coefficient.

[0143] The second parameter in the embodiment of the present application is related to the type of multimedia data, and both audio data and video data have their corresponding second parameters.

[0144] Specifically, assuming that the multimedia data is audio data, the second parameter includes the write clock frequency (TMDS CLK) sent by the source end, CTS (Cycle time counter), a pre-set multiple parameter N and other parameters. These parameters satisfy (TMDS CLK / CTS)*N=128fs, wherein TMDS CLK represents the write clock frequency, CTS represents the cycle time counter, and N is the multiplication factor. Through these parameters, the second target division coefficient can be obtained, and the second target division coefficient is input into the PLL, and the PLL can generate a corresponding read clock frequency according to the division coefficient.

[0145] The present application embodiment provides a method for controlling a cache water level using a sink end, such as Figure 3 As shown, the cache water level control method may include:

[0146] Step S301, adjusting the current water level of the cache based on the currently executed frequency tracking mode;

[0147] Step S302, real-time detection of the current water level of the buffer adjusted based on the currently executed frequency tracking mode;

[0148] Step S303, if it is determined that the currently executed frequency chasing mode is the passive frequency chasing mode and the current water level does not meet the first preset condition, the currently executed frequency chasing mode is switched to the active frequency chasing mode until it is determined that the current water level is at the equilibrium water level;

[0149] Among them, the active frequency tracking mode is used to iteratively update the cached read clock frequency based on the changing first parameter, the first parameter of the current iteration cycle is determined based on the water level of the previous iteration cycle, and the passive frequency tracking mode is used to generate the cached read clock frequency based on the fixed second parameter.

[0150] When the embodiment of the present application determines that the currently executed frequency chasing mode is the passive frequency chasing mode and the current water level does not meet the first preset condition, the currently executed frequency chasing mode is switched to the active frequency chasing mode until it is determined that the current water level is at the equilibrium water level. The dynamic balance of the cache water level can always be maintained. Even if there is a certain unidirectional deviation in the write clock frequency provided by the source end, the read clock frequency on the other side of the cache can cope with this deviation, so that the cache will not overflow or the data volume will be insufficient, which greatly improves the scope of application of the cache, and further improves the scope of use of the sink end.

[0151] In an embodiment of the present application, a possible implementation method is provided, in which the first parameter of the current iteration cycle is determined in the following manner:

[0152] Determine each sampling period in the historical period corresponding to the current iteration period; each sampling period is an iteration period;

[0153] Determine the water level difference of each sampling period, the water level difference being the difference between the high water level warning line and the water level of the corresponding sampling period or the difference between the water level of the corresponding sampling period and the low water level warning line;

[0154] Based on the water level difference in each sampling period, determine the distribution of water level difference in the historical period;

[0155] The first parameter of the current iteration cycle is determined according to the distribution of water level differences in the historical period.

[0156] A possible implementation method is provided in an embodiment of the present application, and executing the active frequency tracking mode includes: determining a first target division coefficient of a cached phase-locked loop according to a first parameter of a current iteration cycle, sending the first target division coefficient to the phase-locked loop, and instructing the phase-locked loop to generate a read clock frequency according to the first target division coefficient.

[0157] In an embodiment of the present application, a possible implementation method is provided, which determines a first target frequency division coefficient of a cached phase-locked loop according to a first parameter of a current iteration cycle, including:

[0158] Acquire a first target frequency division coefficient of a previous iteration cycle, and determine a first integer frequency division coefficient and a first decimal frequency division coefficient in the first target frequency division coefficient of the previous iteration cycle;

[0159] Determine, according to the first parameter of the current iteration cycle, a first step value corresponding to the first integer frequency division coefficient and a second step value corresponding to the first decimal frequency division coefficient;

[0160] The first integer frequency division coefficient is updated according to the first step value to obtain the second integer frequency division coefficient of the current iteration cycle; the first decimal frequency division coefficient is updated according to the second step value to obtain the second decimal frequency division coefficient of the current iteration cycle;

[0161] A first target frequency division coefficient of a current iteration cycle is obtained according to the second integer frequency division coefficient and the second fractional frequency division coefficient.

[0162] In an embodiment of the present application, a possible implementation method is provided, which determines a first step value corresponding to a first integer frequency division coefficient and a second step value corresponding to a first decimal frequency division coefficient according to a first parameter of a current iteration cycle, including:

[0163] Determine the step level corresponding to the first parameter of the current iteration cycle and the step parameter value corresponding to the step level; the step level is used to characterize the step degree;

[0164] Get the reference read clock frequency in the phase-locked loop and the third parameter sent by the source end;

[0165] According to the reference read clock frequency, the third parameter and the step parameter value, a first step value corresponding to the integer frequency division coefficient of the previous iteration cycle and a second step value corresponding to the fractional frequency division coefficient of the previous iteration cycle are obtained.

[0166] A possible implementation method is provided in the embodiment of the present application.

[0167] The current water level does not meet the first preset condition, including that the current water level is higher than the high water level warning line;

[0168] The first integer frequency division coefficient is updated according to the first step value to obtain the second integer frequency division coefficient of the current iteration cycle, including:

[0169] If the current water level is higher than the high water level warning line, determine a first sum between the first integer frequency division coefficient and the first step value, and use the first sum as the second integer frequency division coefficient of the current iteration cycle;

[0170] The first fractional frequency division coefficient is updated according to the second step value to obtain the second fractional frequency division coefficient of the current iteration cycle, including:

[0171] If the current water level is higher than the high water level warning line, a second sum value between the first decimal frequency division coefficient and the second step value is determined, and the second sum value is used as the second decimal frequency division coefficient of the current iteration cycle.

[0172] A possible implementation method is provided in an embodiment of the present application, where the current water level does not meet the first preset condition, including that the current water level is lower than a low water level warning line;

[0173] The first integer frequency division coefficient is updated according to the first step value to obtain the second integer frequency division coefficient of the current iteration cycle, including:

[0174] If the current water level is lower than the low water level warning line, determine a first difference between the first integer frequency division coefficient and the first step value, and use the first difference as the second integer frequency division coefficient of the current iteration cycle;

[0175] The first fractional frequency division coefficient is updated according to the second step value to obtain the second fractional frequency division coefficient of the current iteration cycle, including:

[0176] If the current water level is lower than the low water level warning line, a second difference between the first fractional frequency division coefficient and the second step value is determined, and the second difference is used as the second fractional frequency division coefficient of the current iteration cycle.

[0177] A possible implementation method is provided in an embodiment of the present application, and the device further includes:

[0178] Get the clock quality of the source end and the maximum rated water level of the cache; the clock quality is used to characterize the fluctuation of the write clock frequency;

[0179] The cache's high and low water levels are determined based on the maximum rated water level and the clock quality.

[0180] The device of the embodiments of the present application can execute the method provided by the embodiments of the present application, and the implementation principles are similar. The actions performed by each module in the device of each embodiment of the present application correspond to the steps in the method of each embodiment of the present application. For the detailed functional description of each module of the device, please refer to the description in the corresponding method shown in the previous text, which will not be repeated here.

[0181] The embodiment of the present application provides an electronic device, which includes the aforementioned cache water level control device, and its implementation principle is similar. The embodiment of the present application will not be overly repeated here. Compared with the prior art, it can be achieved that: the embodiment of the present application can adjust the current water level of the cache based on the currently executed frequency chasing mode. If it is determined that the currently executed frequency chasing mode is a passive frequency chasing mode, and the current water level does not meet the first preset condition, the currently executed frequency chasing mode is switched to an active frequency chasing mode until it is determined that the current water level is at a balanced water level, wherein the active frequency chasing mode is used to iteratively update the cache read clock frequency based on a changed first parameter, and the first parameter of the current iteration cycle is determined based on the water level of the previous iteration cycle. The embodiment of the present application can always maintain the dynamic balance of the cache water level. Even if the write clock frequency provided by the source end has a certain unidirectional deviation, the read clock frequency on the other side of the cache can also cope with this deviation, so that the cache will not overflow or the amount of data is insufficient, which greatly improves the scope of application of the cache, and thus improves the scope of use of the sink end.

[0182] In an embodiment of the present application, another electronic device is provided, including a memory, a processor, and a computer program stored in the memory. The processor executes the computer program to implement the steps of the cache water level control method. Compared with the related art, the following can be achieved:

[0183] The embodiment of the present application can adjust the current water level of the cache based on the currently executed frequency chasing mode. If it is determined that the currently executed frequency chasing mode is a passive frequency chasing mode and the current water level does not meet the first preset condition, the currently executed frequency chasing mode is switched to an active frequency chasing mode until the current water level is determined to be at a balanced water level, wherein the active frequency chasing mode is used to iteratively update the read clock frequency of the cache based on a changed first parameter, and the first parameter of the current iteration cycle is determined based on the water level of the previous iteration cycle. The embodiment of the present application can always maintain the dynamic balance of the cache water level. Even if there is a certain unidirectional deviation in the write clock frequency provided by the source end, the read clock frequency on the other side of the cache can also cope with this deviation, so that the cache will not overflow or the amount of data will be insufficient, which greatly improves the scope of application of the cache, and thus improves the scope of use of the sink end.

[0184] In an alternative embodiment, an electronic device is provided, such as Figure 4 As shown, Figure 4 The electronic device 4000 shown includes: a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, such as through a bus 4002. Optionally, the electronic device 4000 may also include a transceiver 4004, which may be used for data interaction between the electronic device and other electronic devices, such as data transmission and / or data reception. It should be noted that in actual applications, the transceiver 4004 is not limited to one, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present application.

[0185] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It may implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of this application. Processor 4001 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0186] The bus 4002 may include a path to transmit information between the above components. The bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The bus 4002 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0187] The memory 4003 may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, optical disk storage (including compressed optical disk, laser disk, optical disk, digital versatile disk, Blu-ray disk, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium that can be used to carry or store computer programs and can be read by a computer, without limitation herein.

[0188] The memory 4003 is used to store the computer program for executing the embodiment of the present application, and the execution is controlled by the processor 4001. The processor 4001 is used to execute the computer program stored in the memory 4003 to implement the steps shown in the above method embodiment.

[0189] Among them, the electronic equipment package may include but is not limited to mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., as well as fixed terminals such as digital TVs, desktop computers, etc. Figure 4 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0190] The embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps and corresponding contents of the aforementioned method embodiment can be implemented. Compared with the prior art, the following can be implemented:

[0191] The embodiment of the present application can adjust the current water level of the cache based on the currently executed frequency chasing mode. If it is determined that the currently executed frequency chasing mode is a passive frequency chasing mode and the current water level does not meet the first preset condition, the currently executed frequency chasing mode is switched to an active frequency chasing mode until the current water level is determined to be at a balanced water level, wherein the active frequency chasing mode is used to iteratively update the read clock frequency of the cache based on a changed first parameter, and the first parameter of the current iteration cycle is determined based on the water level of the previous iteration cycle. The embodiment of the present application can always maintain the dynamic balance of the cache water level. Even if there is a certain unidirectional deviation in the write clock frequency provided by the source end, the read clock frequency on the other side of the cache can also cope with this deviation, so that the cache will not overflow or the amount of data will be insufficient, which greatly improves the scope of application of the cache, and thus improves the scope of use of the sink end.

[0192] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0193] The present application also provides a computer program product, including a computer program, which can implement the steps and corresponding contents of the above method embodiments when executed by a processor. Compared with the prior art, it can achieve:

[0194] The embodiment of the present application can adjust the current water level of the cache based on the currently executed frequency chasing mode. If it is determined that the currently executed frequency chasing mode is a passive frequency chasing mode and the current water level does not meet the first preset condition, the currently executed frequency chasing mode is switched to an active frequency chasing mode until the current water level is determined to be at a balanced water level, wherein the active frequency chasing mode is used to iteratively update the read clock frequency of the cache based on a changed first parameter, and the first parameter of the current iteration cycle is determined based on the water level of the previous iteration cycle. The embodiment of the present application can always maintain the dynamic balance of the cache water level. Even if there is a certain unidirectional deviation in the write clock frequency provided by the source end, the read clock frequency on the other side of the cache can also cope with this deviation, so that the cache will not overflow or the amount of data will be insufficient, which greatly improves the scope of application of the cache, and thus improves the scope of use of the sink end.

[0195] The terms "first", "second", "third", "fourth", "1", "2", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that shown or described in the drawings.

[0196] It should be understood that, although each operation step is indicated by arrows in the flowchart of the embodiment of the present application, the implementation order of these steps is not limited to the order indicated by the arrows. Unless clearly stated herein, in some implementation scenarios of the embodiment of the present application, the implementation steps in each flowchart can be performed in other orders according to demand. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, and each sub-step or stage in these sub-steps or stages may also be executed at different times respectively. In different scenarios of execution time, the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiment of the present application does not limit this.

[0197] The above are only optional implementation methods for some implementation scenarios of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A control device for a cache water level, characterized in that: Using a sink end, the device includes: A water level adjustment module, used to adjust the current water level of the cache based on the currently executed frequency tracking mode, wherein the frequency tracking mode includes a passive frequency tracking mode and an active frequency tracking mode; A water level detection module, used for real-time detection of the current water level of the cache adjusted based on the currently executed frequency tracking mode; A mode switching module, configured to switch the currently executed frequency chasing mode to an active frequency chasing mode if it is determined that the currently executed frequency chasing mode is a passive frequency chasing mode and the current water level does not meet a first preset condition, until it is determined that the current water level is at a balanced water level; Among them, the active frequency tracking mode is used to generate a first target division coefficient based on a changing first parameter, and the phase-locked loop PLL iteratively updates the cached read clock frequency according to the first target division coefficient. The first parameter of the current iteration cycle is determined based on the water level of the previous iteration cycle. The passive frequency tracking mode is used to generate a second target division coefficient based on a fixed second parameter, and the phase-locked loop PLL iteratively updates the cached read clock frequency according to the second target division coefficient.

2. The device according to claim 1, characterized in that The mode switching module specifically determines the first parameter of the current iteration cycle in the following manner: Determine each sampling period in the historical period corresponding to the current iteration period; each sampling period is an iteration period; Determine the water level difference of each sampling period, wherein the water level difference is the difference between the high water level warning line and the water level of the corresponding sampling period or the difference between the water level of the corresponding sampling period and the low water level warning line; Based on the water level differences of the respective sampling periods, determining the distribution of the water level differences within the historical period; The first parameter of the current iteration cycle is determined according to the distribution of the water level difference in the historical period.

3. The device according to claim 1 or 2, characterized in that: The water level adjustment module includes an active frequency tracking submodule for executing the active frequency tracking mode; The active frequency tracking submodule is specifically used to determine a first target frequency division coefficient according to a first parameter of the current iteration cycle, and send the first target frequency division coefficient to a phase-locked loop corresponding to the cache to instruct the phase-locked loop to generate a read clock frequency according to the first target frequency division coefficient.

4. The device according to claim 3, characterized in that The active frequency tracking submodule comprises: A frequency division coefficient acquisition unit, used to acquire a first target frequency division coefficient of a previous iteration cycle, and determine a first integer frequency division coefficient and a first decimal frequency division coefficient in the first target frequency division coefficient of the previous iteration cycle; a step value determining unit, configured to determine a first step value corresponding to the first integer frequency division coefficient and a second step value corresponding to the first decimal frequency division coefficient according to a first parameter of the current iteration cycle; A frequency division coefficient updating unit, configured to update the first integer frequency division coefficient according to the first step value to obtain a second integer frequency division coefficient of a current iteration period; and update the first decimal frequency division coefficient according to the second step value to obtain a second decimal frequency division coefficient of the current iteration period; The frequency division coefficient determining unit is used to obtain a first target frequency division coefficient of a current iteration cycle according to the second integer frequency division coefficient and the second fractional frequency division coefficient.

5. The device according to claim 4, characterized in that The step value determination unit is specifically used to determine the step level corresponding to the first parameter of the current iteration cycle and the step parameter value corresponding to the step level; the step level is used to characterize the step degree; Obtaining a reference read clock frequency in the phase-locked loop and a third parameter sent by a source end; According to the reference read clock frequency, the third parameter and the step parameter value, a first step value corresponding to the integer frequency division coefficient of the previous iteration cycle and a second step value corresponding to the fractional frequency division coefficient of the previous iteration cycle are obtained.

6. The device according to claim 4, characterized in that The current water level not meeting the first preset condition includes the current water level being higher than a high water level warning line; The frequency division coefficient updating unit is specifically used for determining a first sum value between the first integer frequency division coefficient and the first step value if it is determined that the current water level is higher than the high water level warning line, and using the first sum value as the second integer frequency division coefficient of the current iteration cycle; A second sum value between the first fractional frequency division coefficient and the second step value is determined, and the second sum value is used as the second fractional frequency division coefficient of the current iteration cycle.

7. The device according to claim 4, characterized in that The current water level not meeting the first preset condition includes the current water level being lower than a low water level warning line; If the current water level is determined to be lower than the low water level warning line, the frequency division coefficient updating unit determines a first difference between the first integer frequency division coefficient and the first step value, and uses the first difference as a second integer frequency division coefficient of the current iteration cycle; A second difference between the first fractional frequency division coefficient and the second step value is determined, and the second difference is used as the second fractional frequency division coefficient of the current iteration cycle.

8. The device according to claim 2, characterized in that The device also includes: An acquisition module, used to acquire the clock quality of the source end and the maximum rated water level of the cache; the clock quality is used to characterize the fluctuation of the write clock frequency; A warning line setting module is used to determine a high water level warning line and a low water level warning line of the cache according to the maximum rated water level and the clock quality.

9. The device according to claim 3, characterized in that The water level adjustment module further includes a passive frequency tracking submodule for executing the active frequency tracking mode; The passive frequency tracking submodule is specifically used to determine a second target frequency division coefficient of the phase-locked loop according to the second parameter, and send the second target frequency division coefficient to the phase-locked loop to instruct the phase-locked loop to determine a read clock frequency according to the second target frequency division coefficient.

10. A method for controlling a cache water level, characterized in that: Applying a sink end, the method includes: Adjusting the current water level of the cache based on the currently executed frequency tracking mode, wherein the frequency tracking mode includes a passive frequency tracking mode and an active frequency tracking mode; Real-time detection of the current water level of the cache based on the currently executed frequency tracking mode adjustment; If it is determined that the currently executed frequency chasing mode is a passive frequency chasing mode and the current water level does not meet the first preset condition, the currently executed frequency chasing mode is switched to an active frequency chasing mode until it is determined that the current water level is at a balanced water level; Among them, the active frequency tracking mode is used to generate a first target division coefficient based on a changing first parameter, and the phase-locked loop PLL iteratively updates the cached read clock frequency according to the first target division coefficient. The first parameter of the current iteration cycle is determined based on the water level of the previous iteration cycle. The passive frequency tracking mode is used to generate a second target division coefficient based on a fixed second parameter, and the phase-locked loop PLL iteratively updates the cached read clock frequency according to the second target division coefficient.

11. An electronic device comprising the device according to any one of claims 1 to 9.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to claim 10 are implemented.

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