A pixel circuit and a noise reduction method

Abstract

The present invention discloses a novel pixel circuit and noise reduction method, which is related to photoelectric detection and imaging, and proposes a solution to solve the incompatibility problem between global exposure and column-level CDS in the prior art. G ; Auxiliary pixel P G The production process and circuit structure of the auxiliary pixel P are the same as those of any APS. G One or more light shielding masks are arranged on the top; auxiliary pixels P G Perform spatial double sampling and perform analog and digital signal processing. The advantage is that the pixel operates at a high speed and the size of the suspended diffusion capacitor is not limited. Global exposure can be achieved at the array level. The spatial double sampling technology is used to first convert the output analog voltage into a temperature-independent quantity, and it can also reduce the FPN caused by dark current to a certain extent, and then further eliminate FPN through image processing methods at the digital signal stage. Compared with traditional active pixel circuits, it has lower noise, higher sensitivity, wider dynamic range and faster speed.

Description

Technical Field

[0001] The present invention relates to optoelectronic technology, and in particular to a pixel circuit and a noise reduction method. Background Art

[0002] At present, most image sensor chips based on CMOS technology use active pixel sensor (APS) circuits, which have bottlenecks in sensitivity, dynamic range, speed, etc. and cannot meet the needs of emerging applications. In addition, traditional APS arrays cannot take into account global exposure and column-level correlated double sampling (CDS). Although some existing designs use the intra-pixel CDS method to achieve the combination of the two, this will greatly increase the complexity of the pixel circuit, resulting in a decrease in the pixel fill factor and the resolution of the array.

[0003] Active pixel sensor APS is a basic unit of an image sensor chip. An array composed of this pixel unit can form an image. Each pixel sensor unit consists of a photosensitive unit and multiple transistors. Among them, the function of the photosensitive unit is to realize photoelectric conversion and convert incident photons into electrons. The current typical photosensitive unit design is a pinned photodiode (PPD). The functions of each transistor are to reset, transmit and select signals as a switch and to amplify signals as an amplifier. The transistors in APS are generally metal oxide semiconductor field effect transistors (MOSFET). The active pixel sensor was proposed to solve the shortcomings of passive pixel circuits, such as high noise, narrow dynamic range, low sensitivity, and the need to amplify signals outside the array.

[0004] The most widely used active pixel circuit at present is a four-transistor structure, called 4T-APS. Its circuit principle and structure are as follows: Figure 1 and Figure 2 The working principle of 4T-APS is as follows: first, the reset switch Trst and the transmission gate TX are turned on, and the floating diffusion capacitor C FD and the junction capacitance C of PPD PD The voltage on the PPD is charged to the reset voltage Vrst. After the reset is completed, Trst and TX are turned off. Then the pixel begins to be exposed. The PPD generates photogenerated charges under light. The generated electrons and holes move to the cathode and anode respectively, thereby recombining with the reset charge. The longer the exposure time, the more charge recombination. After the exposure is completed, TX is turned on for the second time. At this time, C PD The charge on the C FD Transfer, thereby C PD The charge change on the FDThe voltage changes on C FD Generally small, according to V=Q / C, C FD The voltage change on C PD The voltage changes on the TX pin, thereby realizing the conversion and amplification of the photogenerated charge to the voltage signal. After the conversion is completed, TX is turned off. Finally, the voltage signal is read out by selecting the switch Tsel. Tsf forms a voltage follower, which plays a role of buffer isolation in the circuit. The working timing diagram of 4T-APS is shown in Figure 3 shown.

[0005] Any technical solution for converting photoelectric signals on the plane of the pixel sensor array will encounter the problem of fixed pattern noise (FPN) caused by uneven manufacturing of the conversion array plane. The mechanisms of generating such noise on the conversion array plane of different solutions are not exactly the same. Due to the influence of fixed pattern noise, the sensor array will also output a fixed pattern signal in the absence of light signal illumination; and in the case of optical image illumination, this fixed pattern signal will be superimposed on the real image signal. The cause of FPN is the inconsistency of the parameter performance of pixel elements at different coordinate positions of the entire array. For CMOS image sensor arrays using APS, the sources of fixed pattern noise mainly include: inconsistent active transistor turn-on voltage Vth, inconsistent transistor on-resistance Ron as a switch, inconsistent thermal noise 4KTRon caused by inconsistent Ron, inconsistent dark current Idark of the photodiode (dark current is the reverse current generated by the photodiode in the absence of light), etc. From the expression of thermal noise (common knowledge), it can be seen that FPN is also affected by temperature. When the temperature of the environment in which the sensor array is located is different, FPN is also different, and it increases with the increase of temperature.

[0006] The main method to eliminate FPN is to use CDS technology. For 4T-APS, that is, CDS is used to eliminate FPN at different times. FD The voltage on the pixel is sampled twice, and then the sampled voltages are subtracted. The final output signal is the pure voltage change between the two sampling moments after FPN is filtered out. Considering the speed and circuit complexity, the current arrays basically adopt the row scan column readout mode, that is, a column of pixels shares the load current source and CDS circuit, but at the same time the CDS circuit only serves one pixel in a column. This CDS circuit is called column-level CDS. The schematic diagram of the column-level CDS circuit of 4T-APS is shown in the figure. Figure 4 The working timing diagram of the 4T-APS array CDS readout circuit is shown in Figure 5 After the reset is completed, Tsel can be turned on, but it is necessary to ensure that SCAfter Tsel is turned on, turn on T before TX is turned on for the second time. S1 , then C FD The reset voltage on the C is sampled as the first sampling voltage and stored in C S1 After the first sampling is completed, turn off T S1 After TX is turned on and off for the second time, T can be turned on. S2 At this time C FD The voltage on the C S2 After sampling is completed, turn off T S2 Finally, open T SC1 , T SC2 The two sampling voltages are respectively sent to the in-phase terminal and the inverting terminal of the differential amplifier circuit for difference and amplification, thereby obtaining a noise-reduced output signal.

[0007] In addition to FPN, another major factor affecting image quality is image lag, that is, the information reflected at different positions on the image does not come from the same time. This phenomenon must be avoided for some application scenarios. Therefore, a global exposure method should be used for the pixel array. For 4T-APS, the Reset and TX signals of the entire array are completely synchronized before the Select signal arrives, and the image information at different spatial positions is stored in C at the same time. FD The 4T-APS array is then read out in turn through the Select signal for subsequent processing. In the global exposure mode, the image information obtained by each pixel comes from the same moment, so there is no image lag. The timing diagram of the global exposure of the 4T-APS array is as follows: Figure 6 As shown in Figure 1, Texp is the exposure time, Trow is the time it takes to read out all the pixels in a row, and x represents the row that the array is currently reading out. From the principle of global exposure, we can know that column-level circuits cannot implement CDS, because a CDS circuit can only read the CDS of one pixel at a time. FD However, the reset operation of global exposure is performed on the entire array, so it is impossible to use the column-level CDS to perform the first sampling, that is, to read out and store the reset voltage Vrst of all pixels at the same time.

[0008] As mentioned above, global exposure is incompatible with column-level CDS, although some circuits have adopted the solution of intra-pixel CDS, that is, a CDS circuit is integrated in each pixel to ensure that each CDS circuit serves a pixel separately. However, this will greatly increase the complexity of the pixel circuit and cause a decrease in other aspects of pixel performance, such as fill factor and spatial resolution.

[0009] In summary, the shortcomings of the existing technology are:

[0010] 1. Due to the limitations of photosensitive elements and exposure methods, the sensitivity and dynamic range (sensitivity refers to the conversion gain when optical signals are converted into electrical signals, and dynamic range refers to the range between the weakest and strongest light that can be detected) of the existing 4T-APS have reached bottlenecks. Although these indicators can be slightly improved by optimizing the process, this structure can no longer meet some emerging application requirements.

[0011] 2. The existing 4T-APS circuit uses the redistribution of photogenerated charges between the photodiode junction capacitance and the suspended diffusion capacitance to achieve photoelectric conversion and signal amplification. However, the photogenerated current of the photodiode is very small, so the speed of charge accumulation is very slow. If you want to obtain a higher gain, that is, a higher sensitivity, the pixel exposure time will be very long. Therefore, the main problem of this pixel circuit is the slow working speed, which will affect the complexity of the array back-end circuit and the frame rate of the readout.

[0012] 3. The existing 4T-APS has a suspended diffusion capacitor C due to the need for sensitivity. FD must be much smaller than the junction capacitance C of the photodiode PD , but Little C FD This will increase the pixel reset noise (the noise generated by Ron of Trst and the associated capacitance during each reset operation is proportional to KT / C, where K is the Boltzmann constant, T is temperature, and C is capacitance).

[0013] 4. Existing active pixel sensor arrays cannot achieve the combination of global exposure and column-level correlated double sampling, and therefore cannot be applied to scenes with high requirements for image tailing and fixed pattern noise.

[0014] Related technology prior public documents: CN112510058A, PD-photosensitive diode. Summary of the invention

[0015] The present invention aims to provide a pixel circuit and a noise reduction method to solve the problems existing in the above-mentioned prior art.

[0016] A pixel circuit described in the present invention comprises: an APS array, a pixel reading unit and a digital processing unit;

[0017] Also includes an auxiliary pixel P arranged next to the APS array G The auxiliary pixel P G The production process and circuit structure of the auxiliary pixel P are the same as any APS in the APS array, and both adopt a 4T-APS structure; G One or more light-shielding masks are provided on the top;

[0018] The pixel reading unit is used to read the pixel voltage of the APS array pixel by pixel, and read the auxiliary pixel P at the same time when reading the pixel voltage of the APS array. G The voltage of the two voltages is input to the digital processing unit through an ADC after the difference and amplification;

[0019] The digital processing unit stores the received digital quantization values ​​corresponding to the positions in the APS array one by one to obtain array data after FPN removal.

[0020] The pixels and auxiliary pixels P of the APS array G Both use PD-MOS as photosensitive elements.

[0021] The digital processing unit presets a fixed noise template of the APS array, and the pixel reading unit subtracts the fixed noise template from the array data after FPN removal to obtain the final noise-reduced array data.

[0022] The fixed noise template is obtained by placing the APS array in a dark environment; the pixel reading unit reads the pixel voltage of the APS array pixel by pixel, and reads the auxiliary pixel P at the same time when reading the pixel voltage of the APS array. G The voltage is obtained by taking the difference and amplifying the two voltages, and then inputting them into the digital processing unit through the ADC; the digital processing unit stores the received digital quantization values ​​corresponding to the positions in the APS array one by one to obtain the fixed noise template.

[0023] The digital processing unit updates or resets the fixed noise template according to a user instruction.

[0024] The pixel reading unit includes at least three operational amplifiers and four resistors;

[0025] The in-phase terminal of the operational amplifier OPA1 is externally connected to the auxiliary pixel P G The voltage output end of the operational amplifier OPA1, the inverting end of the operational amplifier OPA1 is connected to its own output end, and the output end of the operational amplifier OPA1 is connected to the ground after passing through the resistor R2 and the resistor R3 in sequence;

[0026] The in-phase terminal of the operational amplifier OPA2 is externally connected to the voltage output terminal of the APS array, the inverting terminal of the operational amplifier OPA2 is connected to its own output terminal, and the output terminal of the operational amplifier OPA2 is connected to the input terminal of the ADC after passing through the resistor R1 and the resistor R4 in sequence;

[0027] The in-phase terminal of the operational amplifier OPA3 is connected to the connection point of the resistor R2 and the resistor R3, the inverting terminal of the operational amplifier OPA3 is connected to the connection point of the resistor R1 and the resistor R4, and the output terminal of the operational amplifier OPA3 is connected to the input terminal of the ADC;

[0028] And let the resistance ratio R3 / R2=R4 / R1=β, where β is the amplification factor of the pixel reading unit.

[0029] The noise reduction method in the present invention uses the pixel circuit to perform noise reduction.

[0030] The pixel circuit and noise reduction method described in the present invention have the advantages that the exposure method is used to improve the working speed of the pixel, and the size of the suspended diffusion capacitor is no longer limited. Under the condition that the area allows, the C FD Connect additional capacitors in parallel to reduce reset noise. At the array level, the 4T-APS architecture determines that global exposure can be achieved. To eliminate FPN, the spatial double sampling technology is used to first convert the output analog voltage into a temperature-independent quantity, and to a certain extent reduce the FPN caused by dark current. Then, the FPN is further eliminated through image processing methods at the digital signal stage. Compared with traditional active pixel circuits, it has lower noise, higher sensitivity, wider dynamic range and faster speed. The spatial double sampling scheme realizes the combination of global exposure and filtering out fixed pattern noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a circuit schematic diagram of 4T-APS in the prior art;

[0032] Figure 2 It is a schematic diagram of the structure of 4T-APS in the prior art;

[0033] Figure 3 It is a timing diagram of 4T-APS in the prior art;

[0034] Figure 4 It is a circuit schematic diagram of a 4T-APS column-level CDS in the prior art;

[0035] Figure 5 It is a timing diagram of a CDS readout circuit of a 4T-APS array in the prior art;

[0036] Figure 6 It is a timing diagram of global exposure of a 4T-APS array in the prior art;

[0037] Figure 7 is a structural schematic diagram of a pixel circuit described in the present invention;

[0038] Figure 8 is a circuit schematic diagram of the PD-MOS 4T-APS described in the present invention;

[0039] Fig. 9 is a schematic diagram of the structure of the PD-MOS 4T-APS described in the present invention;

[0040] Fig.10 is a timing diagram of the PD-MOS 4T-APS described in the present invention;

[0041] Fig.11 is a timing diagram of global exposure of the PD-MOS 4T-APS array described in the present invention;

[0042] Fig.12 It is a circuit schematic diagram of the PD-MOS 4T-APS in the present invention for performing spatial double sampling analog signal stage;

[0043] Fig.13 It is a timing diagram of the PD-MOS 4T-APS in the present invention performing spatial double sampling analog signal stage;

[0044] Fig.14 It is a schematic diagram of the working principle of the PD-MOS 4T-APS in the present invention in the spatial double sampling digital signal stage. DETAILED DESCRIPTION

[0045] The noise reduction method in the present invention is implemented by utilizing the pixel circuit under specific working requirements.

[0046] The specific structure and working principle of a pixel circuit described in the present invention are as follows: Figures 7 to 14 shown.

[0047] In this embodiment, based on the traditional 4T-APS architecture, the photosensitive element adopts a photoelectric conversion device PD-MOS, which uses the photoinduced deflection effect to indirectly convert the incident light into the drain-source current of the MOSFET, and has better sensitivity and dynamic range than traditional photodiodes, as recorded in the document with publication number CN112510058A. The PD-MOS is only a preferred option and should not be used as a specific limitation on the selection of the photosensitive element of the present invention.

[0048] Figure 8 , Fig. 9 The device structure diagram and equivalent circuit diagram of PD-MOS are shown respectively. The holes generated by the reverse-biased PD under illumination conditions diffuse through the anode to the substrate of the adjacent MOS tube, and the drain-source current is further changed by changing the substrate voltage and thus the threshold voltage of the MOS tube. The drain-source current is different when the illumination is different, so PD-MOS is actually a "light-controlled current source". In addition, the device can adjust the gain by controlling the gate voltage of the MOS tube. Thus, a pixel PD-MOS 4T-APS is formed, in which the output signal can fully inherit the characteristics of PD-MOS, so the pixel can obtain high sensitivity and wide dynamic range.

[0049] Because the substrate voltage of PD-MOS changes with light, it should be isolated from the substrates of other transistors. Here, the deep N-well (DNW) process is used to achieve this requirement. The drain of PD-MOS is connected to the left end of the transmission gate, and the source is grounded. The pixel circuit is divided into three stages: reset, integration, and readout. First, reset, that is, turn on Trst to charge the FD point voltage to a fixed value. This process is similar to 4T-APS, but here the transmission gate Ttx must be closed. After the reset is completed, Ttx can be turned on to use the drain-source current of PD-MOS to charge C FD Integrate, that is, discharge. Because the drain-source current of PD-MOS is different under different illumination, the degree of discharge is also different. FD Before the stored charge is discharged, turn off Ttx. FD The voltage stabilizes to a certain value. The voltage varies with different illumination. This integration process is also the pixel exposure process. Finally, V FD Read out, the working timing diagram of the entire pixel internal circuit is as follows Fig.10 shown.

[0050] The above integration process, i.e., exposure, is completely different from the traditional exposure method, and the exposure time is much shorter than the exposure time of the traditional APS. Therefore, this exposure method determines that the pixel can have a very fast working speed. Because a single pixel has an extremely high response speed, the array can adopt a row scanning and parallel column readout method, that is, a column selection switch is added to each column, and all columns share a back-end processing circuit, and the column selection switch is controlled by timing to select the output voltage of a pixel in the current column. This method will greatly reduce the complexity of the back-end analog circuit, so that more pixels can be integrated in the same area, that is, the resolution of the array can be improved. In addition, this high-speed feature will also increase the frame rate of the array readout.

[0051] Because of the different exposure methods, C FD The size of C is no longer limited by sensitivity requirements, so it can be increased by process adjustment. FD This reduces reset noise.

[0052] At the array level, the PD-MOS 4T-APS-based array can achieve global exposure. Its principle is the same as that of the traditional APS array, that is, the Trst of all pixels in the array must be turned on synchronously, and the Ttx must also be turned on synchronously, and then Tsel is turned on in sequence to read out the voltage signal. The timing diagram is shown in Fig.11 shown.

[0053] On the basis of achieving global exposure, fixed pattern noise needs to be removed, which is achieved by using spatial double sampling. It is divided into two parts: analog processing stage and digital processing stage.

[0054] Simulation processing stage: Schematic diagram as shown Fig.12 As shown, P A Represents a pixel in the APS array, P G It is an auxiliary pixel made in the adjacent position of the APS array with the same process as the pixel in the APS array, but the auxiliary pixel needs to be shielded. Due to the shielding process, the output voltage of the auxiliary pixel at any time is only caused by the dark current of the PD-MOS. In addition, the auxiliary pixel P G The Reset and TX timings are related to the pixel P A The same, but the Select timing is different. When the Select signal of each pixel in the APS array arrives, the auxiliary pixel P G The Tsel of each APS array must be turned on once, that is, the number of pixels P A , auxiliary pixel P G The Select signal has as many pulses as there are in one cycle. Vout0 is the auxiliary pixel P G The output obtained entirely by the dark current of PD-MOS, that is, the background noise of the pixel; Vout1 is the output of the pixel of the APS array under illumination. Operational amplifier OPA1 and operational amplifier OPA2 are two voltage followers, which act as buffers and isolate to prevent the output signal from being affected by the back-end circuit. Resistor R1, resistor R2, resistor R3, resistor R4 and operational amplifier OPA3 form a difference circuit; if the resistance ratio R3 / R2=R4 / R1=β, where β is the amplification factor of the pixel reading unit, then Vout=β·(Vout1-Vout0), so that different amplification factors can be obtained by adjusting the resistance value. The timing diagram of the spatial double sampling analog end circuit is as follows: Fig.13 Because only one pixel in the APS array is used as an example here, P G With P A The Select signal is the same. Those skilled in the art can undoubtedly know from the above technical analysis that if there are N P A , just change P G The Select signal frequency is set to P A The main function is to filter out the background noise caused by the dark current in the APS array. G With P A The noise caused by dark current is not exactly the same, but for the case of large dark current, this method will greatly improve the influence of the noise caused by dark current. In addition to reducing the influence of dark current, the noise in the output signal after difference calculation is weakly correlated with temperature. This is because P G With P AIn exactly the same temperature environment. After taking the difference, the difference in temperature-related noise (reset noise and thermal noise) between them is almost only related to the deviation of process parameters such as load capacitance and on-resistance, and has little to do with temperature changes. After basically solving the dynamic part of the noise, the remaining noise in the output signal can be approximately considered as a fixed noise, which can be solved in the digital processing stage.

[0055] Digital processing stage: The signal processed in the analog processing stage can be sent to the ADC to obtain the digital quantization value corresponding to different output voltages. The quantization value includes the fixed noise remaining after the analog end processing. Once the circuit is fixed on the circuit board or each APS is fixed on the chip, the fixed noise template of the APS array is obtained and pre-stored in the digital processing unit. Each subsequent analog processed array data is subtracted from the fixed noise template to obtain the final denoised array signal.

[0056] In order to obtain the fixed noise template, the entire APS array can be placed in a completely dark environment, and the temperature factor can be weakened by the above-mentioned analog processing method. At this time, the output digital signal is completely caused by the fixed noise. For a sensor array prepared and processed using a stable process, the fixed noise will not change with the external environment and time, and the digital signal output based on this will not change. Therefore, the image information of this frame under dark conditions can be saved as a template, and the information of this frame can be subtracted when processing each frame of the image later to achieve the purpose of filtering out the fixed noise.

[0057] In order to demonstrate the effect of the fixed noise template, the theoretical situation is as follows Fig.14 When uniform light is irradiated onto the APS array, after being processed by the pixel reading unit and ADC, the ideal image information obtained should be that the grayscale value of each pixel is exactly the same. However, due to the existence of fixed noise, the image information obtained is Fig.14 As shown in (a), the grayscale values ​​of each pixel are not completely consistent. Fig.14 (b) shows the fixed noise template, where a mn represents the output noise caused by the fixed deviation of PA and PG under dark conditions, and n and m represent the row and column numbers of the pixels respectively. Fig.14 (c) is the output image after being processed by the digital processing unit. Although it is not possible to completely filter out the noise, the noise reduction effect is very obvious.

[0058] In some special cases, such as poor shading effect when the fixed noise template is initially made, physical changes to a certain pixel caused by other physical factors, poor denoising due to human visual perception, etc., when the fixed noise template needs to be adjusted or updated, all pixels or any pixel can be changed according to user needs. This is because the fixed noise template is stored in digital form and can be adjusted / updated to the mobile phone processing unit at any time.

[0059] For those skilled in the art, various other corresponding changes and deformations can be made according to the technical solutions and concepts described above, and all of these changes and deformations should fall within the protection scope of the claims of the present invention.

Claims

1. A pixel circuit, comprising: APS array, pixel readout unit, and digital processing unit; It is characterized in that Also includes an auxiliary pixel P arranged next to the APS array G The auxiliary pixel P G The production process and circuit structure of the auxiliary pixel P are the same as any APS in the APS array, and both adopt a 4T-APS structure; G One or more light-shielding masks are provided on the top; The pixel reading unit is used to read the pixel voltage of the APS array pixel by pixel, and read the auxiliary pixel P at the same time when reading the pixel voltage of the APS array. G The voltage of the two voltages is input to the digital processing unit through an ADC after the difference and amplification; The digital processing unit stores the received digital quantization values ​​corresponding to the positions in the APS array one by one to obtain array data after FPN removal; The digital processing unit presets a fixed noise template of the APS array, and the pixel reading unit subtracts the fixed noise template from the array data after FPN removal to obtain the final noise-reduced array data; The fixed noise template is obtained by placing the APS array in a dark environment; the pixel reading unit reads the pixel voltage of the APS array pixel by pixel, and reads the auxiliary pixel P at the same time when reading the pixel voltage of the APS array. G The voltage is obtained by taking the difference and amplifying the two voltages, and then inputting them into the digital processing unit through the ADC; the digital processing unit stores the received digital quantization values ​​corresponding to the positions in the APS array one by one to obtain the fixed noise template.

2. A pixel circuit according to claim 1, characterized in that: The pixels and auxiliary pixels P of the APS array G Both use PD-MOS as photosensitive elements.

3. A pixel circuit according to claim 1, characterized in that: The digital processing unit updates or resets the fixed noise template according to a user instruction.

4. A pixel circuit according to claim 1, characterized in that: The pixel reading unit includes at least three operational amplifiers and four resistors; The in-phase terminal of the operational amplifier OPA1 is externally connected to the auxiliary pixel P G The voltage output end of the operational amplifier OPA1, the inverting end of the operational amplifier OPA1 is connected to its own output end, and the output end of the operational amplifier OPA1 is connected to the ground after passing through the resistor R2 and the resistor R3 in sequence; The in-phase terminal of the operational amplifier OPA2 is externally connected to the voltage output terminal of the APS array, the inverting terminal of the operational amplifier OPA2 is connected to its own output terminal, and the output terminal of the operational amplifier OPA2 is connected to the input terminal of the ADC after passing through the resistor R1 and the resistor R4 in sequence; The in-phase terminal of the operational amplifier OPA3 is connected to the connection point of the resistor R2 and the resistor R3, the inverting terminal of the operational amplifier OPA3 is connected to the connection point of the resistor R1 and the resistor R4, and the output terminal of the operational amplifier OPA3 is connected to the input terminal of the ADC; And let the resistance ratio R3 / R2=R4 / R1=β, where β is the amplification factor of the pixel reading unit.

5. A noise reduction method, characterized in that: Noise reduction is performed using a pixel circuit as described in any one of claims 1 to 4.

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