Method for adjusting threshold voltage balance of long and short channels based on ion implantation process

Abstract

The application provides a method for adjusting threshold voltage balance of long and short channel based on ion implantation process. A substrate is provided, and a plurality of gate structures are formed on the substrate. The substrate on both sides of the gate structure is provided with a groove located in a source and a drain region. Part of the grooves correspond to a first length of channel length, and the other part of the grooves correspond to a second length of channel length greater than the first length. The substrate at the groove is doped so that the threshold voltage at the groove with the first length (short channel) is reduced, and the threshold voltage at the groove with the second length (long channel) tends to be unchanged. An epitaxial layer filling the groove is formed. The threshold voltage of the short channel device is adjusted before the epitaxial layer is formed, so that the threshold voltage of the long and short channel devices is balanced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for adjusting the threshold voltage balance of long and short channels based on ion implantation process. Background Technology

[0002] In integrated circuit manufacturing, adjusting the threshold voltage of devices with different channel lengths is often involved. Generally, the Spice Model (semiconductor device model) requires that the threshold voltage of the long channel region be higher than that of the short channel region. However, in actual manufacturing, the threshold voltage of short-channel devices can become high due to various reasons, causing an imbalance between the threshold voltages of long and short channels and affecting the overall performance of the device.

[0003] Please see Figure 1 In the prior art, a substrate 101 is typically provided, on which multiple gate structures are formed. On both sides of the gate structure, grooves located in the source and drain regions are formed on the substrate 101. The length of some grooves is a first length, which is a short channel, and the length of other grooves is a second length greater than the first length, which is a long channel. Then, an epitaxial layer 105 as shown in Title 2 is formed at the groove.

[0004] Current methods for addressing high threshold voltage in short channels primarily focus on adjusting the germanium-silicon epitaxial (SiGe) or silicon-phosphorus (SiP) epitaxial processes. Taking the germanium-silicon epitaxial process as an example, increasing the concentration of boron ions in the germanium-silicon epitaxial layer can effectively reduce the threshold voltage in the short-channel region by diffusing boron ions into the channel. However, for the longer channel region, the small amount of boron ion diffusion has little impact on its threshold voltage.

[0005] The method of adjusting the threshold voltage balance of long and short channels through epitaxial processes is based on increasing the ion doping concentration of the epitaxial layer. However, a higher epitaxial ion doping concentration will cause instability at the interface between the epitaxial layer and silicon, resulting in a large number of dislocations and defects in the germanium-silicon epitaxial layer interface, causing strain relaxation in the germanium-silicon epitaxial layer, weakening the stress on the channel, and affecting the speed of the device.

[0006] To address the aforementioned issues, a novel method for adjusting the threshold voltage balance between long and short channels based on ion implantation technology is needed. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for adjusting the threshold voltage balance of long and short channels based on ion implantation process, which is used to solve the problem that the high epitaxial ion doping concentration in the prior art will cause instability of the epitaxial layer and silicon interface state, generate a large number of dislocations and defects in the germanium-silicon epitaxial layer interface layer, cause strain relaxation of germanium-silicon epitaxial layer, weaken the channel stress, and affect the speed of device.

[0008] To achieve the above and other related objectives, the present invention provides a method for adjusting the threshold voltage balance of long and short channels based on ion implantation technology, comprising:

[0009] Step 1: Provide a substrate on which a plurality of gate structures are formed. On both sides of the gate structures, grooves located in the source and drain regions are formed on the substrate. The length of some of the grooves is a first length, which is a short channel. The length of the other part of the grooves is a second length greater than the first length, which is a long channel.

[0010] Step 2: Doping the substrate at the groove reduces the channel voltage at the groove with the first length, while keeping the trench voltage at the groove with the second length relatively constant. The implantation of a small number of ions can effectively reduce the threshold voltage in the short channel region, while having little effect on the threshold voltage in the longer channel region, thereby achieving the purpose of adjusting the balance of threshold voltage between long and short channels.

[0011] Step 3: Form an epitaxial layer that fills the groove. This epitaxial layer can usually be formed by vapor phase epitaxy.

[0012] Preferably, the substrate in step one is a bulk semiconductor substrate or a silicon-on-insulator substrate.

[0013] Preferably, in step one, the groove is formed on the substrate using a dry etching method.

[0014] Preferably, the gate structure in step one includes a gate dielectric layer and a polysilicon gate stacked sequentially; a top hard mask layer is covered on top of the polysilicon gate, and sidewalls are formed on the sides of the polysilicon gate.

[0015] Preferably, the material of the top hard mask layer in step one includes silicon oxide or silicon nitride; the material of the sidewalls includes silicon oxide or silicon nitride.

[0016] Preferably, PMOS and NMOS are integrated on the substrate described in step one.

[0017] Preferably, before step two, a photolithography process is performed to open the formation region of the PMOS and cover the formation region of the NMOS, or a photolithography process is performed to open the formation region of the NMOS and cover the formation region of the PMOS.

[0018] Preferably, in step two, phosphorus ions are used to dope the groove in the formation region of the NMOS, or boron ions are used to dope the groove in the formation region of the PMOS.

[0019] Preferably, the doping concentration in step two is 1.0E14 to 1.0E16 Atom / cm³. 3 .

[0020] Preferably, the epitaxial layer in step three is a germanium-silicon epitaxial layer or a phosphorus-silicon epitaxial layer.

[0021] As described above, the method for adjusting the threshold voltage balance of long and short channels based on ion implantation process of the present invention has the following beneficial effects:

[0022] This invention balances the threshold voltages of long and short channel devices by adjusting the threshold voltage of short-channel devices before the epitaxial layer is formed. Attached Figure Description

[0023] Figure 1 The diagram shows a prior art example of forming grooves in the source and drain regions.

[0024] Figure 2 The diagram shows a schematic representation of the formation of an epitaxial layer using existing technology.

[0025] Figure 3 The diagram shown is a schematic representation of the process flow of the present invention.

[0026] Figure 4 The diagram shows the formation of grooves located in the source and drain regions according to the present invention.

[0027] Figure 5 The diagram shown is a schematic representation of the doping process of this invention.

[0028] Figure 6 The diagram shown illustrates the formation of the epitaxial layer according to the present invention.

[0029] Figure 7 This diagram shows a comparison of the threshold voltage of the channel between the present invention and existing technology devices. Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] Please see Figure 3 This invention provides a method for adjusting the threshold voltage balance of long and short channels based on ion implantation technology, comprising:

[0032] Step 1, please refer to Figure 4A substrate 101 is provided, on which a plurality of gate structures are formed. On both sides of the gate structures, grooves located in the source and drain regions are formed on the substrate 101. The length of some grooves is a first length, which is a short channel, and the length of other grooves is a second length greater than the first length, which is a long channel.

[0033] In embodiments of the present invention, the substrate 101 in step one is a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer located beneath a thin semiconductor layer serving as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that can be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0034] In an embodiment of the present invention, in step one, a groove is formed on the substrate 101 using a dry etching method. That is, the position to be etched on the substrate 101 is defined by a photolithography process, and an anisotropic dry etching method can form a U-shaped groove on the substrate 101.

[0035] In an embodiment of the present invention, the gate structure in step one includes a gate dielectric layer and a polysilicon gate 103 stacked sequentially; a top hard mask layer 104 is covered on the top of the polysilicon gate 103, and a sidewall 102 is formed on the side of the polysilicon gate 103.

[0036] In an embodiment of the present invention, the material of the top hard mask layer 104 in step one includes silicon oxide or silicon nitride; the material of the sidewall 102 includes silicon oxide or silicon nitride.

[0037] In an embodiment of the present invention, PMOS and NMOS are integrated on substrate 101 in step one.

[0038] Step 2, please refer to Figure 5 The substrate 101 at the groove is doped, which reduces the channel voltage at the groove with a length of the first length and makes the trench voltage at the groove with a length of the second length tend to remain unchanged. The implantation of a small number of ions can effectively reduce the threshold voltage of the short channel region, while having little effect on the threshold voltage of the longer channel region, thereby achieving the purpose of adjusting the balance of threshold voltage between long and short channels.

[0039] In embodiments of the present invention, before step two, a photolithography process is performed to open the formation region of the PMOS and cover the formation region of the NMOS, or a photolithography process is performed to open the formation region of the NMOS and cover the formation region of the PMOS.

[0040] In an embodiment of the present invention, in step two, phosphorus ions 106 are used to dope the grooves in the formation region of the NMOS, or boron ions 106 are used to dope the grooves in the formation region of the PMOS.

[0041] In an embodiment of the present invention, the doping concentration in step two is 1.0E14 to 1.0E16 Atom / cm³. 3 .

[0042] Step 3, please refer to Figure 6 An epitaxial layer 105 is formed to fill the groove. The threshold voltage of the short-channel device is adjusted before the epitaxial layer 105 is formed, so that the threshold voltage of the long and short-channel devices are balanced.

[0043] In an embodiment of the present invention, the epitaxial layer 105 in step three is a germanium-silicon epitaxial layer 105 or a phosphorus-silicon epitaxial layer 105.

[0044] In an embodiment of the present invention, please refer to Figure 7 The relationship between channel length and threshold voltage of the device in the prior art is shown in curve 201. The relationship between channel length and threshold voltage of the device obtained by the process of the present invention is shown in curve 202. The threshold voltage decreases at the short channel and approaches no change at the long channel. The threshold voltage of all channels tends to the same value, that is, the threshold voltage tends to be balanced.

[0045] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] In summary, by adjusting the threshold voltage of short-channel devices before the epitaxial layer is formed, the threshold voltages of long and short-channel devices are balanced. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0047] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for adjusting the threshold voltage balance of long and short channels based on ion implantation technology, characterized in that, At least including: Step 1: Provide a substrate on which a plurality of gate structures are formed. On both sides of the gate structures, grooves located in the source and drain regions are formed on the substrate. A portion of the grooves correspond to a channel length of a first length, and the device corresponding to the grooves of the first length is a short-channel device. The other portion of the grooves correspond to a channel length of a second length greater than the first length, and the device corresponding to the grooves of the second length is a long-channel device. Step 2: Doping the substrate at the groove with a doping concentration of 1.0E14 to 1.0E16 Atom / cm3, so that the threshold voltage of the short-channel device corresponding to the groove with the first length is reduced, and the threshold voltage of the long-channel device corresponding to the groove with the second length tends to remain unchanged. Step 3: Form an epitaxial layer that fills the groove. Before forming the epitaxial layer, adjust the threshold voltage of the short-channel device to balance the threshold voltages of the long and short-channel devices.

2. The method for adjusting the threshold voltage balance of long and short channels based on ion implantation process according to claim 1, characterized in that: The substrate mentioned in step one is a bulk semiconductor substrate or a silicon-on-insulator substrate.

3. The method for adjusting the threshold voltage balance of long and short channels based on ion implantation process according to claim 1, characterized in that: In step one, the groove is formed on the substrate using a dry etching method.

4. The method for adjusting the threshold voltage balance of long and short channels based on ion implantation process according to claim 1, characterized in that: The gate structure in step one includes a gate dielectric layer and a polysilicon gate stacked sequentially; a top hard mask layer covers the top of the polysilicon gate, and sidewalls are formed on the sides of the polysilicon gate.

5. The method for adjusting the threshold voltage balance of long and short channels based on ion implantation process according to claim 4, characterized in that: The material of the top hard mask layer in step one includes silicon oxide or silicon nitride; the material of the sidewalls includes silicon oxide or silicon nitride.

6. The method for adjusting the threshold voltage balance of long and short channels based on ion implantation process according to claim 1, characterized in that: The substrate described in step one has PMOS and NMOS integrated on it.

7. The method for adjusting the threshold voltage balance of long and short channels based on ion implantation process according to claim 6, characterized in that: Before step two, the process also includes performing a photolithography process to open the formation region of the PMOS and cover the formation region of the NMOS, or performing a photolithography process to open the formation region of the NMOS and cover the formation region of the PMOS.

8. The method for adjusting the threshold voltage balance of long and short channels based on ion implantation process according to claim 7, characterized in that: In step two, phosphorus ions are used to dope the groove in the formation region of the NMOS, or boron ions are used to dope the groove in the formation region of the PMOS.

9. The method for adjusting the threshold voltage balance of long and short channels based on ion implantation process according to claim 1, characterized in that: The epitaxial layer in step three is a germanium-silicon epitaxial layer or a phosphorus-silicon epitaxial layer.

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