Semiconductor device and method of manufacturing and operating the same

Abstract

The present invention provides a semiconductor device and a manufacturing method and an operating method thereof, wherein the semiconductor device comprises: a substrate formed with a groove; a first isolation layer formed on the bottom wall of the groove; a floating gate layer formed on the first isolation layer in the groove, with a tunneling oxide layer sandwiched between the floating gate layer and the side wall of the groove; a control gate layer formed on the floating gate layer, with an inter-gate dielectric layer sandwiched between the control gate layer and the floating gate layer; a drift region formed in the substrate outside the groove; a source region formed in the drift region outside the groove, with part of the tunneling oxide layer sandwiched between the source region and the floating gate layer; and a drain region formed in the drift region on the side of the source region away from the groove. The technical solution of the present invention makes it unnecessary to connect a gate drive circuit to the control gate to control the opening and closing of the LDMOS device, thereby reducing the complexity of the opening and closing operation of the LDMOS device and the complexity of the circuit design in the DC-DC converter, etc.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method and an operating method thereof. Background Art

[0002] Power devices are widely used in automotive electronics, consumer electronics and other fields, mainly used as DC-DC converters, power management, voltage regulators, etc. In traditional DC-DC converters, laterally diffused metal oxide semiconductors (LDMOS) are mainly used as switching circuits. However, a gate drive circuit needs to be connected to the gate of the LDMOS to control the on and off of the LDMOS. The gate drive circuit is very complex, which increases the complexity of the on and off operation of the LDMOS and the complexity of the circuit design in the DC-DC converter.

[0003] Therefore, how to improve the method of controlling the on and off of LDMOS is a problem that needs to be solved urgently. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a manufacturing method and an operating method thereof, so that there is no need to connect a gate drive circuit to the control gate to control the on and off of the LDMOS device, thereby reducing the complexity of the on and off operation of the LDMOS device and reducing the complexity of the circuit design in a DC-DC converter, etc.

[0005] To achieve the above object, the present invention provides a semiconductor device

[0006] a substrate having a groove formed therein;

[0007] A first isolation layer formed on the bottom wall of the trench;

[0008] A floating gate layer is formed on the first isolation layer in the trench, and a tunneling oxide layer is sandwiched between the floating gate layer and the sidewall of the trench;

[0009] A control gate layer is formed on the floating gate layer, an intergate dielectric layer is sandwiched between the control gate layer and the floating gate layer, and a second isolation layer is sandwiched between the control gate layer and the sidewall of the trench;

[0010] a drift region formed in the substrate at the periphery of the trench;

[0011] A source region formed in the drift region outside the trench, with a portion of the tunnel oxide layer sandwiched between the source region and the floating gate layer;

[0012] A drain region is formed in the drift region on a side of the source region away from the trench.

[0013] Optionally, the semiconductor device further includes:

[0014] A well region is formed in the drift region at the periphery of the trench, and the well region surrounds the source region.

[0015] Optionally, the thickness of the tunnel oxide layer is smaller than the thickness of the second isolation layer.

[0016] Optionally, a surface of the floating gate layer opposite to the control gate layer has a sharp angle.

[0017] Optionally, the semiconductor device is a symmetrical structure, and the drift region, the source region and the drain region surround the trench.

[0018] Optionally, the longitudinal cross-sectional shapes of the floating gate layer and the control gate layer are square and T-shaped respectively, and a floating gate layer is formed on both sides of the “|” part of the control gate layer; or, the longitudinal cross-sectional shapes of the floating gate layer and the control gate layer are matching convex and concave respectively; or, the longitudinal cross-sectional shapes of the floating gate layer and the control gate layer are both square.

[0019] Optionally, the semiconductor device has an asymmetric structure, and the drift region, the source region and the drain region are located at least on one side of the trench.

[0020] Optionally, the longitudinal cross-sectional shapes of the floating gate layer and the control gate layer are square and L-shaped respectively, and the inner side of the L-shaped control gate layer faces the floating gate layer; or, the longitudinal cross-sectional shapes of the floating gate layer and the control gate layer are both L-shaped, and the inner side of the L-shaped floating gate layer faces the inner side of the L-shaped control gate layer; or, the longitudinal cross-sectional shapes of the floating gate layer and the control gate layer are both square.

[0021] The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0022] providing a substrate having a groove formed therein;

[0023] forming a first isolation layer on the bottom wall of the trench;

[0024] forming a tunneling oxide layer and a floating gate layer, wherein the floating gate layer is formed on the first isolation layer in the trench, and the tunneling oxide layer is sandwiched between the floating gate layer and the trench sidewall;

[0025] forming an inter-gate dielectric layer, a second isolation layer and a control gate layer, wherein the control gate layer is formed on the floating gate layer, the inter-gate dielectric layer is sandwiched between the control gate layer and the floating gate layer, and the second isolation layer is sandwiched between the control gate layer and the sidewall of the trench;

[0026] forming a drift region in the substrate at the periphery of the trench;

[0027] A source region and a drain region are formed in the drift region outside the trench, a portion of the tunnel oxide layer is sandwiched between the source region and the floating gate layer, and the drain region is formed in the drift region on a side of the source region away from the trench.

[0028] Optionally, after forming the drift region in the substrate at the periphery of the trench and before forming the source region and the drain region in the drift region at the periphery of the trench, the method for manufacturing the semiconductor device further includes:

[0029] A well region is formed in the drift region at the periphery of the trench, wherein the well region surrounds the source region.

[0030] Optionally, the thickness of the tunnel oxide layer is smaller than the thickness of the second isolation layer.

[0031] Optionally, a surface of the floating gate layer opposite to the control gate layer has a sharp angle.

[0032] The present invention also provides an operating method of a semiconductor device, comprising: performing a programming operation, an erasing operation and a reading operation on the semiconductor device.

[0033] Optionally, when the doping types of the drift region, the source region and the drain region are P-type, the steps of performing a programming operation, an erasing operation and a reading operation on the semiconductor device include:

[0034] Applying a first positive voltage to the control gate layer and a first negative voltage to the source region, with the drain region floating, to perform a programming operation on the semiconductor device;

[0035] Applying a second positive voltage to the control gate layer, and grounding the source region and the drain region, to perform an erase operation on the semiconductor device; or irradiating the semiconductor device with ultraviolet rays to perform an erase operation on the semiconductor device;

[0036] A second negative voltage is applied to the drain region, the source region is grounded, and the control gate layer is floated or grounded, so as to perform a read operation on the semiconductor device.

[0037] Optionally, when the doping types of the drift region, the source region and the drain region are N-type, the steps of performing a programming operation, an erasing operation and a reading operation on the semiconductor device include:

[0038] Applying a third negative voltage to the control gate layer and a third positive voltage to the source region, with the drain region being left floating, so as to perform a programming operation on the semiconductor device;

[0039] A fourth negative voltage is applied to the control gate layer, and the source region and the drain region are grounded, so as to perform an erase operation on the semiconductor device; or ultraviolet rays are used to irradiate the semiconductor device, so as to perform an erase operation on the semiconductor device;

[0040] A fourth positive voltage is applied to the drain region, and the source region is grounded, and the control gate layer is floating or grounded, so as to perform a read operation on the semiconductor device.

[0041] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0042] 1. The semiconductor device of the present invention integrates a memory device with an LDMOS device because a floating gate layer and a control gate layer are formed in a trench of a substrate, and a drift region, a source region, and a drain region are formed in the substrate outside the trench, so that the semiconductor device itself has the function of storing charges, so that the on and off control of the LDMOS device can be achieved by controlling the number of electrons (when the LDMOS device is a PLDMOS device) or holes (when the LDMOS device is an NLDMOS device) in the floating gate layer of the semiconductor device, without connecting a gate drive circuit to the control gate to control the on and off of the LDMOS device, thereby reducing the complexity of the on and off operation of the LDMOS device, and reducing the complexity of the circuit design in a DC-DC converter, etc.

[0043] 2. The manufacturing method of the semiconductor device of the present invention integrates the memory device with the LDMOS device by forming a floating gate layer and a control gate layer in a groove of the substrate, and forming a drift region, a source region and a drain region in the substrate outside the groove, so that the semiconductor device itself has the function of storing charge, so that the LDMOS device can be turned on and off by controlling the number of electrons (when the LDMOS device is a PLDMOS device) or holes (when the LDMOS device is an NLDMOS device) in the floating gate layer of the semiconductor device, without connecting a gate drive circuit to the control gate to control the turning on and off of the LDMOS device, thereby reducing the complexity of the turning on and off operation of the LDMOS device, and reducing the complexity of the circuit design in the DC-DC converter, etc.

[0044] 3. The operating method of the semiconductor device of the present invention implements programming operation, erasing operation and reading operation of the semiconductor device by applying external pressure, so that the number of electrons (when the LDMOS device is a PLDMOS device) or holes (when the LDMOS device is an NLDMOS device) in the floating gate layer can be adjusted by adjusting the magnitude of the applied voltage, thereby making the inversion degree of the channel adjustable, so that the threshold voltage of the LDMOS device can be continuously adjusted, the threshold voltage of the LDMOS device has better controllability, and the perfect integration of the storage device and the LDMOS device is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a layout of a semiconductor device according to an embodiment of the present invention;

[0046] Figure 2a to Figure 2c yes Figure 1 A schematic cross-sectional view of the semiconductor device shown along the AA' direction;

[0047] Figure 3 is a layout of a semiconductor device according to an embodiment of the present invention;

[0048] Figure 4a to Figure 4c yes Figure 3 A schematic cross-sectional view of the semiconductor device shown along the BB' direction;

[0049] Figure 5 The flowchart of the method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0050] Among them, Figure 1 to Figure 5 The reference numerals are described as follows:

[0051] 11-substrate; 111-trench isolation structure; 12-trench; 121-first isolation layer; 122-oxide layer; 123-floating gate layer; 124-insulating material layer; 125-control gate layer; 126-sidewall; 13-drift region; 14-well region; 15-source region; 16-drain region; 17-metal silicide layer; 18-interlayer dielectric layer; 181-conductive plug; 182-metal layer. DETAILED DESCRIPTION

[0052] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and its manufacturing method and operating method proposed by the present invention are further described in detail below in conjunction with the accompanying drawings. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0053] An embodiment of the present invention provides a semiconductor device, comprising: a substrate, in which a trench is formed; a first isolation layer, formed on the bottom wall of the trench; a floating gate layer, formed on the first isolation layer in the trench, with a tunneling oxide layer sandwiched between the floating gate layer and the side wall of the trench; a control gate layer, formed on the floating gate layer, with an intergate dielectric layer sandwiched between the control gate layer and the floating gate layer, and a second isolation layer sandwiched between the control gate layer and the side wall of the trench; a drift region, formed in the substrate outside the trench; a source region, formed in the drift region outside the trench, with a portion of the tunneling oxide layer sandwiched between the source region and the floating gate layer; and a drain region, formed in the drift region on a side of the source region away from the trench.

[0054] See below Figure 1 to Figure 4c The semiconductor device provided by this embodiment is introduced in more detail.

[0055] The substrate 11 has a groove 12 formed therein.

[0056] The substrate 11 may be made of any suitable material known to those skilled in the art.

[0057] The substrate 11 may be a bulk substrate or a SOI (Semiconductor On Insulator) substrate. The bulk substrate may be, for example, a commonly used substrate in the semiconductor field such as silicon, germanium, GaN, etc. The SOI substrate may be, for example, a silicon on insulator or a germanium on insulator substrate. The SOI substrate includes a lower substrate, an insulating buried layer, and an upper semiconductor layer.

[0058] The first isolation layer 121 is formed on the bottom wall of the trench 12 .

[0059] The substrate 11 may also be provided with an annular trench for forming a trench isolation structure 111. The trench isolation structure 111 is used for isolation. The annular trench surrounds the trench 12. When the semiconductor device is a symmetrical structure, Figure 1 As shown, the trench 12 is located at the center of the area surrounded by the annular trench (i.e., the location of the trench isolation structure 111), and the trench 12 is not connected to the annular trench; when the semiconductor device is an asymmetric structure, such as Figure 3 As shown, one side of the groove 12 is connected to the annular groove. The symmetrical structure refers to the center line of the groove 12 parallel to the top surface of the substrate 11 (i.e. Figure 1 The symmetry plane formed by CC' shown in FIG. 1 extending along a direction perpendicular to the top surface of the substrate 11 presents a symmetrical structure.

[0060] Preferably, the groove 12 and the annular groove have the same depth.

[0061] When the substrate 11 is an SOI substrate, the trench 12 and the annular trench preferably penetrate the upper semiconductor layer to expose the buried insulating layer, so that the first isolation layer 121 contacts the buried insulating layer, and the trench isolation structure 111 contacts the buried insulating layer.

[0062] like Figure 1 and Figure 3 As shown, the cross-section of the groove 12 (ie, in a direction parallel to the top surface of the substrate 11 ) may be in the shape of a rectangle.

[0063] The floating gate layer 123 is formed on the first isolation layer 121 in the trench 12 , and a tunneling oxide layer is sandwiched between the floating gate layer 123 and the sidewall of the trench 12 .

[0064] The floating gate layer 123 may cover part or all of the first isolation layer 121 , and a top surface of the floating gate layer 123 is lower than a top surface of the substrate 11 .

[0065] exist Figure 2a to Figure 2c and Figure 4a to Figure 4c In the embodiment shown, an oxide layer 122 is formed on the sidewall of the trench 12, and the oxide layer 122 between the floating gate layer 123 and the sidewall of the trench 12 serves as the tunneling oxide layer. It should be noted that when the semiconductor device is an asymmetric structure, the oxide layer 122 is not formed on the sidewall of the trench 12 that is connected to the annular trench.

[0066] Furthermore, the oxide layer 122 other than between the floating gate layer 123 and the sidewall of the trench 12 may be retained or removed by etching.

[0067] The control gate layer 125 is formed on the floating gate layer 123 , and an inter-gate dielectric layer is sandwiched between the control gate layer 125 and the floating gate layer 123 , and a second isolation layer is sandwiched between the control gate layer 125 and the sidewall of the trench 12 .

[0068] Among them, Figure 2a to Figure 2c and Figure 4a to Figure 4cIn the embodiment shown, an insulating material layer 124 is formed on the surface of the floating gate layer 123 and the sidewalls of the trench 12. If the floating gate layer 123 only covers a portion of the first isolation layer 121, the insulating material layer 124 can also be formed on the uncovered first isolation layer 121, and the insulating material layer 124 between the control gate layer 125 and the floating gate layer 123 serves as the inter-gate dielectric layer; wherein, if the oxide layer 122 other than between the floating gate layer 123 and the sidewalls of the trench 12 is retained, the insulating material layer 124 and the oxide layer 122 between the control gate layer 125 and the sidewalls of the trench 12 together constitute the second isolation layer; if the oxide layer 122 other than between the floating gate layer 123 and the sidewalls of the trench 12 is etched and removed, the insulating material layer 124 between the control gate layer 125 and the sidewalls of the trench 12 serves as the second isolation layer. It should be noted that the second isolation layer is not limited to the above composition.

[0069] Preferably, the surface of the floating gate layer 123 opposite to the control gate layer 125 has a sharp angle, in which case the semiconductor device may have a symmetrical structure or an asymmetrical structure. Figure 2a to Figure 2b as well as Figure 4a to Figure 4b In the embodiment shown, the sharp corners are all L-shaped corners (i.e., the sharp corners are right angles), the control gate layer 125 has at least one L-shaped inner corner, the floating gate layer 123 has at least one L-shaped outer corner, and the inner corner of the control gate layer 125 is arranged opposite to the outer corner of the floating gate layer 123. It can be understood by those skilled in the art that the sharp corners are not limited to Figure 2a to Figure 2b as well as Figure 4a to Figure 4b The L-shaped corner shown may also be of other designs, such as a bird's beak shape or other non-right angle shapes.

[0070] Among them, in some embodiments, when the semiconductor device is a symmetrical structure, such as Figure 2aAs shown, the longitudinal cross-sections (i.e., the cross-sections in the direction perpendicular to the top surface of the substrate 11) of the floating gate layer 123 and the control gate layer 125 are square and T-shaped, respectively. The center line of the T-shaped control gate layer 125 in the direction perpendicular to the top surface of the substrate 11 is the symmetry axis of the symmetrical structure. A floating gate layer 123 is symmetrically formed on both sides of the "|" part of the T-shaped control gate layer 125. The floating gate layer 123 only covers a portion of the first isolation layer 121. The insulating material layer 123 may also be formed between the "|" part of the T-shaped control gate layer 125 and the first isolation layer 121. 4. The T-shaped control gate layer 125 has two L-shaped inner corners, and the two floating gate layers 123 each have an L-shaped outer corner, and the two inner corners of the control gate layer 125 are respectively arranged opposite to the outer corners of the two floating gate layers 123; or, the longitudinal cross-sectional shapes of the floating gate layer 123 and the control gate layer 125 are respectively matched convex and concave, wherein the floating gate layer 123 is convex and the control gate layer 125 is concave, or the floating gate layer 123 is concave and the control gate layer 125 is convex. Taking the floating gate layer 123 as a convex shape and the control gate layer 125 as a concave shape as an example, as Figure 2b As shown, the protruding portion of the convex floating gate layer 123 extends into the recessed portion of the concave control gate layer 125, and the line connecting the center lines of the floating gate layer 123 and the control gate layer 125 in a direction perpendicular to the top surface of the substrate 11 is the symmetry axis of the symmetrical structure. The floating gate layer 123 covers the entire first isolation layer 121, the recessed portion of the control gate layer 125 has two L-shaped inner corners, and the protruding portion of the floating gate layer 123 has two L-shaped outer corners.

[0071] Alternatively, in some other embodiments, when the semiconductor device is an asymmetric structure, such as Figure 4a As shown, the longitudinal cross-section shapes of the floating gate layer 123 and the control gate layer 125 are square and L-shaped respectively, the floating gate layer 123 only covers a portion of the first isolation layer 121, and the insulating material layer 124 may be further formed between the bottom of the control gate layer 125 and the first isolation layer 121, and the inner side of the L-shaped control gate layer 125 faces the floating gate layer 123, so that the inner corner of the control gate layer 125 is arranged opposite to the outer corner of the floating gate layer 123; or as Figure 4b As shown, the longitudinal cross-section shapes of the floating gate layer 123 and the control gate layer 125 are both L-shaped, the floating gate layer 123 only covers a portion of the first isolation layer 121, and the inner side of the L-shaped floating gate layer 123 faces the inner side of the L-shaped control gate layer 125.

[0072] It should be noted that the shapes of the floating gate layer 123 and the control gate layer 125 are not limited to Figure 2a to Figure 2b and Figure 4a to Figure 4b In the embodiment shown, in other embodiments, the longitudinal cross-sectional shape of the floating gate layer 123 can be a comb shape with at least two comb teeth, and the longitudinal cross-sectional shape of the control gate layer 125 can be a comb shape with at least three comb teeth, and the comb teeth of the floating gate layer 123 are inserted into the gap between two adjacent comb teeth of the control gate layer 125. At this time, the recessed portion of the control gate layer 125 has at least four L-shaped inner corners, and the protruding portion of the floating gate layer 123 has at least four L-shaped outer corners; or, the sharp angle of the surface of the floating gate layer 123 opposite to the control gate layer 125 is an acute angle or an obtuse angle.

[0073] In addition, in other embodiments, the surface of the floating gate layer 123 facing the control gate layer 125 may not have sharp corners. In this case, the semiconductor device may also be a symmetrical structure or an asymmetrical structure. Figure 2c As shown, the longitudinal cross-section shapes of the floating gate layer 123 and the control gate layer 125 are both square, the floating gate layer 123 covers the entire first isolation layer 121, and the line connecting the center lines of the floating gate layer 123 and the control gate layer 125 in a direction perpendicular to the top surface of the substrate 11 is the symmetry axis of the symmetrical structure; or, when the semiconductor device is an asymmetric structure, as Figure 4c As shown, the longitudinal cross-sections of the floating gate layer 123 and the control gate layer 125 are both square, and the floating gate layer 123 only covers a portion of the first isolation layer 121 .

[0074] Furthermore, when the semiconductor device is a symmetrical structure, Figure 2a to Figure 2c As shown, the tunnel oxide layer is formed between the floating gate layer 123 and each side wall of the trench 12, and the second isolation layer is formed between the control gate layer 125 and each side wall of the trench 12; when the semiconductor device is an asymmetric structure, since one side of the trench 12 is connected to the annular trench, the floating gate layer 123 only covers a portion of the first isolation layer 121, as shown in FIG. Figure 4a to Figure 4c As shown, the tunneling oxide layer is sandwiched between only the side wall of the groove 12 that is not connected to the annular groove and the floating gate layer 123, and the second isolation layer can be sandwiched between the side wall of the groove 12 that is connected to the annular groove and the floating gate layer 123 and the control gate layer 125.

[0075] The insulating material layer 124 may be made of at least one insulating material such as silicon oxide, silicon oxynitride or silicon nitride. For example, the insulating material layer 124 is a stacked structure of silicon oxide / silicon nitride / silicon oxide.

[0076] The top surface of the control gate layer 125 is flush with the top surface of the substrate 11, or the top surface of the control gate layer 125 is lower than the top surface of the substrate 11, in which case, no sidewalls need to be formed on the sidewalls of the control gate layer 125; or the top surface of the control gate layer 125 is higher than the top surface of the substrate 11, in which case, Figure 2a to 2c as well as Figure 4a to Figure 4c As shown, a sidewall 126 is formed on the sidewall of the control gate layer 125 that is higher than the top surface of the substrate 11 .

[0077] Preferably, the thickness of the tunnel oxide layer is smaller than the thickness of the second isolation layer, and the thickness of the tunnel oxide layer is smaller than the thickness of the inter-gate dielectric layer.

[0078] Preferably, the thickness of the tunnel oxide layer is The thickness of the second isolation layer is not less than The thickness of the inter-gate dielectric layer is

[0079] The drift region 13 is formed in the substrate 11 outside the trench 12 , and the drift region 13 is formed in the substrate 11 surrounded by the trench isolation structure 111 .

[0080] The source region 15 is formed in the drift region 13 at the periphery of the trench 12 , and the drain region 16 is formed in the drift region 13 at a side of the source region 15 away from the trench 12 .

[0081] The semiconductor device further comprises:

[0082] A well region 14 is formed in the drift region 13 outside the trench 12, and the well region 14 surrounds the source region 15. The well region 14 below the source region 15 is a longitudinal channel of the semiconductor device.

[0083] The source region 15 is formed in the well region 14 , the source region 15 contacts a portion of the sidewall of the trench 12 , the drain region 16 may contact the trench filling structure 111 , and the drain region 16 does not contact the well region 14 .

[0084] Furthermore, the source region 15 extends from the top surface of the substrate 11 to the inside of the substrate 11 , so that the second isolation layer is sandwiched between the source region 15 and the control gate layer 125 , and a portion of the tunneling oxide layer is sandwiched between the source region 15 and the floating gate layer 123 .

[0085] Preferably, the ion doping concentration of the drift region 13 may be 5E12cm -3 ~1E13cm -3The ion doping concentration of the well region 14 may be 1E13 cm -3 -3E13cm -3 The ion doping concentration of the source region 15 and the drain region 16 may be 1e19 cm -3 ~1E21cm -3 .

[0086] When the semiconductor device is a symmetrical structure, Figure 1 and Figure 2a to Figure 2c As shown, the drift region 13 , the well region 14 , the source region 15 and the drain region 16 surround the trench 12 .

[0087] When the semiconductor device has an asymmetric structure, such as Figure 3 and Figure 4a to Figure 4c As shown, the drift region 13, the well region 14, the source region 15 and the drain region 16 are formed in at least the substrate 11 on the side of the groove 12 close to the floating gate layer 123, and the second isolation layer may also be sandwiched between the floating gate layer 123 and the side wall of the groove 12 on the side where the drift region 13, the well region 14, the source region 15 and the drain region 16 are not formed.

[0088] The semiconductor device further comprises:

[0089] A metal silicide layer 17, formed on the source region 15, the drain region 16 and the control gate layer 125, wherein the metal in the metal silicide layer 17 may include one or a combination of two or more of tungsten, iron, nickel, cobalt, platinum and titanium;

[0090] An interlayer dielectric layer 18 is formed on the substrate 11, and the interlayer dielectric layer 18 buries the metal silicide layer 17, the well region 14, the drift region 13, etc.;

[0091] A conductive plug 181 is formed on the source region 15, the drain region 16 and the metal silicide layer 17 on the control gate layer 125, and the conductive plug 181 penetrates the interlayer dielectric layer 18;

[0092] A metal interconnect structure including a metal layer 182 is formed on the interlayer dielectric layer 18 , and the metal layer 182 is electrically connected to the conductive plug 181 .

[0093] The drift region 13, the source region 15 and the drain region 16 are of a first doping type, and the well region 14 is of a second doping type; the first doping type is P type, and the second doping type is N type, or the first doping type is N type, and the second doping type is P type. The doping type of the substrate 11 is P type.

[0094] In the semiconductor device of the present invention, since the floating gate layer 123 and the control gate layer 125 are formed in the trench 12 of the substrate 11, and the drift region 13, the source region 15 and the drain region 16 are formed in the substrate 11 outside the trench 12, the memory device (Flash or EEPROM) and the LDMOS device are integrated together, and the semiconductor device has the functions of the memory device and the LDMOS device at the same time, so that the semiconductor device itself has the function of storing charges, and by applying a bias voltage to the source region 15 and the control gate layer 125, electrons (when the LDMOS device is a PLDMOS device) or holes (when the LDMOS device is an NLDMOS device) are transferred from the source region 15 through the source region 15 and the floating gate layer 123. The tunnel oxide layer sandwiched therebetween passes through and enters the floating gate layer 123 to implement a programming operation, and a high voltage is applied to the control gate layer 125 so that electrons (when the LDMOS device is a PLDMOS device) or holes (when the LDMOS device is an NLDMOS device) move from the floating gate layer 123 to the control gate layer 125 to implement an erase operation, thereby enabling the LDMOS device to be turned on and off to be controlled by controlling the number of electrons or holes in the floating gate layer 123 in the semiconductor device, without the need to connect a gate drive circuit to the control gate 125 to control the LDMOS device to be turned on and off, thereby reducing the complexity of the LDMOS device's on and off operations, and reducing the complexity of the circuit design in a DC-DC converter, etc.

[0095] Among them, when the first doping type is P type and the second doping type is N type, the LDMOS device is a PLDMOS device, so that the semiconductor device integrates a memory device and a PLDMOS device; when the first doping type is N type and the second doping type is P type, the LDMOS device is an NLDMOS device, so that the semiconductor device integrates a memory device and a NLDMOS device.

[0096] Furthermore, since the thickness of the tunnel oxide layer is less than that of the second isolation layer, when performing a programming operation, electrons or holes can pass through the tunnel oxide layer sandwiched between the source region 15 and the floating gate layer 123 and then enter the floating gate layer 123 (i.e. Figure 2a to Figure 2c and Figure 4a to Figure 4c The source region 15 in the control gate layer 125 points to the arrow in the floating gate layer 123), and will not pass through the second isolation layer sandwiched between the source region 15 and the control gate layer 125, thereby preventing electrons or holes from leaking from the second isolation layer sandwiched between the source region 15 and the control gate layer 125.

[0097] Furthermore, when the surface of the floating gate layer 123 facing the control gate layer 125 does not have a sharp corner, the electrons or holes in the floating gate layer 123 pass through the inter-gate dielectric layer and enter the control gate layer 125 to implement the erase operation; when the surface of the floating gate layer 123 facing the control gate layer 125 has a sharp corner, the electric field is easily concentrated due to the unevenness at the sharp corner, so that an electric field enhancement effect is generated at the sharp corner, thereby making it easier for electrons or holes to move from the sharp corner of the floating gate layer 123 through the inter-gate dielectric layer to the sharp corner of the control gate layer 125 (i.e. Figure 2a to Figure 2b and Figure 4a to Figure 4b The floating gate layer 123 in the embodiment points to the arrow in the control gate layer 125), thereby making it easier to perform an erase operation of the semiconductor device.

[0098] Furthermore, in the present invention, the floating gate layer 123 and the control gate layer 125 are formed in the groove 12 in the substrate 11, so that the device area occupied by the gate is reduced compared to being formed on the top surface of the substrate 11; especially when the semiconductor device is a symmetrical structure, it is equivalent to two LDMOS devices sharing one storage device (i.e., sharing the floating gate layer 123 and the control gate layer 125 in the same groove 12), so that while realizing the functions of the two devices, the area of ​​one storage device is saved, thereby further reducing the area of ​​the semiconductor device.

[0099] In summary, the semiconductor device provided by the present invention comprises: a substrate, in which a groove is formed; a first isolation layer, formed on the bottom wall of the groove; a floating gate layer, formed on the first isolation layer in the groove, a tunneling oxide layer is sandwiched between the floating gate layer and the side wall of the groove; a control gate layer, formed on the floating gate layer, an inter-gate dielectric layer is sandwiched between the control gate layer and the floating gate layer, and a second isolation layer is sandwiched between the control gate layer and the side wall of the groove; a drift region, formed in the substrate outside the groove; a source region, formed in the drift region outside the groove, a part of the tunneling oxide layer is sandwiched between the source region and the floating gate layer; a drain region, formed in the drift region on the side of the source region away from the groove. The semiconductor device of the present invention makes it unnecessary to connect a gate drive circuit to the control gate to control the opening and closing of the LDMOS device, thereby reducing the complexity of the opening and closing operation of the LDMOS device, and reducing the complexity of the circuit design in the DC-DC converter, etc.

[0100] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 5 , Figure 5 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein the method for manufacturing a semiconductor device comprises:

[0101] Step S1, providing a substrate, wherein a groove is formed in the substrate;

[0102] Step S2, forming a first isolation layer on the bottom wall of the trench;

[0103] Step S3, forming a tunneling oxide layer and a floating gate layer, wherein the floating gate layer is formed on the first isolation layer in the trench, and the tunneling oxide layer is sandwiched between the floating gate layer and the trench sidewall;

[0104] Step S4, forming an inter-gate dielectric layer, a second isolation layer and a control gate layer, wherein the control gate layer is formed on the floating gate layer, and the inter-gate dielectric layer is sandwiched between the control gate layer and the floating gate layer, and the second isolation layer is sandwiched between the control gate layer and the sidewall of the trench;

[0105] Step S5, forming a drift region in the substrate outside the trench;

[0106] Step S6, forming a source region and a drain region in the drift region outside the trench, with a portion of the tunneling oxide layer sandwiched between the source region and the floating gate layer, and the drain region being formed in the drift region on a side of the source region away from the trench.

[0107] See below Figure 1 to Figure 4c The manufacturing method of the semiconductor device provided in this embodiment is introduced in more detail.

[0108] According to step S1 , a substrate 11 is provided, wherein a groove 12 is formed in the substrate 11 .

[0109] The substrate 11 may be made of any suitable material known to those skilled in the art.

[0110] The substrate 11 may be a bulk substrate or a SOI (Semiconductor On Insulator) substrate. The bulk substrate may be, for example, a commonly used substrate in the semiconductor field such as silicon, germanium, GaN, etc. The SOI substrate may be, for example, a silicon on insulator or a germanium on insulator substrate. The SOI substrate includes a lower substrate, an insulating buried layer, and an upper semiconductor layer.

[0111] The substrate 11 may also be provided with an annular trench for forming a trench isolation structure 111. The trench isolation structure 111 is used for isolation. The annular trench surrounds the trench 12. When the semiconductor device is a symmetrical structure, Figure 1 As shown, the trench 12 is located at the center of the area surrounded by the annular trench (i.e., the location of the trench isolation structure 111), and the trench 12 is not connected to the annular trench; when the semiconductor device is an asymmetric structure, such as Figure 3As shown, one side of the groove 12 is connected to the annular groove. The symmetrical structure refers to the center line of the groove 12 parallel to the top surface of the substrate 11 (i.e. Figure 1 The symmetry plane formed by CC' shown in FIG. 1 extending along a direction perpendicular to the top surface of the substrate 11 presents a symmetrical structure.

[0112] The groove 12 and the annular groove are formed by etching the substrate 11. Preferably, the groove 12 and the annular groove are formed simultaneously, and the groove 12 and the annular groove have the same depth.

[0113] When the substrate 11 is an SOI substrate, it is preferred that the groove 12 and the annular groove penetrate through the upper semiconductor layer to expose the buried insulating layer.

[0114] like Figure 1 and Figure 3 As shown, the cross-section of the groove 12 (ie, in a direction parallel to the top surface of the substrate 11 ) may be in the shape of a rectangle.

[0115] According to step S2 , a first isolation layer 121 is formed on the bottom wall of the trench 12 .

[0116] The steps may include: first, depositing insulating material in the groove 12, and preferably depositing insulating material in the annular groove at the same time, the insulating material filling the groove 12 and the annular groove to form a trench isolation structure 111 in the annular groove; then, etching away part of the insulating material in the groove 12, and retaining the insulating material on the bottom wall of the groove 12 as the first isolation layer 121.

[0117] According to step S3 , a tunneling oxide layer and a floating gate layer 123 are formed. The floating gate layer 123 is formed on the first isolation layer 121 in the trench 12 , and the tunneling oxide layer is sandwiched between the floating gate layer 123 and the sidewall of the trench 12 .

[0118] The floating gate layer 123 may cover part or all of the first isolation layer 121 , and a top surface of the floating gate layer 123 is lower than a top surface of the substrate 11 .

[0119] The steps of forming the tunneling oxide layer and the floating gate layer 123 may include: first, forming an oxide layer 122 on the sidewalls of the trench 12, and preferably using a thermal oxidation process to form the oxide layer 122; then, depositing polysilicon to fill the trench 12, and etching away part of the polysilicon to form the floating gate layer 123, wherein the oxide layer 122 between the floating gate layer 123 and the sidewalls of the trench 12 serves as the tunneling oxide layer. Wherein, a suitable etching process may be selected according to the shape of the floating gate layer 123 to be formed, for example Figure 2a to Figure 2b , Figure 4a and Figure 4c The floating gate layer 123 in the embodiment shown can be formed by etching polysilicon twice. Figure 2c The floating gate layer 123 in the embodiment shown can be formed by etching polysilicon once. Figure 4b The floating gate layer 123 in the illustrated embodiment may be formed by etching polysilicon three times.

[0120] It should be noted that, since the trench isolation structure 111 is formed in the annular trench, when the semiconductor device is an asymmetric structure, the oxide layer 122 is not formed on the sidewall of the trench 12 communicating with the annular trench.

[0121] Furthermore, the oxide layer 122 outside the floating gate layer 123 and the sidewall of the trench 12 can be retained or removed by etching. To save process cost, the oxide layer 122 outside the floating gate layer 123 and the sidewall of the trench 12 shown in the drawings is retained.

[0122] According to step S4, an inter-gate dielectric layer, a second isolation layer and a control gate layer 125 are formed. The control gate layer 125 is formed on the floating gate layer 123, and the inter-gate dielectric layer is sandwiched between the control gate layer 125 and the floating gate layer 123, and the second isolation layer is sandwiched between the control gate layer 125 and the side wall of the trench 12.

[0123] Preferably, the steps of forming the inter-gate dielectric layer, the second isolation layer and the control gate layer 125 include: first, forming an insulating material layer 124 on the surface of the floating gate layer 123 and on the sidewalls of the trench 12; if the floating gate layer 123 only covers a portion of the first isolation layer 121, the insulating material layer 124 may also be formed on the uncovered first isolation layer 121, and the insulating material layer 124 does not fill the trench 12; then, depositing the control gate layer 125 to fill the trench 12, and the control gate layer 125 and the sidewalls of the trench 12 are separated. The insulating material layer 124 between the floating gate layer 123 serves as the inter-gate dielectric layer; wherein, if the oxide layer 122 other than between the floating gate layer 123 and the sidewall of the trench 12 is retained, the insulating material layer 124 and the oxide layer 122 between the control gate layer 125 and the sidewall of the trench 12 together constitute the second isolation layer; if the oxide layer 122 other than between the floating gate layer 123 and the sidewall of the trench 12 is etched away, the insulating material layer 124 between the control gate layer 125 and the sidewall of the trench 12 serves as the second isolation layer. The above method for forming the inter-gate dielectric layer and the second isolation layer can simplify the process; it should be noted that the method for forming the second isolation layer is not limited to the above case. In other embodiments, the gate dielectric layer can be first deposited on the surface of the floating gate layer 123, and then the second isolation layer can be deposited between the control gate layer 125 and the sidewall of the trench 12.

[0124] Preferably, the surface of the floating gate layer 123 opposite to the control gate layer 125 has a sharp angle, in which case the semiconductor device may have a symmetrical structure or an asymmetrical structure. Figure 2a to Figure 2b as well as Figure 4a to Figure 4b In the embodiment shown, the sharp corners are all L-shaped corners (i.e., the sharp corners are right angles), the control gate layer 125 has at least one L-shaped inner corner, the floating gate layer 123 has at least one L-shaped outer corner, and the inner corner of the control gate layer 125 is arranged opposite to the outer corner of the floating gate layer 123. For specific examples, please refer to the above description of the semiconductor device of the present invention, which will not be repeated here.

[0125] In addition, in other embodiments, the surface of the floating gate layer 123 facing the control gate layer 125 may not have sharp corners, and in this case, the semiconductor device may also be a symmetrical structure or an asymmetrical structure. For specific examples, please refer to the above description of the semiconductor device of the present invention, which will not be repeated here.

[0126] Furthermore, when the semiconductor device is a symmetrical structure, Figure 2a to Figure 2cAs shown, the tunnel oxide layer is formed between the floating gate layer 123 and each side wall of the trench 12, and the second isolation layer is formed between the control gate layer 125 and each side wall of the trench 12; when the semiconductor device is an asymmetric structure, since one side of the trench 12 is connected to the annular trench, the floating gate layer 123 only covers a portion of the first isolation layer 121, as shown in FIG. Figure 4a to Figure 4c As shown, the tunneling oxide layer is sandwiched between only the side wall of the groove 12 that is not connected to the annular groove and the floating gate layer 123, and the second isolation layer can be sandwiched between the side wall of the groove 12 that is connected to the annular groove and the floating gate layer 123 and the control gate layer 125.

[0127] The insulating material layer 124 may be made of at least one insulating material such as silicon oxide, silicon oxynitride or silicon nitride. For example, the insulating material layer 124 is a stacked structure of silicon oxide / silicon nitride / silicon oxide.

[0128] The top surface of the control gate layer 125 is flush with the top surface of the substrate 11, or the top surface of the control gate layer 125 is lower than the top surface of the substrate 11, in which case, no sidewalls need to be formed on the sidewalls of the control gate layer 125; or the top surface of the control gate layer 125 is higher than the top surface of the substrate 11, in which case, Figure 2a to 2c as well as Figure 4a to Figure 4c As shown, the method for manufacturing the semiconductor device further includes: forming a sidewall 126 on a portion of the sidewall of the control gate layer 125 that is higher than the top surface of the substrate 11 .

[0129] Preferably, the thickness of the tunnel oxide layer is smaller than the thickness of the second isolation layer, and the thickness of the tunnel oxide layer is smaller than the thickness of the inter-gate dielectric layer.

[0130] Preferably, the thickness of the tunnel oxide layer is The thickness of the second isolation layer is not less than The thickness of the inter-gate dielectric layer is

[0131] According to step S5 , a drift region 13 is formed in the substrate 11 outside the trench 12 . The drift region 13 is formed in the substrate 11 surrounded by the trench isolation structure 111 .

[0132] According to step S6 , a source region 15 and a drain region 16 are formed in the drift region 13 outside the trench 12 , and the drain region 16 is formed in the drift region 13 on a side of the source region 15 away from the trench 12 .

[0133] Furthermore, after forming the drift region 13 in the substrate 11 outside the trench 12 and before forming the source region 15 and the drain region 16 in the drift region 13 outside the trench 12, the method for manufacturing the semiconductor device further includes:

[0134] A well region 14 is formed in the drift region 13 outside the trench 12, and the well region 14 surrounds the source region 15. The well region 14 below the source region 15 is a longitudinal channel of the semiconductor device.

[0135] The source region 15 is formed in the well region 14 , the source region 15 contacts a portion of the sidewall of the trench 12 , the drain region 16 may contact the trench filling structure 111 , and the drain region 16 does not contact the well region 14 .

[0136] Furthermore, the source region 15 extends from the top surface of the substrate 11 to the inside of the substrate 11 , so that the second isolation layer is sandwiched between the source region 15 and the control gate layer 125 , and a portion of the tunneling oxide layer is sandwiched between the source region 15 and the floating gate layer 123 .

[0137] The drift region 13 , the well region 14 , the source region 15 and the drain region 16 may be formed by an ion implantation process.

[0138] Preferably, the ion doping concentration of the drift region 13 may be 5E12cm -3 ~1E13cm -3 The ion doping concentration of the well region 14 may be 1E13 cm -3 -3E13cm -3 The ion doping concentration of the source region 15 and the drain region 16 may be 1e19 cm -3 ~1E21cm -3 .

[0139] When the semiconductor device is a symmetrical structure, Figure 1 and Figure 2a to Figure 2c As shown, the drift region 13 , the well region 14 , the source region 15 and the drain region 16 surround the trench 12 .

[0140] When the semiconductor device has an asymmetric structure, such as Figure 3 and Figure 4a to Figure 4cAs shown, the drift region 13, the well region 14, the source region 15 and the drain region 16 are formed in at least the substrate 11 on the side of the groove 12 close to the floating gate layer 123, and the second isolation layer may also be sandwiched between the floating gate layer 123 and the side wall of the groove 12 on the side where the drift region 13, the well region 14, the source region 15 and the drain region 16 are not formed.

[0141] In addition, the method for manufacturing the semiconductor device further includes:

[0142] Forming a metal silicide layer 17 on the source region 15, the drain region 16 and the control gate layer 125, wherein the metal in the metal silicide layer 17 may include one or a combination of two or more of tungsten, iron, nickel, cobalt, platinum and titanium;

[0143] An interlayer dielectric layer 18 is formed to cover the substrate 11, wherein the interlayer dielectric layer 18 buries the metal silicide layer 17, the well region 14, the drift region 13, etc.;

[0144] Forming a conductive plug 181 on the source region 15 , the drain region 16 and the metal silicide layer 17 on the control gate layer 125 , wherein the conductive plug 181 penetrates the interlayer dielectric layer 18 ;

[0145] A metal interconnect structure including a metal layer 182 is formed on the interlayer dielectric layer 18 , and the metal layer 182 is electrically connected to the conductive plug 181 .

[0146] The drift region 13, the source region 15 and the drain region 16 are of a first doping type, and the well region 14 is of a second doping type; the first doping type is P type, and the second doping type is N type, or the first doping type is N type, and the second doping type is P type. The doping type of the substrate 11 is P type.

[0147] The manufacturing method of the semiconductor device of the present invention forms the floating gate layer 123 and the control gate layer 125 in the groove 12 of the substrate 11, and forms the drift region 13, the source region 15 and the drain region 16 in the substrate 11 outside the groove 12, so that the storage device (Flash or EEPROM) and the LDMOS device are integrated together, and the semiconductor device has the functions of the storage device and the LDMOS device at the same time, so that the semiconductor device itself has the function of storing charges, and by applying a bias voltage to the source region 15 and the control gate layer 125, electrons (when the LDMOS device is a PLDMOS device) or holes (when the LDMOS device is an NLDMOS device) are transferred from the source region 15 through the source region 15 and the floating gate layer 123. The tunnel oxide layer sandwiched between the semiconductor devices 23 passes through and enters the floating gate layer 123 to implement the programming operation, and the erasing operation is implemented by applying high voltage to the control gate layer 125 so that electrons (when the LDMOS device is a PLDMOS device) or holes (when the LDMOS device is an NLDMOS device) move from the floating gate layer 123 to the control gate layer 125, thereby enabling the LDMOS device to be turned on and off to be controlled by controlling the number of electrons or holes in the floating gate layer 123 in the semiconductor device, without the need to connect a gate drive circuit to the control gate 125 to control the LDMOS device to be turned on and off, thereby reducing the complexity of the LDMOS device's on and off operations, and reducing the complexity of the circuit design in the DC-DC converter, etc.

[0148] Among them, when the first doping type is P type and the second doping type is N type, the LDMOS device is a PLDMOS device, so that the semiconductor device integrates a memory device and a PLDMOS device; when the first doping type is N type and the second doping type is P type, the LDMOS device is an NLDMOS device, so that the semiconductor device integrates a memory device and a NLDMOS device.

[0149] Furthermore, since the thickness of the tunnel oxide layer is less than that of the second isolation layer, when performing a programming operation, electrons or holes can pass through the tunnel oxide layer sandwiched between the source region 15 and the floating gate layer 123 and then enter the floating gate layer 123 (i.e. Figure 2a to Figure 2c and Figure 4a to Figure 4c The source region 15 in the control gate layer 125 points to the arrow in the floating gate layer 123), and will not pass through the second isolation layer sandwiched between the source region 15 and the control gate layer 125, thereby preventing electrons or holes from leaking from the second isolation layer sandwiched between the source region 15 and the control gate layer 125.

[0150] Furthermore, when the surface of the floating gate layer 123 facing the control gate layer 125 does not have a sharp corner, the electrons or holes in the floating gate layer 123 pass through the inter-gate dielectric layer and enter the control gate layer 125 to implement the erase operation; when the surface of the floating gate layer 123 facing the control gate layer 125 has a sharp corner, the electric field is easily concentrated due to the unevenness at the sharp corner, so that an electric field enhancement effect is generated at the sharp corner, thereby making it easier for electrons or holes to pass through the inter-gate dielectric layer from the sharp corner of the floating gate layer 123 to move to the sharp corner of the control gate layer 125 (i.e. Figure 2a to Figure 2b and Figure 4a to Figure 4b The floating gate layer 123 in the embodiment points to the arrow in the control gate layer 125), thereby making it easier to perform an erase operation of the semiconductor device.

[0151] Furthermore, in the present invention, the floating gate layer 123 and the control gate layer 125 are formed in the groove 12 in the substrate 11, so that the device area occupied by the gate is reduced compared to being formed on the top surface of the substrate 11; especially when the semiconductor device is a symmetrical structure, it is equivalent to two LDMOS devices sharing one storage device (i.e., sharing the floating gate layer 123 and the control gate layer 125 in the same groove 12), so that while realizing the functions of the two devices, the area of ​​one storage device is saved, thereby further reducing the area of ​​the semiconductor device.

[0152] In summary, the manufacturing method of the semiconductor device provided by the present invention includes: providing a substrate, in which a groove is formed; forming a first isolation layer on the bottom wall of the groove; forming a tunneling oxide layer and a floating gate layer, wherein the floating gate layer is formed on the first isolation layer in the groove, and the tunneling oxide layer is sandwiched between the floating gate layer and the side wall of the groove; forming an inter-gate dielectric layer, a second isolation layer and a control gate layer, wherein the control gate layer is formed on the floating gate layer, and the inter-gate dielectric layer is sandwiched between the control gate layer and the floating gate layer, and the second isolation layer is sandwiched between the control gate layer and the side wall of the groove; forming a drift region in the substrate outside the groove; forming a source region and a drain region in the drift region outside the groove, wherein a portion of the tunneling oxide layer is sandwiched between the source region and the floating gate layer, and the drain region is formed in the drift region on the side of the source region away from the groove. The manufacturing method of the semiconductor device of the present invention makes it unnecessary to connect a gate drive circuit to the control gate to control the on and off of the LDMOS device, thereby reducing the complexity of the on and off operation of the LDMOS device and reducing the complexity of the circuit design in the DC-DC converter and the like.

[0153] An embodiment of the present invention provides an operating method of a semiconductor device, comprising: performing a programming operation, an erasing operation and a reading operation on the semiconductor device.

[0154] The structure of the semiconductor device is as described above and will not be described again here.

[0155] When the doping types of the drift region 13, the source region 15 and the drain region 16 are P-type, and the doping type of the well region 14 is N-type, the LDMOS device is a PLDMOS device, and the steps of performing a programming operation, an erasing operation and a reading operation on the semiconductor device include:

[0156] A first positive voltage is applied to the control gate layer 125 and a first negative voltage is applied to the source region 15, and the drain region 16 is floating (i.e., the drain region 16 is not connected to the circuit), so that electrons are injected from the source region 15 into the floating gate layer 123 to implement a programming operation on the semiconductor device. When the semiconductor device is programmed, electrons accumulate in the floating gate layer 123, and the channel in the well region 14 is inverted, so that the PLDMOS device is turned on, and a large current is generated between the source region 15 and the drain region 16.

[0157] When a first positive voltage is applied to the control gate layer 125, a positive voltage is coupled to the floating gate layer 123. Preferably, a coupling coefficient when the first positive voltage is coupled to the floating gate layer 123 is in a range of 0.6 to 0.8.

[0158] Since the tunneling oxide layer is sandwiched between the source region 15 and the floating gate layer 123, that is, the source region 15 overlaps with a portion of the floating gate layer 123 in a direction parallel to the top surface of the substrate 11, after a bias voltage is applied to the control gate layer 125 and the source region 15, a deep depletion region is formed on the surface of the substrate 11 in the overlapping region of the source region 15 and the floating gate layer 123, and the energy band bending in the deep depletion region is very serious. When the energy band bending exceeds the bandgap width of the material of the substrate 11, band-to-band tunneling electron-hole pairs will be generated, in which the holes are collected by the source region 15, and the electrons are accelerated under the action of the high electric field in the deep depletion region to obtain sufficiently high energy, and are injected into the floating gate layer 123 through the tunneling oxide layer sandwiched between the source region 15 and the floating gate layer 123 with the help of the electric field of the tunneling oxide layer.

[0159] Preferably, the first positive voltage is in the range of 3 V to 5 V, and the first negative voltage is in the range of -8 V to -5.5 V. Preferably, the pulse width when the first negative voltage is applied to the source region 15 is 10 μs.

[0160] A second positive voltage is applied to the control gate layer 125, and the source region 15 and the drain region 16 are grounded, so that electrons pass through the inter-gate dielectric layer from the floating gate layer 123 and enter the control gate layer 125, so as to perform an erase operation on the semiconductor device. When the erase operation is performed on the semiconductor device, electrons in the floating gate layer 123 are missing, the channel in the well region 14 is in an accumulation state, the channel is closed, so that the PLDMOS device is turned off, and the current between the source region 15 and the drain region 16 is very small.

[0161] When the surfaces of the floating gate layer 123 and the control gate layer 125 opposite to each other have sharp corners, electric field concentration is likely to occur due to the unevenness at the sharp corners, so that an electric field enhancement effect is generated at the sharp corners of the floating gate layer 123 and the control gate layer 125, thereby making it easier for electrons to move from the sharp corners of the floating gate layer 123 through the inter-gate dielectric layer to the sharp corners of the control gate layer 125 (i.e. Figure 2a to Figure 2b and Figure 4a to Figure 4b The floating gate layer 123 in the embodiment points to the arrow in the control gate layer 125), so that the erasing operation of the semiconductor device is easier to perform. At this time, the second positive voltage is preferably in the range of 15V to 20V.

[0162] When the surface of the floating gate layer 123 opposite to the control gate layer 125 does not have a sharp corner (such as Figure 2c and Figure 4c In the embodiment shown in the figure, since there is no electric field enhancement effect, the second positive voltage applied to the control gate layer 125 should be greater than Figure 2a to Figure 2b and Figure 4a to Figure 4b In the embodiment shown, the second positive voltage applied to the control gate layer 125 can provide electrons with sufficient energy to move into the control gate layer 125. At this time, the second positive voltage is preferably in the range of 18V to 20V.

[0163] Furthermore, the pulse width when the second positive voltage is applied to the control gate layer 125 is preferably 10 ms.

[0164] Alternatively, ultraviolet rays are used to irradiate the semiconductor device so that electrons in the floating gate layer 123 can absorb the energy provided by the ultraviolet rays, thereby enabling the electrons to cross the potential barrier of the inter-gate dielectric layer and enter the control gate layer 125 to perform an erase operation on the semiconductor device.

[0165] A second negative voltage is applied to the drain region 16, the source region 15 is grounded, and the control gate layer 125 is floating or grounded, so as to perform a read operation on the semiconductor device. The second negative voltage may be in the range of -20V to -2V.

[0166] In addition, when the doping type of the drift region 13, the source region 15 and the drain region 16 is N-type, and the doping type of the well region 14 is P-type, the LDMOS device is an NLDMOS device, and the steps of performing a programming operation, an erasing operation and a reading operation on the semiconductor device include:

[0167] A third negative voltage is applied to the control gate layer 125 and a third positive voltage is applied to the source region 15, and the drain region 16 is floated to perform a programming operation on the semiconductor device; wherein, preferably, the third negative voltage ranges from -5V to -3V, and the third positive voltage ranges from 5.5V to 8V.

[0168] A fourth negative voltage is applied to the control gate layer 125, and the source region 15 and the drain region 16 are grounded to perform an erase operation on the semiconductor device; wherein, preferably, when the surfaces of the floating gate layer 123 relative to the control gate layer 125 have a sharp angle, the range of the fourth negative voltage is -12V to -8V; when the surfaces of the floating gate layer 123 relative to the control gate layer 125 do not have a sharp angle, the range of the fourth negative voltage is -20V to -18V.

[0169] Alternatively, ultraviolet rays are used to irradiate the semiconductor device to perform an erasing operation on the semiconductor device;

[0170] A fourth positive voltage is applied to the drain region 16, the source region 15 is grounded, and the control gate layer 125 is floating or grounded, so as to perform a read operation on the semiconductor device. The fourth positive voltage may be in the range of 10V to 100V.

[0171] Furthermore, when the LDMOS device is an NLDMOS device, the description of performing programming and erasing operations on the semiconductor device refers to the description when the LDMOS device is a PLDMOS device, and the difference from the LDMOS device being a PLDMOS device is that when the LDMOS device is an NLDMOS device, the holes are moved from the source region 15 into the floating gate layer 123 to implement programming operations on the semiconductor device, and the holes are moved from the floating gate layer 123 through the inter-gate dielectric layer and then into the control gate layer 125 to implement erasing operations on the semiconductor device.

[0172] From the above content, it can be seen that the programming operation, erasing operation and reading operation of the semiconductor device are all realized by external pressure application. Therefore, by adjusting the magnitude of the applied voltage, the number of electrons (when the LDMOS device is a PLDMOS device) or holes (when the LDMOS device is an NLDMOS device) in the floating gate layer can be adjusted, thereby making the inversion degree of the channel adjustable, so that the threshold voltage of the LDMOS device can be continuously adjusted, the threshold voltage of the LDMOS device is more controllable, and the perfect integration of the storage device and the LDMOS device is achieved.

[0173] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor device, It is characterized in that include: a substrate having a groove formed therein; A first isolation layer formed on the bottom wall of the trench; A floating gate layer is formed on the first isolation layer in the trench, and a tunneling oxide layer is sandwiched between the floating gate layer and the sidewall of the trench; A control gate layer is formed on the floating gate layer, an intergate dielectric layer is sandwiched between the control gate layer and the floating gate layer, and a second isolation layer is sandwiched between the control gate layer and the sidewall of the trench; a drift region formed in the substrate at the periphery of the trench; a well region formed in the drift region at the periphery of the trench; A source region is formed in the drift region outside the trench, the well region surrounds the source region, and a portion of the tunnel oxide layer is sandwiched between the source region and the floating gate layer; A drain region is formed in the drift region on a side of the source region away from the trench.

2. The semiconductor device according to claim 1, It is characterized in that The thickness of the tunnel oxide layer is smaller than the thickness of the second isolation layer.

3. The semiconductor device according to claim 1, It is characterized in that A surface of the floating gate layer opposite to the control gate layer has a sharp angle.

4. The semiconductor device according to claim 1, It is characterized in that The semiconductor device has a symmetrical structure, and the drift region, the source region and the drain region surround the trench.

5. The semiconductor device according to claim 4, It is characterized in that The longitudinal cross-sectional shapes of the floating gate layer and the control gate layer are square and T-shaped respectively, and a floating gate layer is formed on both sides of the "|" part of the control gate layer; or, the longitudinal cross-sectional shapes of the floating gate layer and the control gate layer are matching convex and concave respectively; or, the longitudinal cross-sectional shapes of the floating gate layer and the control gate layer are both square.

6. The semiconductor device according to claim 1, It is characterized in that The semiconductor device has an asymmetric structure, and the drift region, the source region and the drain region are located at least on one side of the trench.

7. The semiconductor device according to claim 6, It is characterized in that The longitudinal cross-sectional shapes of the floating gate layer and the control gate layer are square and L-shaped respectively, and the inner side of the L-shaped control gate layer faces the floating gate layer; or, the longitudinal cross-sectional shapes of the floating gate layer and the control gate layer are both L-shaped, and the inner side of the L-shaped floating gate layer faces the inner side of the L-shaped control gate layer; or, the longitudinal cross-sectional shapes of the floating gate layer and the control gate layer are both square.

8. A method for manufacturing a semiconductor device, It is characterized in that include: providing a substrate having a groove formed therein; forming a first isolation layer on the bottom wall of the trench; forming a tunneling oxide layer and a floating gate layer, wherein the floating gate layer is formed on the first isolation layer in the trench, and the tunneling oxide layer is sandwiched between the floating gate layer and the trench sidewall; forming an inter-gate dielectric layer, a second isolation layer and a control gate layer, wherein the control gate layer is formed on the floating gate layer, the inter-gate dielectric layer is sandwiched between the control gate layer and the floating gate layer, and the second isolation layer is sandwiched between the control gate layer and the sidewall of the trench; forming a drift region in the substrate at the periphery of the trench; forming a well region in the drift region at the periphery of the trench; A source region and a drain region are formed in the drift region outside the trench, and the well region surrounds the source region; a portion of the tunnel oxide layer is sandwiched between the source region and the floating gate layer, and the drain region is formed in the drift region on the side of the source region away from the trench.

9. The method for manufacturing a semiconductor device according to claim 8, It is characterized in that The thickness of the tunnel oxide layer is smaller than the thickness of the second isolation layer.

10. The method for manufacturing a semiconductor device according to claim 8, It is characterized in that A surface of the floating gate layer opposite to the control gate layer has a sharp angle.

11. A method for operating a semiconductor device, It is characterized in that include: A program operation, an erase operation, and a read operation are performed on the semiconductor device according to any one of claims 1 to 7.

12. The method for operating a semiconductor device according to claim 11, It is characterized in that When the doping types of the drift region, the source region, and the drain region are P-type, the steps of performing a programming operation, an erasing operation, and a reading operation on the semiconductor device include: Applying a first positive voltage to the control gate layer and a first negative voltage to the source region, with the drain region floating, to perform a programming operation on the semiconductor device; Applying a second positive voltage to the control gate layer, and grounding the source region and the drain region, to perform an erase operation on the semiconductor device; or irradiating the semiconductor device with ultraviolet rays to perform an erase operation on the semiconductor device; A second negative voltage is applied to the drain region, the source region is grounded, and the control gate layer is floated or grounded, so as to perform a read operation on the semiconductor device.

13. The method for operating a semiconductor device according to claim 11, It is characterized in that When the doping types of the drift region, the source region, and the drain region are N-type, the steps of performing a programming operation, an erasing operation, and a reading operation on the semiconductor device include: Applying a third negative voltage to the control gate layer and a third positive voltage to the source region, with the drain region being left floating, so as to perform a programming operation on the semiconductor device; A fourth negative voltage is applied to the control gate layer, and the source region and the drain region are grounded, so as to perform an erase operation on the semiconductor device; or ultraviolet rays are used to irradiate the semiconductor device, so as to perform an erase operation on the semiconductor device; A fourth positive voltage is applied to the drain region, and the source region is grounded, and the control gate layer is floating or grounded, so as to perform a read operation on the semiconductor device.

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