Circuit for synthesizing a negative impedance

Abstract

A circuit for synthesizing a negative impedance using a current reuse includes a current source circuit, a differential circuit, and a negative impedance conversion circuit. The current source circuit is configured to provide at least one predetermined current, wherein the current source circuit has a first port and a second port, and the first port of the current source circuit is coupled to a first reference voltage. The differential circuit is coupled between the second port of the current source circuit and a second reference voltage, and is configured to receive a differential input pair and generate a differential output pair, wherein the differential circuit has a differential output port. The negative impedance conversion circuit is coupled between the differential output port and a third reference voltage, wherein the third reference voltage is different from the first reference voltage.

Description

TECHNICAL FIELD

[0001] The present invention relates to a technique for synthesizing negative impedance, and more particularly to a circuit for reusing current to synthesize negative impedance. BACKGROUND

[0002] Generally speaking, in an amplifier circuit, the parasitic capacitance between the input and output terminals will be enlarged according to the Miller effect due to the amplification of the amplifier, which will not only affect the stability of the amplifier circuit, but also limit the operating bandwidth of the amplifier circuit. Therefore, a negative impedance conversion circuit is often coupled to the output terminal of the amplifier circuit (for example, a negative impedance synthesizing circuit includes an amplifier circuit and a negative impedance conversion circuit) to compensate for the parasitic capacitance, thereby improving the operating bandwidth of the amplifier circuit. The existing negative impedance conversion circuit usually includes two cross-coupled transistors and a fixed capacitor, and one end of the negative impedance conversion circuit is connected in parallel to the output terminal of the amplifier circuit, and the other end is grounded. Since the fixed capacitor sees a negative capacitance effect at the output terminal, the parasitic capacitance can be compensated, thereby obtaining a higher bandwidth. However, the existing negative impedance synthesizing circuit has a fatal drawback of requiring additional current consumption. In addition to the high overall power consumption of the negative impedance synthesizing circuit, the accompanying cost will also be increased. Therefore, a novel negative impedance synthesizing circuit is needed to solve this problem. SUMMARY

[0003] An object of the present invention is to provide a circuit for reusing current to synthesize negative impedance to solve the above problems.

[0004] At least one embodiment of the present invention provides a negative impedance synthesizing circuit that reuses current to synthesize negative impedance. The negative impedance synthesizing circuit can include a current source circuit, a differential circuit, and a negative impedance conversion circuit. The current source circuit can be used to provide at least one predetermined current, wherein the current source circuit has a first port and a second port, and the first port of the current source can be coupled to a first reference voltage. The differential circuit can be coupled between the second port of the current source circuit and a second reference voltage, and can be used to receive a differential input pair and generate a differential output pair, wherein the differential circuit has a differential output port for outputting the differential output pair. The negative impedance conversion circuit can be coupled between the differential output port and a third reference voltage, wherein the third reference voltage is different from the first reference voltage.

[0005] One advantage of this invention is that by connecting a negative impedance conversion circuit in parallel at the differential output port of the differential circuit, the negative impedance conversion circuit uses a portion of the current of the differential circuit to achieve the negative capacitance effect, thus eliminating the need for additional current consumption. In addition to increasing the bandwidth of the circuit that synthesizes the negative impedance, the power consumption and cost of the overall circuit can be reduced. Attached Figure Description

[0006] Figure 1 This is a block diagram of a synthetic negative impedance circuit according to an embodiment of the present invention.

[0007] Figure 2 This is a schematic diagram of a negative impedance conversion circuit according to an embodiment of the present invention.

[0008] Figure 3 for Figure 1 The circuit diagram shown is a schematic diagram of one embodiment of the synthesized negative impedance circuit.

[0009] Figure 4 for Figure 1 A circuit diagram of another embodiment of the synthesized negative impedance circuit shown.

[0010] Figure 5 This is a block diagram of a synthetic negative impedance circuit according to another embodiment of the present invention.

[0011] Figure 6 for Figure 5 The circuit diagram shown is a schematic diagram of one embodiment of the synthesized negative impedance circuit.

[0012] Figure 7 for Figure 5 A circuit diagram of another embodiment of the synthesized negative impedance circuit shown. Detailed Implementation

[0013] Figure 1Fig. 1 shows a block diagram of a synthetic negative impedance circuit 10 according to an embodiment of the present application. The synthetic negative impedance circuit 10 can include a current source circuit 100, a differential circuit 102, and a negative impedance conversion circuit 104. The current source circuit 100 can be configured to provide at least one predetermined current, i.e., the current source circuit 100 can include one or more current sources according to design requirements, and can include a plurality of connection ports 106, 108, wherein the connection port 106 can be coupled to a reference voltage VI. The differential circuit 102 can be coupled between the connection port 108 of the current source circuit 100 and a reference voltage V2, and can be configured to receive a differential input pair (i.e., differential input voltages INN, INP) and generate a differential output pair (i.e., differential output voltages OUTN, OUTP), wherein the reference voltage V2 is greater than the reference voltage VI, and further, the differential circuit 102 has a differential output port 110, wherein the differential output port 110 can include a plurality of output terminals 120, 122 for outputting the differential output pair (e.g., outputting the differential output voltages OUTN, OUTP, respectively). The negative impedance conversion circuit 104 can be coupled between the output terminals 120, 122 and a reference voltage V3, wherein the reference voltage V3 is different from the reference voltage V2, e.g., the reference voltage V3 is greater than the reference voltages VI, V2. Further, the differential circuit 102 includes a plurality of loads 112, 114, wherein the load 112 can be coupled between the output terminal 120 and the reference voltage V2, and the load 114 can be coupled between the output terminal 122 and the reference voltage V2, and the negative impedance conversion circuit 104 is in parallel with the load 112 at the output terminal 120, and in parallel with the load 114 at the output terminal 122. As shown in Fig. 1, the differential circuit 102 and the negative impedance conversion circuit 104 can share the at least one predetermined current provided by the current source circuit 100, thus, when the negative impedance conversion circuit 104 is to achieve a negative capacitance effect, only a portion of the at least one predetermined current is consumed, and no additional current is consumed. In addition to increasing the bandwidth of the synthetic negative impedance circuit 10, the power consumption and cost of the synthetic negative impedance circuit 10 can be reduced. Figure 1

[0014] Figure 2 Fig. 2 shows a schematic diagram of a negative impedance conversion circuit 200 according to an embodiment of the present application. Figure 1 As shown in Fig. 1, the negative impedance conversion circuit 104 can be implemented using the negative impedance conversion circuit 200 as shown in Fig. 2. Figure 2 Figure 2 ​​As shown, the negative impedance conversion circuit 200 may include a variable capacitor 202 and a plurality of P-type metal-oxide-semiconductor field-effect transistors (MOSFETs; for simplicity, referred to as transistors) 204 and 206, wherein the gate of the P-type transistor 204 can be coupled to the drain of the P-type transistor 206, and the gate of the P-type transistor 206 can be coupled to the drain of the P-type transistor 204 (i.e., the P-type transistors 204 and 206 are cross-coupled), and the variable capacitor 202 can be coupled between the source of the P-type transistor 204 and the source of the P-type transistor 206. In addition, the frequency response of the synthesized negative impedance circuit 10 at high frequencies can be fine-tuned by adjusting the capacitance value of the variable capacitor 202.

[0015] Figure 3 for Figure 1 The circuit diagram shown is a schematic diagram of one embodiment of the composite negative impedance circuit 10. Figure 1 The synthesized negative impedance circuit 10 shown can utilize Figure 3 The synthesized negative impedance circuit 30 shown is used for implementation, that is, the synthesized negative impedance circuit 30 also adopts Figure 1 The architecture shown is as follows: Figure 3 As shown, the synthesized negative impedance circuit 30 may include a current source 300, a current mode logic (CML) amplifier 302, and a negative impedance conversion circuit 304, wherein the current source 300 is used to implement... Figure 1 The current source circuit 100 and current-mode logic amplifier 302 shown are used to implement... Figure 1 The differential circuit 102 and the negative impedance conversion circuit 304 shown are used to implement Figure 1 The negative impedance conversion circuit 104 is shown. In this embodiment, the current source 300 (e.g., Figure 1 One end of the current source circuit 100 shown can be grounded (e.g., Figure 1 The reference voltage V1 shown is 0), and the other end of the current source 300 can be coupled to the current-mode logic amplifier 302 (e.g., the reference voltage V1 = 0). Figure 1 The differential circuit 102 shown is used, and the current source 300 can be used to provide a predetermined current I1. The current-mode logic amplifier 302 can be coupled to the current source 300 and a power supply voltage VDD2 (e.g., ...). Figure 1 The reference voltage V2 shown is between, and can be used to receive a differential input pair (i.e., differential input voltages INN, INP) and generate a differential output pair (i.e., differential output voltages OUTN, OUTP), and may include a plurality of parasitic capacitors 314, 316, a plurality of N-type transistors 318, 320 and a plurality of output terminals 328, 330 (e.g., ...).Figure 1 The output terminals 120 and 122 shown are provided. Parasitic capacitors 314 and 316 can be located between output terminals 328 and 330 and ground, respectively. N-type transistors 318 and 320 can be coupled between output terminals 328 and 330 and current source 300, respectively. Output terminals 328 and 330 can be used to output the differential output pair (e.g., output differential output voltages OUTN and OUTP, respectively).

[0016] The negative impedance conversion circuit 304 can be coupled to output terminal 328, output terminal 330 and a power supply voltage VDD1 (e.g. Figure 1 The reference voltage V3 shown is between, and may include a plurality of P-type transistors 322 and 324 and a variable capacitor 326. The drain of P-type transistor 322 is coupled to output terminal 328, and the gate of P-type transistor 322 is coupled to output terminal 330. The drain of P-type transistor 324 is coupled to output terminal 330, and the gate of P-type transistor 324 is coupled to output terminal 328 (i.e., P-type transistors 322 and 324 are cross-coupled, which can be...). Figure 2 (Implemented by the negative impedance conversion circuit 200 shown), the variable capacitor 326 can be coupled between the source of P-type transistor 322 and the source of P-type transistor 324, and the power supply voltage VDD1 is greater than the power supply voltage VDD2. The current-mode logic amplifier 302 may also include a plurality of resistors 310, 312 (e.g., Figure 1 The loads 112 and 114 shown are provided, wherein resistor 310 can be coupled between output terminal 328 and power supply voltage VDD2, resistor 312 can be coupled between output terminal 330 and power supply voltage VDD2, and negative impedance conversion circuit 304 and resistor 310 can be connected in parallel to output terminal 328 and in parallel with resistor 312 to output terminal 330.

[0017] It should be noted that resistors 310 and 312 (e.g., in the current-mode logic amplifier 302) Figure 1 The loads 112 and 114 shown can be replaced by passive inductors, active inductors, or series, parallel, or series-parallel combinations of inductors or resistors. The use of resistors to represent loads here is merely illustrative and is not intended to limit the invention. Furthermore, a plurality of current sources 306 and 308 may be present between the negative impedance conversion circuit 304 and the power supply voltage VDD1 to provide a current I2 flowing through the P-type transistor 322 and a current I3 flowing through the P-type transistor 324, respectively.

[0018] like Figure 3As shown, the current-mode logic amplifier 302 and the negative impedance conversion circuit 304 can share the current source 300 (i.e. share the predetermined current I1 provided by the current source 300), that is, the current I2 and the current I3 are part of the predetermined current I1, thus, when the negative impedance conversion circuit 304 achieves the negative capacitance effect by the equivalent impedance seen at the output terminals 328, 330 via the variable capacitance 326 to compensate for the parasitic capacitances 314, 316, the negative impedance conversion circuit 304 only needs to consume part of the predetermined current I1 itself (i.e. the current I2 and the current I3), and does not need to consume additional current, in addition to increasing the bandwidth of the synthetic negative impedance circuit 30, the power consumption and the cost of the synthetic negative impedance circuit 30 can be reduced, and in addition, the capacitance value of the variable capacitance 326 can be adjusted to fine-tune the frequency response of the synthetic negative impedance circuit 30 at high frequencies.

[0019] Figure 4 For Figure 1 the circuit schematic diagram of another embodiment of the synthetic negative impedance circuit 10. Figure 1 The synthetic negative impedance circuit 10 can be implemented by using Figure 4 the synthetic negative impedance circuit 40, that is, the synthetic negative impedance circuit 40 also adopts Figure 1 the architecture as shown, such as Figure 4 As shown, the synthetic negative impedance circuit 40 can include a plurality of current sources 400, 401, a continuous time linear equalizer (CTLE) 402, and a negative impedance conversion circuit 404, wherein the current sources 400, 401 are used to implement Figure 1 the current source circuit 100 as shown, the continuous time linear equalizer 402 is used to implement Figure 1 the differential circuit 102 as shown, and the negative impedance conversion circuit 404 is used to implement Figure 1 the negative impedance conversion circuit 104 as shown. One end of the current sources 400, 401 (for example Figure 1 the current source circuit 100 as shown) is grounded (for example Figure 1 the reference voltage V1 = 0 as shown), the other end of the current sources 400, 401 is coupled to the continuous time linear equalizer 402 (for example Figure 1 the differential circuit 102 as shown), and the current sources 400, 401 can be used to provide a plurality of predetermined currents I1, I2 to the synthetic negative impedance circuit 40, respectively, and the sum of the predetermined currents I1, I2 is I3 (i.e. I3 = I1 + I2). The continuous time linear equalizer 402 can be coupled to the current sources 400, 401 and a power supply voltage VDD2 (for example Figure 1between the reference voltages V2) and can be configured to receive a differential input pair (i.e., differential input voltages INN, INP) and generate a differential output pair (i.e., differential output voltages OUTN, OUTP), and can include parasitic capacitances 414, 416, N-type transistors 418, 420, output terminals 428, 430 (e.g. Figure 1 shown as output terminals 120, 122), a resistor 432, and a variable capacitance 434, where the parasitic capacitances 414, 416 can be between the output terminals 428, 430 and ground, the N-type transistors 418, 420 can be coupled between the output terminals 428, 430 and current sources 400, 401, the output terminals 428, 430 can be configured to output the differential output pair (e.g., output differential output voltages OUTN, OUTP, respectively), the resistor 432 can be coupled between the source of the N-type transistor 418 and the source of the N-type transistor 420, and the variable capacitance 434 can be coupled between the current sources 400, 401 and the resistor 432.

[0020] The negative impedance conversion circuit 404 can be coupled between the output terminal 428, the output terminal 430, and a supply voltage VDD1 (e.g. Figure 1 shown as reference voltage V3), and can include P-type transistors 422, 424, and a variable capacitance 426, where the drain of the P-type transistor 422 can be coupled to the output terminal 428, the gate of the P-type transistor 422 can be coupled to the output terminal 430, the drain of the P-type transistor 424 can be coupled to the output terminal 430, the gate of the P-type transistor 424 can be coupled to the output terminal 428 (i.e., the P-type transistors 422, 424 are cross-coupled, which can be implemented by the negative impedance conversion circuit 200 shown in Figure 2 FIG. 2), the variable capacitance 426 can be coupled between the source of the P-type transistor 422 and the source of the P-type transistor 424, and the supply voltage VDD1 can be greater than the supply voltage VDD2. The continuous-time linear equalizer 402 can also include resistors 410, 412 (e.g. Figure 1 shown as loads 112, 114), where the resistor 410 can be coupled between the output terminal 428 and the supply voltage VDD2, the resistor 412 can be coupled between the output terminal 430 and the supply voltage VDD2, and the negative impedance conversion circuit 404 and the resistor 410 can be in parallel at the output terminal 428, and the negative impedance conversion circuit 404 and the resistor 412 can be in parallel at the output terminal 430. It should be noted that the resistors 410, 412 (e.g. Figure 1The loads 112 and 114 shown can be replaced by passive inductors, active inductors, or series, parallel, or series-parallel combinations of inductors or resistors. The use of resistors to represent loads here is merely illustrative and is not intended to limit the invention. Furthermore, a plurality of current sources 406 and 408 may be present between the negative impedance conversion circuit 404 and the power supply voltage VDD1 to provide a current I4 flowing through the P-type transistor 422 and a current I5 flowing through the P-type transistor 424, respectively.

[0021] like Figure 4 As shown, the continuous-time linear equalizer 402 and the negative impedance conversion circuit 404 can share the current sources 400 and 401 (i.e., share the current I3 provided by the current sources 400 and 401). That is to say, the currents I4 and I5 are a portion of the current I3. Therefore, when the negative impedance conversion circuit 404 achieves the negative capacitance effect by using the equivalent impedance seen by the variable capacitor 426 at the output terminals 428 and 430 to compensate for the parasitic capacitances 414 and 416, the negative impedance conversion circuit 404 only needs to consume a portion of the predetermined current I3 (i.e., currents I4 and I5), and does not need to consume additional current. In addition to increasing the bandwidth of the synthesized negative impedance circuit 40, the power consumption and cost of the synthesized negative impedance circuit 40 can be reduced. Furthermore, the capacitance value of the variable capacitor 426 can be adjusted to fine-tune the frequency response of the synthesized negative impedance circuit 40 at high frequencies.

[0022] Please note, Figure 3 and Figure 4 The circuit shown is for illustrative purposes only and is not intended to limit the invention. In fact, any circuit based on... Figure 1 The synthetic negative impedance circuits implemented by the architecture shown all fall within the scope of this invention.

[0023] Figure 1 If the reference voltage V3 of the synthetic negative impedance circuit 10 shown is high enough, it is not necessary to supply another reference voltage V2 that is different from the reference voltage V3, and the loads 112 and 114 are coupled to the reference voltage V3 respectively (i.e., the reference voltage V2 is equal to the reference voltage V3). In this way, a synthetic negative impedance circuit that reuses current can also be realized.

[0024] Figure 5 This is a block diagram of a synthesized negative impedance circuit 50 according to another embodiment of the present invention. The synthesized negative impedance circuit 50 may include a current source circuit 500, a differential circuit 502, and a negative impedance conversion circuit 504 (which may be composed of...). Figure 2(This is implemented using the negative impedance conversion circuit 200 shown). The current source circuit 500 can be used to provide at least a predetermined current and may include a plurality of connection ports 506, 508, with connection port 506 being coupled to a reference voltage V1. The differential circuit 502 can be coupled between the connection port 508 of the current source circuit 500 and a reference voltage V2, and can be used to receive a differential input pair (i.e., differential input voltages INN, INP) and generate a differential output pair (i.e., differential output voltages OUTN, OUTP), wherein the reference voltage V2 is greater than the reference voltage V1. In addition, the differential circuit 502 has a differential output port 510, wherein the differential output port 510 may include a plurality of output terminals 520, 522 for outputting the differential output pair (e.g., outputting differential output voltages OUTN, OUTP respectively). The negative impedance conversion circuit 504 can be coupled between the output terminals 520, 522 and the reference voltage V2. Furthermore, the differential circuit 502 also includes a plurality of loads 512 and 514, wherein load 512 can be coupled between output terminal 520 and reference voltage V2, load 514 can be coupled between output terminal 522 and reference voltage V2, and the negative impedance conversion circuit 504 and load 512 can be connected in parallel at output terminal 520, and in parallel at output terminal 522 with load 514. Figure 5 As shown, the differential circuit 502 and the negative impedance conversion circuit 504 can share the at least one predetermined current provided by the current source circuit 500. Therefore, when the negative impedance conversion circuit 504 wants to achieve the negative capacitance effect, it only needs to consume a portion of the at least one predetermined current and does not need to consume additional current. In addition to increasing the bandwidth of the synthesized negative impedance circuit 50, the power consumption and cost of the synthesized negative impedance circuit 50 can also be reduced.

[0025] Figure 6 for Figure 5 The circuit diagram shown is a schematic diagram of one embodiment of the composite negative impedance circuit 50. Figure 5 The synthesized negative impedance circuit 50 shown can be used Figure 6 The synthesized negative impedance circuit 60 shown is used for implementation, that is, the synthesized negative impedance circuit 60 also adopts Figure 5 The architecture shown is as follows: Figure 6 As shown, the synthesized negative impedance circuit 60 may include a current source 600, a current-mode logic amplifier 602, and a negative impedance conversion circuit 604, wherein the current source 600 is used to implement... Figure 5 The current source circuit 500 and current-mode logic amplifier 602 shown are used to implement... Figure 5 The differential circuit 502 and the negative impedance conversion circuit 604 shown are used to implement Figure 5 The negative impedance conversion circuit 504 is shown. Current source 600 (e.g.) Figure 5 One end of the current source circuit 500 shown can be grounded (e.g., Figure 5The reference voltage V1 shown is 0), and the other end of the current source 600 can be coupled to the current-mode logic amplifier 602 (e.g., the reference voltage V1 = 0). Figure 5 The differential circuit 502 shown is used, and the current source 600 can be used to provide a predetermined current I1. The current-mode logic amplifier 602 can be coupled to the current source 600 and a power supply voltage VDD1 (e.g., ...). Figure 5 The reference voltage V2 shown is between, and can be used to receive a differential input pair (i.e., differential input voltages INN, INP) and generate a differential output pair (i.e., differential output voltages OUTN, OUTP), and may include a plurality of parasitic capacitors 614, 616, a plurality of N-type transistors 618, 620 and a plurality of output terminals 628, 630 (e.g., ...). Figure 5 The output terminals 520 and 522 shown are provided. Parasitic capacitors 614 and 616 can be located between the output terminals 628 and 630 and ground, respectively. N-type transistors 618 and 620 can be coupled between the output terminals 628 and 630 and the current source 600, respectively. The output terminals 628 and 630 can be used to output the differential output pair (e.g., output differential output voltages OUTN and OUTP, respectively).

[0026] The negative impedance conversion circuit 604 can be coupled to output terminal 628, output terminal 630, and power supply voltage VDD1 (e.g., Figure 5 The reference voltage V2 shown is between, and may include a plurality of P-type transistors 622 and 624 and a variable capacitor 626, wherein the drain of P-type transistor 622 can be coupled to the output terminal 628, the gate of P-type transistor 622 can be coupled to the output terminal 630, the drain of P-type transistor 624 can be coupled to the output terminal 630, and the gate of P-type transistor 624 can be coupled to the output terminal 628 (that is, P-type transistors 622 and 624 are cross-coupled, which can be obtained from...). Figure 2 (Implemented by the negative impedance conversion circuit 200 shown), the variable capacitor 626 can be coupled between the source of P-type transistor 622 and the source of P-type transistor 624. The current-mode logic amplifier 602 may also include a plurality of resistors 610, 612 (e.g., ...). Figure 5 The loads 512 and 514 shown are configured such that resistor 610 can be coupled between output terminal 628 and power supply voltage VDD1, and resistor 612 can be coupled between output terminal 630 and power supply voltage VDD1. The negative impedance conversion circuit 604 and resistor 610 can be connected in parallel at output terminal 628, and in parallel with resistor 612 at output terminal 630. It should be noted that resistors 610 and 612 (e.g., in the current-mode logic amplifier 602) are... Figure 5The loads 512 and 514 shown can be replaced by passive inductors, active inductors, or series, parallel, or series-parallel combinations of inductors or resistors. The use of resistors to represent loads here is merely illustrative and is not intended to limit the invention. Furthermore, a plurality of current sources 606 and 608 may be present between the negative impedance conversion circuit 604 and the power supply voltage VDD1 to provide a current I2 flowing through the P-type transistor 622 and a current I3 flowing through the P-type transistor 624, respectively.

[0027] like Figure 6 As shown, the current-mode logic amplifier 602 and the negative impedance conversion circuit 604 can share the current source 600 (i.e., the predetermined current I1 provided by the shared current source 600). That is to say, the currents I2 and I3 are a portion of the predetermined current I1. Therefore, when the negative impedance conversion circuit 604 achieves the negative capacitance effect by using the equivalent impedance seen by the variable capacitor 626 at the output terminals 628 and 630 to compensate for the parasitic capacitances 614 and 616, the negative impedance conversion circuit 604 only needs to consume a portion of the predetermined current I1 (i.e., currents I2 and I3), and does not need to consume additional current. In addition to increasing the bandwidth of the synthesized negative impedance circuit 60, the power consumption and cost of the synthesized negative impedance circuit 60 can be reduced. Furthermore, the value of the variable capacitor 626 can be adjusted to fine-tune the frequency response of the synthesized negative impedance circuit 60 at high frequencies.

[0028] Figure 7 for Figure 5 A circuit diagram of another embodiment of the synthesized negative impedance circuit 50 shown. Figure 5 The synthesized negative impedance circuit 50 shown can be used Figure 7 The synthesized negative impedance circuit 70 shown is used for implementation, that is, the synthesized negative impedance circuit 70 also adopts Figure 5 The architecture shown is as follows: Figure 7 As shown, the synthesized negative impedance circuit 70 may include a current source 700, a current-mode logic amplifier 702, and a negative impedance conversion circuit 704, wherein the current source 700 is used to implement... Figure 5 The current source circuit 500 and current-mode logic amplifier 702 shown are used to implement... Figure 5 The differential circuit 502 and the negative impedance conversion circuit 704 shown are used to implement Figure 5 The negative impedance conversion circuit 504 is shown. Current source 700 (e.g.) Figure 5 One end of the current source circuit 500 shown can be grounded (e.g., Figure 5 The reference voltage V1 shown is 0), and the other end of the current source 700 can be coupled to the current-mode logic amplifier 702 (e.g., the reference voltage V1 = 0). Figure 5The differential circuit 502) and a current source 700 can be used to provide a predetermined current II. A current-mode logic amplifier 702 can be coupled between the current source 700 and a supply voltage VDDl (e.g., the reference voltage V2) and can be used to receive a differential input pair (i.e., differential input voltages INN, INP) and generate a differential output pair (i.e., differential output voltages OUTN, OUTP) and can include parasitic capacitances 714, 716, N-type transistors 718, 720, and output terminals 728, 730 (e.g., the output terminals 520, 522). Figure 5 The differential circuit 502) and a current source 700 can be used to provide a predetermined current II. A current-mode logic amplifier 702 can be coupled between the current source 700 and a supply voltage VDDl (e.g., the reference voltage V2) and can be used to receive a differential input pair (i.e., differential input voltages INN, INP) and generate a differential output pair (i.e., differential output voltages OUTN, OUTP) and can include parasitic capacitances 714, 716, N-type transistors 718, 720, and output terminals 728, 730 (e.g., the output terminals 520, 522). Figure 5 The differential circuit 502) and a current source 700 can be used to provide a predetermined current II. A current-mode logic amplifier 702 can be coupled between the current source 700 and a supply voltage VDDl (e.g., the reference voltage V2) and can be used to receive a differential input pair (i.e., differential input voltages INN, INP) and generate a differential output pair (i.e., differential output voltages OUTN, OUTP) and can include parasitic capacitances 714, 716, N-type transistors 718, 720, and output terminals 728, 730 (e.g., the output terminals 520, 522).

[0029] The differential circuit 502) and a current source 700 can be used to provide a predetermined current II. A current-mode logic amplifier 702 can be coupled between the current source 700 and a supply voltage VDDl (e.g., the reference voltage V2) and can be used to receive a differential input pair (i.e., differential input voltages INN, INP) and generate a differential output pair (i.e., differential output voltages OUTN, OUTP) and can include parasitic capacitances 714, 716, N-type transistors 718, 720, and output terminals 728, 730 (e.g., the output terminals 520, 522). Figure 2 The differential circuit 502) and a current source 700 can be used to provide a predetermined current II. A current-mode logic amplifier 702 can be coupled between the current source 700 and a supply voltage VDDl (e.g., the reference voltage V2) and can be used to receive a differential input pair (i.e., differential input voltages INN, INP) and generate a differential output pair (i.e., differential output voltages OUTN, OUTP) and can include parasitic capacitances 714, 716, N-type transistors 718, 720, and output terminals 728, 730 (e.g., the output terminals 520, 522). Figure 5 The differential circuit 502) and a current source 700 can be used to provide a predetermined current II. A current-mode logic amplifier 702 can be coupled between the current source 700 and a supply voltage VDDl (e.g., the reference voltage V2) and can be used to receive a differential input pair (i.e., differential input voltages INN, INP) and generate a differential output pair (i.e., differential output voltages OUTN, OUTP) and can include parasitic capacitances 714, 716, N-type transistors 718, 720, and output terminals 728, 730 (e.g., the output terminals 520, 522). Figure 5 The differential circuit 502) and a current source 700 can be used to provide a predetermined current II. A current-mode logic amplifier 702 can be coupled between the current source 700 and a supply voltage VDDl (e.g., the reference voltage V2) and can be used to receive a differential input pair (i.e., differential input voltages INN, INP) and generate a differential output pair (i.e., differential output voltages OUTN, OUTP) and can include parasitic capacitances 714, 716, N-type transistors 718, 720, and output terminals 728, 730 (e.g., the output terminals 520, 522). Figure 5The loads 512 and 514 shown can be replaced by passive inductors, active inductors, or series, parallel, or series-parallel combinations of inductors or resistors. The use of resistors to represent loads here is merely illustrative and is not intended to limit the invention. Furthermore, a resistor 713 is provided between the power supply voltage VDD1 and the current-mode logic amplifier 702 to divide the power supply voltage VDD1 to the current-mode logic amplifier 702 as another reference voltage. This allows the synthesized negative impedance circuit 70 to achieve [the desired effect] even though it only has one power supply voltage VDD1 (e.g., reference voltage V2). Figure 1 The synthesized negative impedance circuit 10 shown (i.e., two reference voltages) may have multiple current sources 706 and 708 between the negative impedance conversion circuit 704 and the power supply voltage VDD1, which are used to provide a current I2 flowing through the P-type transistor 722 and a current I3 flowing through the P-type transistor 724, respectively.

[0030] like Figure 7 As shown, the current-mode logic amplifier 702 and the negative impedance conversion circuit 704 can share the current source 700 (i.e., the predetermined current I1 provided by the shared current source 700). That is to say, the currents I2 and I3 are a portion of the predetermined current I1. Therefore, when the negative impedance conversion circuit 704 achieves the negative capacitance effect by using the equivalent impedance seen by the variable capacitor 726 at the output terminals 728 and 730 to compensate for the parasitic capacitances 714 and 716, the negative impedance conversion circuit 704 only needs to consume a portion of the predetermined current I1 (i.e., currents I2 and I3), and does not need to consume additional current. In addition to increasing the bandwidth of the synthesized negative impedance circuit 70, the power consumption and cost of the synthesized negative impedance circuit 70 can be reduced. Furthermore, the value of the variable capacitor 726 can be adjusted to fine-tune the frequency response of the synthesized negative impedance circuit 70 at high frequencies.

[0031] Please note, Figure 6 and Figure 7 The circuit shown is for illustrative purposes only and is not intended to limit the invention. In fact, any circuit based on... Figure 5 The synthetic negative impedance circuits implemented by the architecture shown all fall within the scope of this invention.

[0032] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

[0033] [Symbol Explanation]

[0034] 10, 30, 40, 50, 60, 70: Synthetic negative impedance circuit

[0035] 100, 500: Current source circuit

[0036] 102, 502: Differential circuit

[0037] 104, 200, 304, 404, 504, 604, 704: negative impedance conversion circuit

[0038] 106, 108, 506, 508: connection port

[0039] 110, 510: differential output port

[0040] 112, 114, 512, 514: load

[0041] 120, 122, 328, 330, 428, 430, 520, 522, 628, 630, 728, 730: output

[0042] 202, 326, 426, 434, 626, 726: variable capacitance

[0043] 204, 206, 322, 324, 422, 424, 622, 624, 722, 724: P-type metal oxide semiconductor field effect transistor

[0044] 300, 306, 308, 400, 401, 406, 408, 600, 606, 608, 700, 706, 708: current source

[0045] 302, 602, 702: current mode logic amplifier

[0046] 310, 312, 410, 412, 432, 610, 612, 710, 712, 713: resistance

[0047] 314, 316, 414, 416, 614, 616, 714, 716: parasitic capacitance

[0048] 318, 320, 418, 420, 618, 620, 718, 720: N-type metal oxide semiconductor field effect transistor

[0049] 402: continuous-time linear equalizer

[0050] V1, V2, V3: reference voltage

[0051] INN, INP: differential input voltage

[0052] OUTN, OUTP: differential output voltage

[0053] VDD1, VDD2: power supply voltage

Claims

1. A circuit for synthesizing a negative impedance, characterized by Comprising: a current source circuit configured to provide at least a predetermined current, wherein the current source circuit has a first port and a second port, and the first port of the current source circuit is coupled to a first reference voltage; a differential circuit coupled between the second port of the current source circuit and a second reference voltage, configured to receive a differential input pair and generate a differential output pair, wherein the differential circuit has a differential output port configured to output the differential output pair; and a negative impedance conversion circuit coupled between the differential output port and a third reference voltage, wherein the third reference voltage is different from the first reference voltage, wherein the differential output port comprises a first output and a second output, the negative impedance conversion circuit comprises: a first P-type transistor, wherein a drain of the first P-type transistor is coupled to the first output, and a gate of the first P-type transistor is coupled to the second output; a second P-type transistor, wherein a drain of the second P-type transistor is coupled to the second output, and a gate of the second P-type transistor is coupled to the first output; and a capacitor coupled between a source of the first P-type transistor and a source of the second P-type transistor. The second reference voltage and the third reference voltage are both higher than the first reference voltage.

2. The circuit of claim 1, wherein, The third reference voltage is different from the second reference voltage.

3. The circuit of claim 1, wherein, The third reference voltage is higher than the second reference voltage.

4. The circuit of claim 3, wherein, The second reference voltage is equal to the third reference voltage.

5. The circuit of claim 1, wherein, The differential circuit comprises:

6. The circuit of claim 1, wherein a first load coupled between the first output and the second reference voltage; and a second load coupled between the second output and the second reference voltage; The negative impedance conversion circuit is in parallel with the first load at the first output, and in parallel with the second load at the second output. The capacitor is a variable capacitor. The first load is one of a resistor, a passive inductor, an active inductor, and a series, parallel, or series-parallel combination of inductors or resistors.

7. The circuit of claim 1, wherein, The second load is one of a resistor, a passive inductor, an active inductor, and a series, parallel, or series-parallel combination of inductors or resistors.

8. The circuit of claim 6, wherein, ​ 9. The circuit of claim 6, wherein, ​

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