A data conversion circuit, method and memory

Abstract

The disclosed embodiment provides a data conversion circuit, method and memory, the circuit includes a conversion module, an adjustment module and a transmission module, one end of the adjustment module is used to receive a compensation signal, and the other end of the adjustment module is connected to the output end of the conversion module and the input end of the transmission module respectively, wherein: the conversion module is used to receive an initial data signal, and perform parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal; the adjustment module is used to perform compensation processing on the intermediate data signal according to the compensation signal to reduce the signal swing of the intermediate data signal; the transmission module is used to perform drive enhancement processing on the intermediate data signal after the compensation processing to obtain a target data signal. The disclosed embodiment can reduce the signal swing of the intermediate data signal, increase the signal bandwidth, and improve the high-frequency performance of the circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a data conversion circuit, method and memory. Background Art

[0002] During data transmission, there is often a need to convert parallel data into serial data. In order to obtain faster data transmission speeds, a series of devices such as memories that can transmit data at double data rate (DDR) have emerged. However, as the data rate increases, for example, from 4266 megabits per second (Mbps) of LPDDR4 to 6400Mbps of LPDDR5, due to the limitation of device performance, for circuits that convert parallel data into serial data, the parasitic capacitance of the data node is large, thus limiting the high-frequency performance of the circuit. Summary of the invention

[0003] Embodiments of the present disclosure provide a data conversion circuit, method and memory.

[0004] In a first aspect, an embodiment of the present disclosure provides a data conversion circuit, comprising a conversion module, an adjustment module and a transmission module, wherein one end of the adjustment module is used to receive a compensation signal, and the other end of the adjustment module is connected to an output end of the conversion module and an input end of the transmission module, respectively, wherein:

[0005] The conversion module is used to receive an initial data signal, and perform parallel-to-serial processing on the initial data signal to obtain an intermediate data signal;

[0006] The adjustment module is used to perform compensation processing on the intermediate data signal according to the compensation signal to reduce the signal swing of the intermediate data signal;

[0007] The transmission module is used to perform driving enhancement processing on the intermediate data signal after compensation processing to obtain a target data signal.

[0008] In some embodiments, the adjustment module includes a transmission gate module, one end of the transmission gate module is used to receive the compensation signal, the other end of the transmission gate module is connected to the output end of the conversion module and the input end of the transmission module respectively, and the control end of the transmission gate module is used to receive an enable control signal, wherein:

[0009] When the enable control signal is in a valid state, the transmission gate module is turned on to perform compensation processing on the intermediate data signal according to the compensation signal; or, when the enable control signal is in an invalid state, the transmission gate module is turned off.

[0010] In some embodiments, the enable control signal includes a first enable control signal and a second enable control signal, wherein:

[0011] The transmission gate module comprises an NMOS tube and a PMOS tube, the first end of the NMOS tube is connected to the first end of the PMOS tube as one end of the transmission gate module, and the second end of the NMOS tube is connected to the second end of the PMOS tube as the other end of the transmission gate module;

[0012] The control end of the transmission gate module includes a gate end of the NMOS tube and a gate end of the PMOS tube, the gate end of the NMOS tube is connected to the first enable control signal, the gate end of the PMOS tube is connected to the second enable control signal, and the first enable control signal and the second enable control signal are inverted signals to each other.

[0013] In some embodiments, the adjustment module further includes a first NOT gate, an input end of the first NOT gate is connected to the gate end of the NMOS tube, and an output end of the first NOT gate is connected to the gate end of the PMOS tube, wherein:

[0014] The first NOT gate is used to receive the first enable control signal and perform inversion processing on the first enable control signal to obtain the second enable control signal.

[0015] In some embodiments, the adjustment module includes a resistance module, one end of the resistance module is used to receive the compensation signal, and the other end of the resistance module is connected to the output end of the conversion module and the input end of the transmission module respectively, wherein:

[0016] The resistor module is used to perform compensation processing on the intermediate data signal according to the compensation signal to reduce the signal swing of the intermediate data signal.

[0017] In some embodiments, the transmission module includes a first transmission submodule and a second transmission submodule, the input end of the first transmission submodule is connected to the output end of the conversion module, and the output end of the first transmission submodule is connected to the input end of the second transmission submodule, wherein:

[0018] The first transmission submodule is used to perform inversion processing on the intermediate data signal after compensation processing to obtain an initial target data signal;

[0019] The second transmission submodule is used to perform inversion processing on the initial target data signal to obtain the target data signal.

[0020] In some embodiments, one end of the adjustment module is connected to the output end of the first transmission submodule, and the other end of the adjustment module is connected to the input end of the first transmission submodule, wherein:

[0021] The first transmission submodule is further configured to determine the initial target data signal as the compensation signal.

[0022] In some embodiments, the first transmission submodule includes a second NOT gate and a first NAND gate, the second transmission submodule includes a third NOT gate, the first input end of the first NAND gate is used to receive a transmission control signal, the second input end of the first NAND gate is connected to the output end of the second NOT gate and the input end of the third NOT gate, and the output end of the first NAND gate is connected to the input end of the second NOT gate; wherein the input end of the second NOT gate serves as the input end of the first transmission submodule, the output end of the second NOT gate serves as the output end of the first transmission submodule, the input end of the third NOT gate serves as the input end of the second transmission submodule, and the output end of the third NOT gate serves as the output end of the second transmission submodule.

[0023] In some embodiments, the conversion module includes a first conversion submodule, a second conversion submodule, a third conversion submodule and a fourth conversion submodule, and the initial data signal includes first initial data, second initial data, third initial data and fourth initial data, wherein:

[0024] The first conversion submodule is used to receive the first initial data and a first clock signal, and perform sampling processing on the first initial data according to the first clock signal to obtain first intermediate data;

[0025] The second conversion submodule is used to receive the second initial data and a second clock signal, and perform sampling processing on the second initial data according to the second clock signal to obtain second intermediate data;

[0026] The third conversion submodule is configured to receive the third initial data and a third clock signal, and perform sampling processing on the third initial data according to the third clock signal to obtain third intermediate data;

[0027] The fourth conversion submodule is configured to receive the fourth initial data and a fourth clock signal, and perform sampling processing on the fourth initial data according to the fourth clock signal to obtain fourth intermediate data;

[0028] Among them, the phases of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are 0 degrees, 90 degrees, 180 degrees and 270 degrees respectively, and the first intermediate data, the second intermediate data, the third intermediate data and the fourth intermediate data constitute the intermediate data signal.

[0029] In some embodiments, the conversion module includes a first conversion module and a second conversion module, the initial data signal includes a first initial data signal and a second initial data signal, and the first initial data signal and the second initial data signal are a pair of differential signals, and the intermediate data signal includes a first intermediate data signal and a second intermediate data signal, wherein:

[0030] The first conversion module is used to receive the first initial data signal, and perform parallel-to-serial processing on the first initial data signal to obtain the first intermediate data signal;

[0031] The second conversion module is used to receive the second initial data signal, and perform parallel-to-serial processing on the second initial data signal to obtain the second intermediate data signal.

[0032] In some embodiments, the compensation signal includes the first intermediate data signal and the second intermediate data signal, wherein:

[0033] The adjustment module is used to perform compensation processing on the second intermediate data signal according to the first intermediate data signal to reduce the signal swing of the second intermediate data signal; and to perform compensation processing on the first intermediate data signal according to the second intermediate data signal to reduce the signal swing of the first intermediate data signal.

[0034] In some embodiments, the target data signal includes a first target data signal and a second target data signal, and the transmission module includes a first transmission module and a second transmission module, wherein:

[0035] The first transmission module is used to perform driving enhancement processing on the first intermediate data signal after compensation processing to obtain the first target data signal;

[0036] The second transmission module is used to perform driving enhancement processing on the second intermediate data signal after compensation processing to obtain the second target data signal.

[0037] In some embodiments, one end of the adjustment module is connected to the output end of the first conversion module and the input end of the first transmission module respectively, and the other end of the adjustment module is connected to the output end of the second conversion module and the input end of the second transmission module respectively.

[0038] In some embodiments, the initial data signal is a parallel data signal, and the intermediate data signal and the target data signal are both serial data signals.

[0039] In a second aspect, an embodiment of the present disclosure provides a data conversion method, including:

[0040] The conversion module receives an initial data signal, and performs parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal;

[0041] receiving a compensation signal through an adjustment module, and performing compensation processing on the intermediate data signal according to the compensation signal to reduce a signal swing of the intermediate data signal;

[0042] The intermediate data signal after the compensation process is received through a transmission module, and a driving enhancement process is performed on the intermediate data signal after the compensation process to obtain a target data signal.

[0043] In a third aspect, an embodiment of the present disclosure provides a memory, comprising a data conversion circuit as described in any one of the first aspects.

[0044] The disclosed embodiment provides a data conversion circuit, method and memory, the circuit includes a conversion module, an adjustment module and a transmission module, one end of the adjustment module is used to receive a compensation signal, and the other end of the adjustment module is connected to the output end of the conversion module and the input end of the transmission module respectively, wherein: the conversion module is used to receive an initial data signal, and perform parallel-to-serial processing on the initial data signal to obtain an intermediate data signal; the adjustment module is used to perform compensation processing on the intermediate data signal according to the compensation signal to reduce the signal swing of the intermediate data signal; the transmission module is used to perform drive enhancement processing on the intermediate data signal after the compensation processing to obtain a target data signal. In this way, by setting an adjustment module in the data conversion circuit, the adjustment module performs compensation processing on the intermediate data signal according to the compensation signal, which can reduce the signal swing of the intermediate data signal, that is, reduce the signal swing of the connection node of the conversion module and the transmission module, thereby increasing the signal bandwidth, and finally achieving the purpose of transmitting high-frequency data, and improving the high-frequency performance of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a schematic diagram of the composition structure of a parallel-to-serial circuit;

[0046] Figure 2 A schematic diagram of the structure of a data conversion circuit provided in an embodiment of the present disclosure Figure 1 ;

[0047] Figure 3 A schematic diagram of the structure of a data conversion circuit provided in an embodiment of the present disclosure Figure 2;

[0048] Figure 4 A schematic diagram of the structure of a data conversion circuit provided in an embodiment of the present disclosure Figure 3 ;

[0049] Figure 5 A schematic diagram of the structure of a data conversion circuit provided in an embodiment of the present disclosure Figure 4 ;

[0050] Figure 6 A schematic diagram of the structure of a data conversion circuit provided in an embodiment of the present disclosure Figure 5 ;

[0051] Figure 7 A schematic diagram of the structure of a data conversion circuit provided in an embodiment of the present disclosure Figure 6 ;

[0052] Figure 8 A specific structural diagram of a data conversion circuit provided in an embodiment of the present disclosure Figure 1 ;

[0053] Fig. 9 A specific structural diagram of a data conversion circuit provided in an embodiment of the present disclosure Figure 2 ;

[0054] Fig.10 A schematic diagram of a specific structure of a conversion module provided in an embodiment of the present disclosure;

[0055] Fig.11 A signal timing diagram provided for an embodiment of the present disclosure;

[0056] Fig.12 A schematic diagram of the structure of a data conversion circuit provided in an embodiment of the present disclosure Figure 7 ;

[0057] Fig.13 A specific structural diagram of a data conversion circuit provided in an embodiment of the present disclosure Figure 3 ;

[0058] Fig.14 A flowchart of a data conversion method provided by an embodiment of the present disclosure;

[0059] Fig.15 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0062] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0063] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0064] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0065] Dynamic Random Access Memory (DRAM);

[0066] Double Data Rate (DDR);

[0067] Positive channel Metal Oxide Semicond-uctor field effect transistor (PMOS tube);

[0068] N-type metal oxide semiconductor field effect transistor (NMOS tube);

[0069] D flip-flop (D flip-flop, DFF).

[0070] Figure 1 Figure 1 is a schematic diagram of the structure of a parallel-to-serial circuit. Figure 1 As shown, the parallel-to-serial circuit 10 is a circuit for converting four parallel data into serial data, including four P2S4tol sub-circuits, which respectively receive four parallel data: DataER, DataEF, DataOR and DataOF, and respectively receive four clock signals: SedCKER, SedCKEF, SedCKOR and SedCKOF. The four P2S4tol sub-circuits respectively sample the four parallel data according to the four clock signals and output serial data at the PupMid node.

[0071] The serial data of the PupMid node is then driven and enhanced by the inverter X1 and the inverter X2, and finally the serial data DataPu is obtained. At the same time, the NAND gate Xfb is connected in parallel with the inverter X1, and controls whether the serial data can be transmitted normally according to the DqRstN signal.

[0072] As the data rate increases, for example, from LPDDR4 4266Mbps to LPDDR5 6400Mbps, the performance of this circuit has encountered a bottleneck due to device performance limitations. The main reason is that the PupMid node not only has to connect to the four P2S4to1 sub-circuits, but also has to connect to the output devices X1 and Xfb, which results in a large parasitic capacitance of the PupMid node, thus limiting the high-frequency performance of the circuit. In order to improve the high-frequency performance of this circuit, one method is to reduce the parasitic capacitance of the PupMid node through the layout, but due to structural limitations, the parasitic capacitance cannot be reduced infinitely. It can be improved but there is a bottleneck.

[0073] Based on this, the embodiment of the present disclosure provides a data conversion circuit, which includes a conversion module, an adjustment module and a transmission module, wherein one end of the adjustment module is used to receive a compensation signal, and the other end of the adjustment module is connected to the output end of the conversion module and the input end of the transmission module respectively, wherein: the conversion module is used to receive an initial data signal, and perform parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal; the adjustment module is used to perform compensation processing on the intermediate data signal according to the compensation signal to reduce the signal swing of the intermediate data signal; the transmission module is used to perform drive enhancement processing on the intermediate data signal after the compensation processing to obtain a target data signal. In this way, by setting an adjustment module in the data conversion circuit, the adjustment module performs compensation processing on the intermediate data signal according to the compensation signal, which can reduce the signal swing of the intermediate data signal, that is, reduce the signal swing of the connection node of the conversion module and the transmission module, thereby increasing the signal bandwidth, and finally achieving the purpose of transmitting high-frequency data, and improving the high-frequency performance of the circuit.

[0074] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0075] In one embodiment of the present disclosure, see Figure 2 , which shows a schematic diagram of the composition structure of a data conversion circuit provided by an embodiment of the present disclosure Figure 1 .like Figure 2 As shown, the data conversion circuit 20 includes a conversion module 201, an adjustment module 202 and a transmission module 203, one end of the adjustment module 202 is used to receive the compensation signal, and the other end of the adjustment module 202 is connected to the output end of the conversion module 201 and the input end of the transmission module 203, respectively, wherein:

[0076] The conversion module 201 is used to receive the initial data signal, and perform parallel-to-serial processing on the initial data signal to obtain an intermediate data signal;

[0077] An adjustment module 202, configured to perform compensation processing on the intermediate data signal according to the compensation signal to reduce the signal swing of the intermediate data signal;

[0078] The transmission module 203 is used to perform driving enhancement processing on the intermediate data signal after the compensation processing to obtain a target data signal.

[0079] It should be noted that, in the data conversion circuit 20, the conversion module 201 receives the parallel initial data signal, converts the parallel initial data signal into a serial intermediate data signal, and the transmission module 203 drives and enhances the serial intermediate data signal to obtain a serial target data signal. That is, in the embodiment of the present disclosure, the initial data signal is a parallel data signal, and the intermediate data signal and the target data signal are both serial data signals.

[0080] It should also be noted that if Figure 2 As shown, the output end of the conversion module 201, the input end of the transmission module 203 and one end of the adjustment module 202 are connected to the same node, and the signal at the node is an intermediate data signal. Since there are many devices connected to the node, the parasitic capacitance of the node is large, which limits the high-frequency characteristics of the device. At this time, the adjustment module 202 can perform compensation processing on the node according to the received compensation signal to reduce the signal swing of the node, that is, to perform compensation processing on the intermediate data signal to reduce the signal swing of the intermediate data signal. In this way, since the signal swing is reduced, the signal bandwidth is increased, and the high-frequency performance of the circuit can be improved, so as to achieve the purpose of transmitting high-frequency data.

[0081] It should also be noted that the compensation signal is usually a signal with a level state opposite to that of the intermediate data signal. For example, if the intermediate data signal is at a high level and the compensation signal is at a low level, the low-level compensation signal will affect the voltage of the intermediate data signal through the adjustment module 202, so that the voltage of the intermediate data signal is slightly lower than the original high level; similarly, when the intermediate data signal is at a low level and the compensation signal is at a high level, the compensation signal will increase the voltage of the intermediate data signal through the adjustment module 202. Finally, the swing amplitude of the intermediate data signal can be reduced, thereby realizing the transmission of high-frequency data.

[0082] For the adjustment module 202, in a possible implementation, as Figure 3 As shown, the adjustment module 202 may include a transmission gate module 2021 (also called a transmission gate, transmission tube), one end of the transmission gate module 2021 is used to receive the compensation signal, the other end of the transmission gate module 2021 is connected to the output end of the conversion module 201 and the input end of the transmission module 203 respectively, and the control end of the transmission gate module 2021 is used to receive the enable control signal, wherein:

[0083] When the enable control signal is in a valid state, the transmission gate module 2021 is turned on to perform compensation processing on the intermediate data signal according to the compensation signal; or, when the enable control signal is in an invalid state, the transmission gate module 2021 is turned off.

[0084] It should be noted that if Figure 3 As shown, the adjustment module 202 can be implemented by a transmission gate module 2021. At this time, the compensation signal acts on the intermediate data signal through the transmission gate module 2021 to reduce the signal swing of the intermediate data signal.

[0085] It should also be noted that the embodiment of the present disclosure mainly performs compensation processing on the intermediate data signal when transmitting a high-frequency signal to meet the need of the circuit to transmit a high-frequency signal. In the case where there is no need to transmit a high-frequency signal, the intermediate data signal may not be compensated. Therefore, the conduction of the transmission gate module 2021 can also be controlled by an enable control signal, so that only when the signal swing of the intermediate data signal needs to be reduced, the enable control signal is in a valid state, and the transmission gate module 2021 is turned on at this time; when the compensation processing of the intermediate data signal is not needed, the enable control signal is in an invalid state, and the transmission gate module 2021 will not be turned on at this time, and the intermediate data signal will not be compensated.

[0086] In this way, by controlling the transmission gate module 2021 through the enable control signal, not only can the signal swing of the intermediate data signal be reduced to meet the needs of transmitting high-frequency data, but the transmission gate module 2021 can also be turned off in other scenarios to save circuit power consumption, meet the usage requirements of various scenarios, and achieve flexible control.

[0087] Further, for the transmission gate module 2021, if Figure 4 As shown, the transmission gate module 2021 includes an NMOS tube (N1) and a PMOS tube (P1), a first end of the NMOS tube is connected to a first end of the PMOS tube as one end of the transmission gate module 2021, and a second end of the NMOS tube is connected to a second end of the PMOS tube as the other end of the transmission gate module 2021;

[0088] The control end of the transmission gate module 2021 includes a gate end of an NMOS tube and a gate end of a PMOS tube, the gate end of the NMOS tube is connected to a first enable control signal, the gate end of the PMOS tube is connected to a second enable control signal, and the first enable control signal and the second enable control signal are inverted signals to each other.

[0089] It should be noted that if Figure 4 As shown, the transmission gate module 2021 can be composed of an NMOS tube and a PMOS tube connected. In this case, the gate terminals of the NMOS tube and the PMOS tube are respectively used as the two control terminals of the transmission gate module 2021, and accordingly, the enable control signal includes a pair of inverted signals: a first enable control signal and a second enable control signal; the first end of the NMOS tube is connected to the first end of the PMOS tube as one end of the transmission gate module 2021 receiving the compensation signal, and the second end of the NMOS tube is connected to the second end of the PMOS tube as the other end of the transmission gate module 2021 connected to the output end of the conversion module 201 and the input end of the transmission module 203.

[0090] In this way, for the first enable control signal and the second enable control signal, the effective state of the first enable control signal can be a high level state (logic "1"), and the effective state of the second enable control signal can be a low level state (logic "0"). When the first enable control signal is in a high level state and / or the second enable control signal is in a low level state, the NMOS tube and / or the PMOS tube is turned on, so that the compensation signal can be transmitted to the node where the intermediate data signal is located, and the compensation processing of the intermediate data signal is realized; when the first enable control signal is in a low level state and the second enable control signal is in a high level state, both the NMOS tube and the PMOS tube are not turned on, the transmission gate module 2021 is turned off, and the compensation signal will not be transmitted to the node where the intermediate data signal is located. At this time, the intermediate data signal will not be compensated.

[0091] Since the first enable control signal and the second enable control signal are mutually inverted signals, the first enable control signal can be inverted into the second enable control signal through a NOT gate. Figure 4 Based on the circuit shown, Figure 5As shown, the adjustment module 202 may further include a first NOT gate 2022, the input end of the first NOT gate 2022 is connected to the gate end of the NMOS tube, and the output end of the first NOT gate 2022 is connected to the gate end of the PMOS tube, wherein:

[0092] The first NOT gate 2022 is used to receive the first enable control signal and invert the first enable control signal to obtain a second enable control signal.

[0093] It should be noted that if Figure 5 As shown, the input end of the first NOT gate 2022 is connected to the gate end of the NMOS tube, both of which are used to receive the first enable control signal, and the output end of the first NOT gate 2022 is connected to the gate end of the PMOS tube, so that the first NOT gate 2022 can provide the second enable control signal obtained by inverting the first enable control signal to the gate end of the PMOS tube.

[0094] It should also be noted that from Figure 5 It can be seen that for the transmission gate module 2021, the two control terminals (the gate terminal of the PMOS tube and the gate terminal of the NMOS tube) receive the first enable control signal and the second enable control signal respectively, while for the adjustment module 202 as a whole, only one first enable control signal needs to be received. In this way, since the transmission gate module can be turned on only in the high-speed mode of transmitting high-frequency data, the level state of the first enable control signal can be controlled. In the high-speed mode, the first enable control signal is high level (logic "1") and is in a valid state, so that the transmission gate module 2021 is turned on, thereby reducing the signal swing of the intermediate data signal; in the non-high-speed mode, the first enable control signal is low level (logic "0") and is in an invalid state, and the transmission gate module 2021 will not be turned on, saving power consumption. It can be seen that whether the first enable control signal is valid is determined according to whether high-frequency data is currently transmitted, thereby turning on or off the transmission gate module 2021. Therefore, the first enable control signal can also be called a high-speed enable signal (High Speed ​​Enable, HSEn).

[0095] It should also be noted that the first NOT gate 2022 can also be connected in the following manner: the input end of the first NOT gate 2022 is connected to the gate end of the PMOS tube, both for receiving the second enable control signal, and the output end of the first NOT gate is connected to the gate end of the NMOS tube, for outputting the first enable control signal. At this time, the adjustment module 202 as a whole only needs to receive a second enable control signal, and the second enable control signal is a high-speed enable signal, and its effective state is a low level (logic "0"), and its invalid state is a high level (logic "1"). The control of the transmission gate module 2021 can also be achieved.

[0096] For the adjustment module 202, in another possible implementation, as Figure 6 As shown, the adjustment module 202 may include a resistance module 2023, one end of the resistance module 2023 is used to receive the compensation signal, and the other end of the resistance module 2023 is connected to the output end of the conversion module 201 and the input end of the transmission module 203, respectively, wherein:

[0097] The resistor module 2023 is used to perform compensation processing on the intermediate data signal according to the compensation signal to reduce the signal swing of the intermediate data signal.

[0098] It should be noted that if Figure 6 As shown, the adjustment module 202 can also be implemented by a resistor module 2023. The resistor module 2023 works in a similar manner to the aforementioned transmission gate module 2021. The compensation signal is transmitted to the node where the intermediate data signal is located through the resistor module 2023. The compensation signal is usually opposite to the level state of the intermediate data signal, so that for a high-level intermediate data signal, its voltage can be pulled down, and for a low-level intermediate data signal, its voltage can be pulled up, and finally the signal swing of the intermediate data signal is reduced to achieve the purpose of transmitting a high-frequency signal.

[0099] It should also be noted that the resistor module 2023 can be a fixed resistor or a variable resistor, or a combination of a fixed resistor and a variable resistor, which is not specifically limited here. In this way, the compensation degree of the intermediate data signal can be adjusted by adjusting the resistance value of the variable resistor, thereby achieving flexible control.

[0100] For example, the frequency level of the data can be divided into low frequency, first-level high frequency and second-level high frequency from low to high. In the low-frequency scenario, the resistance value of the resistor module 2023 can be set very high, so that the compensation signal can hardly pass through, which is equivalent to a disconnected state, so that the intermediate data signal is almost not compensated; in the first-level high-frequency scenario, the resistance value of the resistor module 2023 can be set to the first resistance value, so that the compensation signal can pass through but there is a certain loss, thereby achieving a certain degree of compensation for the intermediate data signal; in the second-level high-frequency scenario, the resistance value of the resistor module 2023 can be set to the second resistance value (the second resistance value is smaller than the first resistance value), so that the compensation signal can pass through with very low loss, thereby achieving a higher degree of compensation for the intermediate data signal.

[0101] Further, for the transmission module 203, if Figure 7 As shown, in some embodiments, the transmission module 203 includes a first transmission submodule 2031 and a second transmission submodule 2032, the input end of the first transmission submodule 2031 is connected to the output end of the conversion module 201, and the output end of the first transmission submodule 2031 is connected to the input end of the second transmission submodule 2032, wherein:

[0102] The first transmission submodule 2031 is used to perform inversion processing on the intermediate data signal after the compensation processing to obtain an initial target data signal;

[0103] The second transmission submodule 2032 is used to perform inversion processing on the initial target data signal to obtain a target data signal.

[0104] It should be noted that if Figure 7 As shown, in the transmission module 203, the first transmission submodule 2031 is connected to the conversion module 201 and the adjustment module 202 respectively, and is used to receive the intermediate data signal after compensation processing, and perform inversion processing to obtain the initial target data signal and then send it to the second transmission submodule 2032; after receiving the initial target data signal, the second transmission submodule performs inversion processing again to invert the initial target data signal into the target data signal. Since the intermediate data signal is serial data, the initial target data signal and the target data signal are also serial data signals.

[0105] In this way, after two-stage inversion processing by the first transmission submodule 2031 and the second transmission submodule 2032, the level state of the target data signal finally obtained remains unchanged compared with the intermediate data signal, but the driving capability is enhanced, which is more conducive to the transmission of the data signal.

[0106] Since the compensation signal is usually a signal with a level state opposite to that of the intermediate data signal, and the initial target data signal is obtained by inverting the intermediate data signal, the initial target data signal can be used as the compensation signal in the embodiment of the present disclosure. Figure 7 As shown, in some embodiments, one end of the adjustment module 202 is connected to the output end of the first transmission submodule 2031, and the other end of the adjustment module 202 is connected to the input end of the first transmission submodule 2032, wherein:

[0107] The first transmission submodule 2031 is further configured to determine the initial target data signal as the compensation signal.

[0108] It should be noted that if Figure 7As shown, the output end of the first transmission submodule 2031 can be connected to one end of the adjustment module 202, the node where the intermediate data signal is located is recorded as the PupMid node, the node where the initial target data signal is located is recorded as the PupMidN node, and the adjustment module 202 is connected between the PupMid node and the PupMidN node. In this way, for the data conversion circuit 20, the initial data signal is processed into an intermediate data signal by the conversion module 201, and the intermediate data signal is inverted by the first conversion submodule 2031 to be the initial target data signal. The initial target data signal is used as a compensation signal, which is an inverted signal with the intermediate data signal. The adjustment module 202 performs compensation processing on the intermediate data signal according to the initial target data signal, so that the signal swing of the intermediate data signal is reduced, that is, the signal swing of the PupMid node is reduced, thereby improving the high-frequency performance of the circuit and the speed of data transmission of the circuit.

[0109] Further, Figure 8 For Figure 5 Based on the above, a specific structure diagram of a data conversion circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 1 , Fig. 9 For Figure 6 Based on the above, a specific structure diagram of a data conversion circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 2 . Figure 8 The adjustment module 202 is implemented by a transmission gate module 2021 and a first NOT gate 2022. Fig. 9 The adjustment module 202 is implemented by a resistance module 2023 .

[0110] It should be noted that in Figure 8 In the embodiment, the output end of the first transmission submodule 2031 is connected to the first end of the PMOS tube and the NMOS tube (the first end of the transmission gate module 2021). Fig. 9 In the embodiment, the output end of the first transmission submodule 2031 is connected to one end of the resistance module 2023. In this way, the first transmission submodule 2031 can directly provide the output initial target data signal as a compensation signal to the adjustment module 202 for compensating the intermediate data signal.

[0111] like Figure 8 or Fig. 9As shown, in some embodiments, the first transmission submodule 2031 includes a second NOT gate 2033 and a first NAND gate 2034, the second transmission submodule 2032 includes a third NOT gate 2035, the first input end of the first NAND gate 2034 is used to receive a transmission control signal, the second input end of the first NAND gate 2034 is connected to the output end of the second NOT gate 2033 and the input end of the third NOT gate 2035, and the output end of the first NAND gate 2034 is connected to the input end of the second NOT gate 2033; wherein, the input end of the second NOT gate 2033 serves as the input end of the first transmission submodule 2031, the output end of the second NOT gate 2033 serves as the output end of the first transmission submodule 2031, the input end of the third NOT gate 2035 serves as the input end of the second transmission submodule 2032, and the output end of the third NOT gate 2035 serves as the output end of the second transmission submodule 2032.

[0112] It should be noted that if Figure 8 or Fig. 9 As shown, in the first transmission submodule 2031, the first NAND gate 2034 and the second NAND gate 2033 are connected end to end, the second input end of the first NAND gate 2034 is connected to the PupMidN node, and the output end is connected to the PupMid node.

[0113] In addition to receiving the initial target data signal output by the second NOT gate 2033 through the second input terminal, the first NAND gate 2034 also receives a transmission control signal (also called DQ reset N, DqRstN) through the first input terminal. The transmission control signal can control whether the data can be normally transmitted by the first transmission submodule 2031. When the transmission control signal is at a high level (logic "1"), the data can be transmitted normally, and when the transmission control signal is at a low level (logic "0"), the data cannot be transmitted normally. In this way, the embodiment of the present disclosure can also control whether the intermediate data signal is normally transmitted as the initial target data signal through the first NAND gate 2034 and the transmission control signal, which increases the flexibility of data conversion and avoids problems such as interference of the circuit caused by erroneous transmission of data when data does not need to be transmitted.

[0114] That is, when the level of the transmission control signal is high, data transmission is not affected, and the first NAND gate 2034 and the second NOT gate 2033 form a latch to latch data. When the level of the transmission control signal is low, the PupMid node will always be high, and data cannot be transmitted normally.

[0115] like Figure 8 or Fig. 9As shown, in some embodiments, for the conversion module 201, the conversion module 201 may include a first conversion submodule 2011, a second conversion submodule 2012, a third conversion submodule 2013 and a fourth conversion submodule 2014, and the initial data signal may include first initial data, second initial data, third initial data and fourth initial data, wherein:

[0116] The first conversion submodule 2011 is used to receive first initial data and a first clock signal, and perform sampling processing on the first initial data according to the first clock signal to obtain first intermediate data;

[0117] The second conversion submodule 2012 is used to receive the second initial data and the second clock signal, and perform sampling processing on the second initial data according to the second clock signal to obtain second intermediate data;

[0118] The third conversion submodule 2013 is used to receive third initial data and a third clock signal, and perform sampling processing on the third initial data according to the third clock signal to obtain third intermediate data;

[0119] The fourth conversion submodule 2014 is used to receive fourth initial data and a fourth clock signal, and perform sampling processing on the fourth initial data according to the fourth clock signal to obtain fourth intermediate data;

[0120] Among them, the phases of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are 0 degrees, 90 degrees, 180 degrees and 270 degrees respectively, and the first intermediate data, the second intermediate data, the third intermediate data and the fourth intermediate data constitute the intermediate data signal.

[0121] It should be noted that if Figure 8 or Fig. 9 As shown, taking the initial data signal including four parallel data as an example, at this time, the conversion module 201 includes four conversion submodules (also recorded as P2S4tol subcircuits), which are respectively used to sample and process the four parallel data to output four intermediate data to form intermediate data signals. Among them, the output end of the first conversion submodule 2011, the output end of the second conversion submodule 2012, the output end of the third conversion submodule 2013 and the output end of the fourth conversion submodule 2014 are connected to the PupMid node as the output end of the conversion module 201, and are used to output the intermediate data signal.

[0122] It should also be noted that in each conversion submodule, the clock signal is used to control the sampling time of the corresponding initial data, so as to ensure the timing between the four intermediate data outputs to form the intermediate data signal. Fig.10A specific structural diagram of a conversion module 201 provided by an embodiment of the present disclosure is shown, wherein the conversion module 201 may also include a clock signal generator 2015, the clock signal generator 2015 receives a first clock signal (SedCKER), a second clock signal (SedCKEF), a third clock signal (SedCKOR) and a fourth clock signal (SedCKOF), generates a first clock selection signal (SedCKERN) according to the rising edge of the first clock signal (SedCKER), generates a second clock selection signal (SedCKEFN) according to the rising edge of the second clock signal (SedCKEF), generates a third clock selection signal (SedCKORN) according to the rising edge of the third clock signal (SedCKOR), generates a fourth clock selection signal (SedCKOFN) according to the rising edge of the fourth clock signal (SedCKOF), and the pulse width of each clock selection signal is smaller than the pulse width of the corresponding clock signal. The signal timing of each clock signal and clock selection signal can refer to Fig.10 shown.

[0123] The first conversion submodule 2011 may include a first trigger (DFF1) and a first switch (S1), the second conversion submodule 2012 may include a second trigger (DFF2) and a second switch (S2), the third conversion submodule 2013 may include a third trigger (DFF3) and a third switch (S3), and the fourth conversion submodule 2014 may include a fourth trigger (DFF4) and a fourth switch (S4).

[0124] In the first conversion submodule 2011, the first trigger DFF1 samples the first initial data DataER at the rising edge of the first clock signal SedCKER. When the first selection clock signal SedCKERN is in a high level state, the first switch S1 is closed, so that the sampled signal passes through the first switch S1 to obtain the first intermediate data D1'. Similarly, in the second conversion submodule 2012, the second trigger DFF2 samples the second initial data DataEF at the rising edge of the second clock signal SedCKEF, and the second switch S2 is closed while the second selection clock signal SedCKEFN is in a high level state, so that the sampled signal passes through the second switch S2 to obtain the second intermediate data D2'; in the third conversion submodule 2013, the third trigger DFF3 samples the third initial data DataOR at the rising edge of the third clock signal SedCKOR, and the third switch S3 is closed while the third selection clock signal SedCKORN is in a high level state, so that the sampled signal passes through the third switch S3 to obtain the third intermediate data D3'; in the fourth conversion submodule 2014, the fourth trigger DFF4 samples the fourth initial data DataOF at the rising edge of the fourth clock signal SedCKOF, and the fourth switch S4 is closed while the fourth selection clock signal SedCKOFN is in a high level state, so that the sampled signal passes through the fourth switch S4 to obtain the fourth intermediate data D4'.

[0125] like Fig.10 and Fig.11 As shown, due to the timing differences between the four clock selection signals, after sampling and outputting the parallel first initial data DataER, the second initial data DataEF, the third initial data DataOR and the fourth initial data DataOF, the four intermediate data can be output in sequence, and finally a serial intermediate data signal is obtained at the PupMid node.

[0126] Furthermore, the embodiments of the present disclosure can also be applied to scenarios where there is a difference. Fig.12 As shown, in some embodiments, the conversion module 201 includes a first conversion module 204 and a second conversion module 205, the initial data signal includes a first initial data signal and a second initial data signal, and the first initial data signal and the second initial data signal are a pair of differential signals, and the intermediate data signal includes a first intermediate data signal and a second intermediate data signal, wherein:

[0127] A first conversion module 204 is used to receive a first initial data signal, and perform parallel-to-serial processing on the first initial data signal to obtain a first intermediate data signal;

[0128] The second conversion module 205 is used to receive the second initial data signal, and perform parallel-to-serial processing on the second initial data signal to obtain a second intermediate data signal.

[0129] It should be noted that, in the embodiment of the present disclosure, the initial data signal may be a pair of differential signals (or inverted signals), including a first initial data signal and a second initial data signal, and both the first initial data signal and the second initial data signal are parallel data signals; the first conversion module 204 processes the first initial data signal into a serial first intermediate data signal, and the second conversion module 205 processes the second initial data signal into a serial second intermediate data signal. It can be understood that the first intermediate data signal and the second intermediate data signal are also a pair of differential signals, and the level states of the two are opposite.

[0130] At this time, if Fig.12 As shown, one end of the adjustment module 202 is connected to the output end of the first conversion module 204, and the other end of the adjustment module 202 is connected to the output end of the second conversion module 205. The second intermediate data signal is used as a compensation signal for compensating the first intermediate data signal, and the first intermediate data signal is used as a compensation signal for compensating the second intermediate data signal. In other words, the compensation signal includes the first intermediate data signal and the second intermediate data signal, wherein:

[0131] The adjustment module 202 is used to compensate the second intermediate data signal according to the first intermediate data signal to reduce the signal swing of the second intermediate data signal; and to compensate the first intermediate data signal according to the second intermediate data signal to reduce the signal swing of the first intermediate data signal.

[0132] It can be seen that for application scenarios with differentials, the embodiment of the present disclosure can also connect the adjustment module 202 between two differential signals (the first intermediate data signal and the second intermediate data signal) to simultaneously reduce the signal swing of the first intermediate data signal and the second intermediate data signal.

[0133] Accordingly, the target data signal includes a first target data signal and a second target data signal, and the transmission module 203 includes a first transmission module 206 and a second transmission module 207, wherein:

[0134] A first transmission module 206 is used to perform a driving enhancement process on the first intermediate data signal after the compensation process to obtain a first target data signal;

[0135] The second transmission module 207 is used to perform driving enhancement processing on the second intermediate data signal after the compensation processing to obtain a second target data signal.

[0136] One end of the adjustment module 202 is connected to the output end of the first conversion module 204 and the input end of the first transmission module 206 , respectively. The other end of the adjustment module 202 is connected to the output end of the second conversion module 205 and the input end of the second transmission module 207 , respectively.

[0137] It should be noted that if Fig.12 As shown, the connection node between the first conversion module 204 and the first transmission module 206 is recorded as the PupMid1 node, and the connection node between the second conversion module 205 and the second transmission module 207 is recorded as the PupMid2 node. The adjustment module 202 is connected between the PupMid1 node and the PupMid2 node, and can not only perform compensation processing on the first intermediate data signal according to the second intermediate data signal, and reduce the signal swing of the first intermediate data signal, that is, reduce the signal swing of the PupMid1 node, but also perform compensation processing on the second intermediate data signal according to the first intermediate data signal, and reduce the signal swing of the second intermediate data signal, that is, reduce the signal swing of the PupMid2 node, and then obtain the first target data signal (also written as DataPu) through the first transmission module 206, and obtain the second target data signal (also written as DataPd) through the second transmission module 207. It can be understood that the first target data signal and the second target data signal are also a pair of differential signals, and the two are inverse signals to each other. Finally, it can be achieved that both the first transmission path (the first conversion module 204 and the second transmission module 206) and the second transmission path (the second conversion module 205 and the second transmission module 207) can transmit high-frequency signals, thereby effectively improving the high-frequency performance of the circuit.

[0138] Further, for an application scenario with a difference, taking the adjustment module 202 including the transmission gate module 2021 and the first NOT gate 2022 as an example, see Fig.13 , which shows a specific structural schematic diagram of a data conversion circuit provided by an embodiment of the present disclosure Figure 3 .like Fig.13 As shown, the structures and functions of the first conversion module 204 and the second conversion module 205 are similar to those of Figure 8 or Fig. 9 The conversion module 201 is the same as that in FIG. 1 , and its specific structure and function can also refer to Fig.10 and Fig.11 At the same time, the first conversion module 204 and the second conversion module 205 can also share the same clock signal generator 2015; the structures and functions of the first transmission module 206 and the second transmission module 207 are the same as Figure 8 or Fig. 9 The transmission module 203 in FIG. Specific functional description thereof will not be repeated here.

[0139] The difference in the differential scenario lies in the connection method of the adjustment module 202. At this time, the adjustment module 202 is connected between the PupMid1 node and the PupMid2 node, so that the signal swing of the PupMid1 node can be reduced according to the second intermediate data signal, and the signal swing of the PupMid2 node can be reduced according to the first intermediate data signal.

[0140] Among them, the four initial data received by the first conversion module 204 are respectively: DataER, DataEF, DataOR and DataOF, and the four initial data received by the second conversion module 205 are respectively DataERN, DataEFN, DataORN and DataOFN. It can be understood that DataER and DataERN are a pair of inverted signals, and the clock signal for sampling the pair of inverted signals is SedCKER; DataEF and DataEFN are a pair of inverted signals, and the clock signal for sampling the pair of inverted signals is SedCKEF; DataOR and DataORN are a pair of inverted signals, and the clock signal for sampling the pair of inverted signals is SedCKOR; DataOF and DataOFN are a pair of inverted signals, and the clock signal for sampling the pair of inverted signals is SedCKOF.

[0141] Similarly, for application scenarios with differences, the adjustment module 202 can be implemented by the resistance module 2023. In this case, the resistance module 2023 is connected between the PupMid1 node and the PupMid2 node. Figure 8 or Fig. 9 In the connection mode, two adjustment modules 202 are set to reduce the signal swing of the PupMid1 node and the PupMid2 node, which is also conducive to transmitting high-frequency data and improving the high-frequency performance of the circuit. Fig.13 For a more detailed description, please refer to the above Figures 8 to 10 As for understanding, I will not go into details here.

[0142] In short, the data conversion circuit provided by the embodiment of the present disclosure can improve the conversion rate from parallel data to serial data. In order to improve the high-frequency performance of the data conversion circuit, the high-frequency performance is improved by reducing the swing of the PupMid node. For application scenarios where there is no difference, it is mainly achieved by an adjustment module connected between the PupMid node and the PupMidN node. In high-speed mode, the HSEn signal is high, and the transmission tube is turned on, which causes the swing of the PupMid node to decrease and the signal bandwidth to increase, thereby achieving the purpose of transmitting high-frequency data; or, it is achieved by a resistor module connected between the PupMid node and the PupMidN node. For scenarios where there is a difference, since the same data needs to be output differentially, when the PupMid1 node is high (High), the PdnMid2 node is (Low), so a transmission tube can be added between the PupMid1 node and the PdnMid2 node to simultaneously reduce the voltage swing of the PupMid1 node and the PdnMid2 node to achieve the purpose of transmitting high-speed data.

[0143] The disclosed embodiment provides a data conversion circuit, which includes a conversion module, an adjustment module and a transmission module, wherein one end of the adjustment module is used to receive a compensation signal, and the other end of the adjustment module is connected to the output end of the conversion module and the input end of the transmission module respectively, wherein: the conversion module is used to receive an initial data signal, and perform parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal; the adjustment module is used to perform compensation processing on the intermediate data signal according to the compensation signal to reduce the signal swing of the intermediate data signal; the transmission module is used to perform drive enhancement processing on the intermediate data signal after the compensation processing to obtain a target data signal. In this way, by setting an adjustment module in the data conversion circuit, the adjustment module performs compensation processing on the intermediate data signal according to the compensation signal, which can reduce the signal swing of the intermediate data signal, that is, reduce the signal swing of the connection node between the conversion module and the transmission module, thereby increasing the signal bandwidth, and finally achieving the purpose of transmitting high-frequency data, and improving the high-frequency performance of the circuit.

[0144] In another embodiment of the present disclosure, see Fig.14 , which shows a flow chart of a data conversion method provided by an embodiment of the present disclosure. Fig.14 As shown, the method may include:

[0145] S1001: receiving an initial data signal through a conversion module, and performing parallel-to-serial processing on the initial data signal to obtain an intermediate data signal.

[0146] S1002: Receive a compensation signal through an adjustment module, and perform compensation processing on the intermediate data signal according to the compensation signal to reduce a signal swing of the intermediate data signal.

[0147] S1003: receiving the compensated intermediate data signal through the transmission module, and performing driving enhancement processing on the compensated intermediate data signal to obtain a target data signal.

[0148] In some embodiments, compensating the intermediate data signal according to the compensation signal includes: turning on the transmission gate module when the enable control signal is in a valid state to compensate the intermediate data signal according to the compensation signal; or turning off the transmission gate module when the enable control signal is in an invalid state.

[0149] In some embodiments, the enable control signal includes a first enable control signal and a second enable control signal. The method may further include: receiving the first enable control signal through a first NOT gate, and inverting the first enable control signal to obtain a second enable control signal.

[0150] In some embodiments, performing compensation processing on the intermediate data signal according to the compensation signal includes: performing compensation processing on the intermediate data signal according to the compensation signal through a resistance module to reduce the signal swing of the intermediate data signal.

[0151] In some embodiments, performing drive enhancement processing on the intermediate data signal after compensation processing to obtain a target data signal includes:

[0152] Performing inversion processing on the intermediate data signal after the compensation processing by the first transmission submodule to obtain an initial target data signal;

[0153] The initial target data signal is inverted by the second transmission submodule to obtain a target data signal.

[0154] In some embodiments, the method may further include: determining the initial target data signal as the compensation signal.

[0155] In some embodiments, performing parallel-to-serial processing on the initial data signal to obtain the intermediate data signal includes:

[0156] Receiving first initial data and a first clock signal through a first conversion submodule, and sampling and processing the first initial data according to the first clock signal to obtain first intermediate data;

[0157] receiving the second initial data and the second clock signal through the second conversion submodule, and performing sampling processing on the second initial data according to the second clock signal to obtain second intermediate data;

[0158] receiving third initial data and a third clock signal through a third conversion submodule, and performing sampling processing on the third initial data according to the third clock signal to obtain third intermediate data;

[0159] receiving fourth initial data and a fourth clock signal through a fourth conversion submodule, and performing sampling processing on the fourth initial data according to the fourth clock signal to obtain fourth intermediate data;

[0160] Among them, the phases of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are 0 degrees, 90 degrees, 180 degrees and 270 degrees respectively, and the first intermediate data, the second intermediate data, the third intermediate data and the fourth intermediate data constitute the intermediate data signal.

[0161] In some embodiments, the initial data signal includes a first initial data signal and a second initial data signal, and the first initial data signal and the second initial data signal are a pair of differential signals, the intermediate data signal includes a first intermediate data signal and a second intermediate data signal, and the initial data signal is processed from parallel to serial to obtain the intermediate data signal, including:

[0162] The first conversion module receives a first initial data signal, and performs parallel-to-serial conversion on the first initial data signal to obtain a first intermediate data signal;

[0163] The second initial data signal is received by the second conversion module, and the second initial data signal is processed from parallel to serial to obtain a second intermediate data signal.

[0164] In some embodiments, the compensation signal includes a first intermediate data signal and a second intermediate data signal, and performing compensation processing on the intermediate data signal according to the compensation signal includes:

[0165] The adjustment module compensates the second intermediate data signal according to the first intermediate data signal to reduce the signal swing of the second intermediate data signal; and compensates the first intermediate data signal according to the second intermediate data signal to reduce the signal swing of the first intermediate data signal.

[0166] In some embodiments, the target data signal includes a first target data signal and a second target data signal, and the drive enhancement process is performed on the intermediate data signal after the compensation process to obtain the target data signal, including:

[0167] Performing a driving enhancement process on the first intermediate data signal after the compensation process by a first transmission module to obtain a first target data signal;

[0168] The second intermediate data signal after the compensation process is subjected to a driving enhancement process by the second transmission module to obtain a second target data signal.

[0169] In some embodiments, the initial data signal is a parallel data signal, and the intermediate data signal and the target data signal are both serial data signals.

[0170] It should be noted that the data conversion method provided in the embodiment of the present disclosure can be applied to the data conversion circuit 20 described in the aforementioned embodiment. For details not disclosed in the embodiment of the present disclosure, please refer to the description of the aforementioned embodiment for understanding.

[0171] The disclosed embodiment provides a data conversion method, which performs compensation processing on an intermediate data signal according to a compensation signal, thereby reducing the signal swing of the intermediate data signal, thereby increasing the signal bandwidth, and ultimately achieving the purpose of transmitting high-frequency data, thereby improving the high-frequency performance of the circuit.

[0172] In another embodiment of the present disclosure, see Fig.15 , which shows a schematic diagram of the composition structure of a semiconductor memory provided by an embodiment of the present disclosure. Fig.15 As shown, the semiconductor memory 150 may at least include the data conversion circuit 20 described in any one of the aforementioned embodiments.

[0173] In some embodiments, the semiconductor memory 150 is a dynamic random access memory (DRAM) chip.

[0174] In the embodiments of the present disclosure, DRAM can not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, etc., but also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, etc., without any limitation here.

[0175] In the embodiment of the present disclosure, for the semiconductor memory 150, since it includes the data conversion circuit 20 described in the above embodiment, the signal bandwidth is increased, and finally the purpose of transmitting high-frequency data is achieved, thereby improving the performance of the memory.

[0176] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0177] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0178] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0179] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0180] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0181] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0182] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A data conversion circuit, characterized in that: It includes a conversion module, an adjustment module and a transmission module, one end of the adjustment module is used to receive a compensation signal, and the other end of the adjustment module is connected to the output end of the conversion module and the input end of the transmission module respectively, wherein: The conversion module is used to receive an initial data signal, and perform parallel-to-serial processing on the initial data signal to obtain an intermediate data signal; The adjustment module is used to perform compensation processing on the intermediate data signal according to a compensation signal to reduce the signal swing of the intermediate data signal, wherein the compensation signal is a signal having a level state opposite to that of the intermediate data signal; The transmission module is used to perform driving enhancement processing on the intermediate data signal after compensation processing to obtain a target data signal.

2. The data conversion circuit according to claim 1, characterized in that: The adjustment module includes a transmission gate module, one end of which is used to receive the compensation signal, the other end of which is connected to the output end of the conversion module and the input end of the transmission module respectively, and the control end of the transmission gate module is used to receive an enable control signal, wherein: When the enable control signal is in a valid state, the transmission gate module is turned on to perform compensation processing on the intermediate data signal according to the compensation signal; or, when the enable control signal is in an invalid state, the transmission gate module is turned off.

3. The data conversion circuit according to claim 2, characterized in that: The enable control signal includes a first enable control signal and a second enable control signal, wherein: The transmission gate module comprises an NMOS tube and a PMOS tube, the first end of the NMOS tube is connected to the first end of the PMOS tube as one end of the transmission gate module, and the second end of the NMOS tube is connected to the second end of the PMOS tube as the other end of the transmission gate module; The control end of the transmission gate module includes a gate end of the NMOS tube and a gate end of the PMOS tube, the gate end of the NMOS tube is connected to the first enable control signal, the gate end of the PMOS tube is connected to the second enable control signal, and the first enable control signal and the second enable control signal are inverted signals to each other.

4. The data conversion circuit according to claim 3, characterized in that: The adjustment module further includes a first NOT gate, an input end of the first NOT gate is connected to the gate end of the NMOS tube, and an output end of the first NOT gate is connected to the gate end of the PMOS tube, wherein: The first NOT gate is used to receive the first enable control signal and perform inversion processing on the first enable control signal to obtain the second enable control signal.

5. The data conversion circuit according to claim 1, characterized in that: The adjustment module includes a resistance module, one end of which is used to receive the compensation signal, and the other end of which is connected to the output end of the conversion module and the input end of the transmission module respectively, wherein: The resistor module is used to perform compensation processing on the intermediate data signal according to the compensation signal to reduce the signal swing of the intermediate data signal.

6. The data conversion circuit according to claim 2, characterized in that: The transmission module includes a first transmission submodule and a second transmission submodule, the input end of the first transmission submodule is connected to the output end of the conversion module, and the output end of the first transmission submodule is connected to the input end of the second transmission submodule, wherein: The first transmission submodule is used to perform inversion processing on the intermediate data signal after compensation processing to obtain an initial target data signal; The second transmission submodule is used to perform inversion processing on the initial target data signal to obtain the target data signal.

7. The data conversion circuit according to claim 6, characterized in that: One end of the adjustment module is connected to the output end of the first transmission submodule, and the other end of the adjustment module is connected to the input end of the first transmission submodule, wherein: The first transmission submodule is further configured to determine the initial target data signal as the compensation signal.

8. The data conversion circuit according to claim 6, characterized in that: The first transmission submodule includes a second NOT gate and a first NAND gate, the second transmission submodule includes a third NOT gate, the first input end of the first NAND gate is used to receive a transmission control signal, the second input end of the first NAND gate is connected to the output end of the second NOT gate and the input end of the third NOT gate, and the output end of the first NAND gate is connected to the input end of the second NOT gate; wherein the input end of the second NOT gate serves as the input end of the first transmission submodule, the output end of the second NOT gate serves as the output end of the first transmission submodule, the input end of the third NOT gate serves as the input end of the second transmission submodule, and the output end of the third NOT gate serves as the output end of the second transmission submodule.

9. The data conversion circuit according to claim 1, characterized in that: The conversion module includes a first conversion submodule, a second conversion submodule, a third conversion submodule and a fourth conversion submodule, and the initial data signal includes first initial data, second initial data, third initial data and fourth initial data, wherein: The first conversion submodule is configured to receive the first initial data and a first clock signal, and perform sampling processing on the first initial data according to the first clock signal to obtain first intermediate data; The second conversion submodule is used to receive the second initial data and a second clock signal, and perform sampling processing on the second initial data according to the second clock signal to obtain second intermediate data; The third conversion submodule is configured to receive the third initial data and a third clock signal, and perform sampling processing on the third initial data according to the third clock signal to obtain third intermediate data; The fourth conversion submodule is configured to receive the fourth initial data and a fourth clock signal, and perform sampling processing on the fourth initial data according to the fourth clock signal to obtain fourth intermediate data; Among them, the phases of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are 0 degrees, 90 degrees, 180 degrees and 270 degrees respectively, and the first intermediate data, the second intermediate data, the third intermediate data and the fourth intermediate data constitute the intermediate data signal.

10. The data conversion circuit according to claim 1, characterized in that: The conversion module includes a first conversion module and a second conversion module, the initial data signal includes a first initial data signal and a second initial data signal, and the first initial data signal and the second initial data signal are a pair of differential signals, and the intermediate data signal includes a first intermediate data signal and a second intermediate data signal, wherein: The first conversion module is used to receive the first initial data signal, and perform parallel-to-serial processing on the first initial data signal to obtain the first intermediate data signal; The second conversion module is used to receive the second initial data signal, and perform parallel-to-serial processing on the second initial data signal to obtain the second intermediate data signal.

11. The data conversion circuit according to claim 10, characterized in that: The compensation signal includes the first intermediate data signal and the second intermediate data signal, wherein: The adjustment module is used to perform compensation processing on the second intermediate data signal according to the first intermediate data signal to reduce the signal swing of the second intermediate data signal; and to perform compensation processing on the first intermediate data signal according to the second intermediate data signal to reduce the signal swing of the first intermediate data signal.

12. The data conversion circuit according to claim 11, characterized in that: The target data signal includes a first target data signal and a second target data signal, and the transmission module includes a first transmission module and a second transmission module, wherein: The first transmission module is used to perform driving enhancement processing on the first intermediate data signal after compensation processing to obtain the first target data signal; The second transmission module is used to perform driving enhancement processing on the second intermediate data signal after compensation processing to obtain the second target data signal.

13. The data conversion circuit according to claim 12, characterized in that: One end of the adjustment module is connected to the output end of the first conversion module and the input end of the first transmission module respectively, and the other end of the adjustment module is connected to the output end of the second conversion module and the input end of the second transmission module respectively.

14. The data conversion circuit according to any one of claims 1 to 13, characterized in that: The initial data signal is a parallel data signal, and the intermediate data signal and the target data signal are both serial data signals.

15. A data conversion method, characterized in that: The method comprises: The conversion module receives an initial data signal, and performs parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal; receiving a compensation signal through an adjustment module, and performing compensation processing on the intermediate data signal according to the compensation signal to reduce the signal swing of the intermediate data signal, wherein the compensation signal is a signal having a level state opposite to that of the intermediate data signal; The intermediate data signal after the compensation process is received through a transmission module, and a driving enhancement process is performed on the intermediate data signal after the compensation process to obtain a target data signal.

16. A memory, characterized in that: The memory comprises the data conversion circuit according to any one of claims 1 to 14.

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